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Lecture 4. Memory, CPLDs, and FPGAs
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Read-Only Memory (ROM)

ROM is a combinational circuit with address inputs and data outputs
 Its information is stored in the ROM when it is manufactured.
 Non-volatile memory
 Its contents are preserved even if no power is applied.
[ “Storing” 2n data and each data is b bits ]
[ 8(23) x 4 ROM ]
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ROM and Decoder

Decoders can be built using ROMs
[ 8(23) x 4 ROM can be used as a 2-to-4 decoder
with an output-polarity control A2 ]
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ROM and Decoder

The assignment pattern of decoder inputs and outputs to ROM inputs and
outputs is a consequence of the way that the truth table of a ROM is
constructed.
[ Another 8(23) x 4 ROM:
still be used as the 2-to-4 decoder with A0=POL, A1=I0. A2=I1 ]
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ROM and Multiplier

A ROM’s contents are normally specified by a file that contains one entry
for every address in the ROM.

You can usually write a simple program in a high-level language (e.g., C program)
to calculate what should be stored in the ROM.
address = 12, entry = 02
starting address of each row
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Internal ROM Structure

The mechanism used by ROMs to “store” information varies with different
ROM technologies.
3-to-8
decoder
If a diode is present,
a 1 is stored;
otherwise, a 0 is a stored.
1110 is stored
word line
bit line
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MOS ROMs

MOS ROMs actually use a transistor instead of a diode.
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Two-dimensional decoding


128(27) x 1 ROM ? 7-to-128 decoder ?
 128 7-input NAND gates !!
Two-dimensional decoding is used to reduce the decoder size
 Arranging the ROM cells in an array that is as close as possible to square
128(8x16) ROM cells
(or 128 bits)
Address
A6 A5 A4 A3 A2 A1 A0
=0 0 1 0 1 1 1
Data output?
0
0
0
0 0 0
1
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Two-dimensional decoding
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Commercial ROM types

Mask ROM
 Early IC ROMs
 Programmed by the pattern of connections and no-connections in a mask
 Expensive mask charge and 4 weeks required to obtain programmed chips
 Normally used today only in very high-volume applications
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Commercial ROM types


PROM (Programmable ROMs)
 Manufactured with all of its diodes or transistors “connected”
 Storing data in just a few minutes using a PROM programmer
EPROM (Erasable programmable ROM)
 Programmed like a PROM
 Erased to the all-1s state by exposing it to ultraviolet light using floatinggate MOS
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Commercial ROM types

EEPROM (Electrically erasable programmable ROM)
 Individual stored bits may be erased electrically
 The floating gates in an EEPROM are surrounded by a much thinner
insulating layer
 Erased by applying a voltage of the opposite polarity
 Writing takes much longer than reading (not good as read/write memory)
 Limited reprogramming because of thin insulating layers
 Typically used for storing data that must be preserved during power-off
 E.g., Default configuration data for a computer.

Flash EPROM (flash memory)
 Large EEPROMs erasing only in fixed-size blocks
 An entire block is erased “in a flash”
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Commercial ROM types
WE(write-enable)
for programming operations
OE(output-enable)
for enabling outputs
CS(chip-select)
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ROM Control Inputs and Timing
8-bit
microprocessor
that requires
128 Kbytes of
EEPROM
A[19-0]
: 20-bit address bus
( maximum address
space of 1Mbyte
(220 bytes))
32K x 8
EEPROM
The EEPROM is supposed to be located in the highest 128K of the address space
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ROM Control Inputs and Timing
CS also serves as a power-down input
CS_L=0 : active mode
CS_L=1 : standby mode
(Power is removed from the ROM.
It consumes less than 10% of
the power it uses in active mode.)
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Static RAM (SRAM)

RAM (random-access memory)



The time it takes to read or write a bit is independent of the bit’s location in the
RAM
For read/write operations
ROMs are also random-access memory (but main function is reading)

SRAM
 Once a word is written at a location, it remains stored as long as power is
applied to the chip, unless the same location is written again.

DRAM (dynamic RAM)
 The data stored at each location must be refreshed periodically by reading it
and then writing it back again, or else it disappears.
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Static RAM (SRAM)
WE(write-enable) input
: When WE is asserted,
the data inputs are written into
the selected memory location
Read : CS and OE are asserted
Write : CS and WE are asserted
SRAM cell = each bit of memory
D latch
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SRAM
1
0
0
1
1
[ 8 x 4 SRAM ]
1
1
0
1
0
0
0
1
1
1
1
1
1
Write operation
1
0
0
1
0
1
1
1
1
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SRAM
0
1
0
1
1
[ 8 x 4 SRAM ]
1
1
0
1
0
0
0
1
1
1
1
1
1
Read operation
1
1
0
1
0
0
1
0
0
0
0
0
1
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Dynamic RAM (DRAM)

In order to build RAMs with higher density (more bits per chip)
 One transistor per bit
 A capacitor stores a bit information
1
1
1
To store “1”
0
1
0
To store “0”
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Dynamic RAM
To read “1”
0
0.5 (precharge to a
voltage halfway
between HIGH
and LOW)
1
1
0.7
0.7
1
1
0.5
A sense amplifier detects 0.7
and recover a 1
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Dynamic RAM
0.7
0.7
destroyed
bit information “1”
A sense amplifier detects 0.7
and recover a 1 (which is stored in a latch)
Note that reading a cell destroys the original voltage stored on the capacitor,
so that the recovered data must be written back into the cell after reading
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Dynamic RAM


Contents in DRAM disappear as time goes by
 Charges on a capacitor don’t remain permanently
DRAM-based memory systems use refresh cycles to update every memory cell
periodically
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Synchronous DRAM (SDRAM)
(bank)
[ 4M (222) x 4-bit DRAM ]
[ CMD[2:0] ]
22-bit address is presented to the chip in two steps at two clock ticks
(1) A[11:0] for 12-bit row address,
(2) A[9:0] for 10-bit column address
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SDRAM Read Cycle





Precharge (PRE) all of the bit lines in a bank, and wait until the precharge has completed
Apply the row address to A[11:0] and issue the ACTV
 The word line for the selected row is activated, and read and stored in a 4096-bit row latch
Wait a few clock ticks (RAS-CAS delay) for the 4096-bit word just read to stabilize
Apply the column address to A[11:0] and issue the READ
 It is applied to the column multiplexer to select 4 bits out of the 4096-bit row latch to be
delivered to DQ[1:4]
CAS latency for addressed 4 bits to propagate to the DQ[1:4]
 During this time, 4096-bit row latch is also written back into the selected row
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SDRAM Write Cycle

A microprocessor drives the write-data onto the DQ bus at the same time that it issues
the WRIT
 SDRAM merges the write-data into the addressed column in the row latch
 Then write the entire, updated 4096-bit value back into selected row
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SDRAM Burst-read and Burst-write cycles


It takes a lot of time and effort to read or write a single location in an SDRAM
 A total of seven clock cycles in our read and write example to transfer a data
Burst-read and burst-write cycles to achieve higher data transfer rates
 Multiple locations in the same row are accessed successively
[ Burst-read cycle with burst length of 4 ]
A typical SDRAM can support burst lengths of 1, 2, 4, or 8 words,
or the entire row latch (called a page, 1024 words in the example)
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SDRAM Burst-read and Burst-write cycles
[ Burst-write cycle with burst length of 4 ]

Auto-refresh cycle (initiated by the REF command)
 SDRAM reads one row of each bank’s internal array into its row latch, and
writes it back
 No address is applied to the A bus
 SDRAM uses the value of an internal 12-bit refresh counter as the row
address, and increments it after the refresh operation
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CPLD (Complex PLD)




A collection of individual PLDs on a single chip
Individual PLDs have at least the functionality of the GAL devices
FPGAs are similar to CPLDs in their applications for complex functions
But internal structures of FPGAs aren’t based on PLAs and PAL devices
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Xilinx CPLD
Architecture of Xilinx XCR3064XL CPLD (Figure based on figures and text owned by Xilinx,
Inc., Courtesy of Xilinx, Inc. © Xilinx, Inc.1999-2003. All rights reserved.)
* From this slide, we take the contents in Fundamentals of Logic Design, by C.M. Roth &
L.L. Kinney, 6th eds. Cengage Learning
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Xilinx CPLD
CPLD Function Block and Macrocell (A Simplified Version of XCR3064XL)
Function Block
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Xilinx CPLD
CoolRunner-II Architecture (Figure based on figures and text owned by Xilinx, Inc., Courtesy of
Xilinx, Inc. © Xilinx, Inc. 1999-2003. All rights reserved.)
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Xilinx CPLD
CoolRunner-II Macrocell (Figure based on figures and text owned by Xilinx, Inc., Courtesy of
Xilinx, Inc. © Xilinx, Inc. 1999-2003. All rights reserved.)
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Xilinx CPLD
CPLD Implementation of a Mealy Machine
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FPGA (Field-Programmable Gate Arrays)

IC chip to contain an array of identical logic cells with programmable
interconnections
CLB (configurable logic block)
is a logic cell
[ Layout of a typical FPGA ]
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FPGA (Field-Programmable Gate Arrays)
LUT (lookup table) : function generator implemented as reprogrammable ROM
[ Simplified Configurable Logic Block (CLB) ]
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FPGA (Field-Programmable Gate Arrays)
Implementation of a Lookup Table (LUT)
a
b
c
d
F
0
0
·
·
1
0
0
·
·
1
0
0
·
·
1
0
1
·
·
1
0
1
·
·
1
F  a' b' c' d 'a' b' cd  a' bc' d  a' bcd 'ab' c' d  ab' cd 'abc' d 'abcd
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FPGA (Field-Programmable Gate Arrays)
Decomposition of switching functions (by Shannon’s expansion theorem)
f ( x1 , x 2 ,..., xi 1 ,0, xi 1 ,..., xn )
 xi ' f ( x1 , x 2 ,..., xi 1 ,0, xi 1 ,..., xn )  xi f ( x1 , x 2 ,..., xi 1 ,0, xi 1 ,..., xn )
 xi ' f 0  xi f i
f (a, b, c, d , e)  a' f (0, b, c, d , e)  af (1, b, c, d , e)  a' f0  af1
G (a, b, c, d , e, f )  a' G (0, b, c, d , e, f )  aG (1, b, c, d , e, f )  a' G0  aG1
G0  b' G (0,0, c, d , e, f )  bG (0,1, c, d , e, f )  b' G00  bG01
G1  b' G (1,0, c, d , e, f )  bG (1,1, c, d , e, f )  b' G10  bG11
G(a, b, c, d , e, f )  a' b' G00  a' bG01  ab' G10  abG11
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FPGA (Field-Programmable Gate Arrays)
f (a, b, c, d , e)  a' f (0, b, c, d , e)  af (1, b, c, d , e)  a' f0  af1
G(a, b, c, d , e, f )  a' b' G00  a' bG01  ab' G10  abG11
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FPGA (Field-Programmable Gate Arrays)
FPGA Implementation of a Mealy Machine
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Xilinx FPGA Spartan-6
www.xilinx.com
The 6-input LUT minimizes the required levels of logic, reducing delay
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