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EET 423 POWER ELECTRONICS -2 Prof R T Kennedy POWER ELECTRONICS 2 1 BUCK CONVERTER CIRCUIT CURRENTS Ii n Ids a IL Ifwd IL b Iout L IC Ids Ei n Ifwd Prof R T Kennedy C POWER ELECTRONICS 2 R Vout 2 BUCK CONVERTER CIRCUIT VOLTAGES Vds a VL,a-b b L Ei n Prof R T Kennedy Vfwd C POWER ELECTRONICS 2 R Vout 3 SUB INTERVAL EQUIVALENT CIRCUITS VL,a-b= Ein-Vout Vds = 0 a L rds,on MOSFET Ei n ON Vfwd = -Ein b C R Vout RECTIFIER OFF Prof R T Kennedy POWER ELECTRONICS 2 4 SUB INTERVAL EQUIVALENT CIRCUITS Vds = Ein VL,a-b= -Vout a b L MOSFET Ei n C OFF R Vout Vfwd= 0 RECTIFIER ON Prof R T Kennedy POWER ELECTRONICS 2 5 Vgs 0 Ein 0 Vds Ein =Vds +(- Vfwd) 0 0 Vfwd 0 VL Vout VL + Vout = -Vfwd 0 0 Prof R T Kennedy POWER ELECTRONICS 2 6 Vgs 0 Ein Ein = Vds + (-Vfwd) 0 -Vfwd Vds 0 0 Vfwd 0 VL Vout 0 0 Prof R T Kennedy POWER ELECTRONICS 2 7 SMPS OPERATION QUANTIZED POWER/ENERGY TRANSFER VOLTAGE REGULATION Prof R T Kennedy POWER ELECTRONICS 2 8 VOLTAGE TRANSFER FUNCTION ANALYSIS • ENERGY BALANCE • POWER BALANCE • VOLT-TIME INTEGRAL Prof R T Kennedy POWER ELECTRONICS 2 9 ‘IDEAL’ BUCK ANALYSIS CCM ENERGY BALANCE APPROACH IL,M INDUCTOR CURRENT I L I out I L 2 IL,av = Iout I L 2 I L, M I out I L 2 I L, m I out I l 2 I L, M I L, m 2 I out I L, M I L, m I L I out I L, M 2Prof I LR, mT2Kennedy 2 I out I L IL,m 0 t POWER ELECTRONICS 2 10 SUB INTERVAL -1: MOSFET ON JL 1 L( I L, M 2 I L, m 2 ) 2 ON Ei n a ENERGY STORED L L I out I L b C OFF R LOAD ENERGY from source INPUT ENERGY J load , s J in Pin ton Prof R T Kennedy Pout ton Vout I out Dsw T Ein I out Dsw T POWER ELECTRONICS 2 11 SUB INTERVAL -2: RECTIFIER ON NO INPUT ENERGY Ei n OFF ON ENERGY Discharge a b L C R J load, L Jload, L Prof R T Kennedy Vout I out D fwd T LOAD ENERGY from inductor L I out I L Vout I out (1 Dsw ) T POWER ELECTRONICS 2 12 J load , s J load, L total load energy (Vout I out Dsw T ) (Vout I out (1 Dsw ) T ) J load, s J load, L Dsw Ein Prof R T Kennedy (Vout I out T ) total load energy input energy Vout I out T Ein I out Dsw T Vout Vout Dsw Ein POWER ELECTRONICS 2 13 ‘IDEAL’ BUCK ANALYSIS CCM POWER BALANCE APPROACH INPUT CURRENT = MOSFET CURRENT IL,M Iout IL,m Iin Iin,av = Ids,av 0 Dsw T Pout Pin Vout I out Ein I in, av Vout I out Ein Dsw I out Vout Prof R T Kennedy Ein Dsw Dfwd T POWER ELECTRONICS 2 t 14 FARADAY’S VOLT-TIME INTEGRAL IM INDUCTOR CURRENT Im current start and finish at same value 0 t V1 INDUCTOR VOLTAGE 0 t1 t V2 t2 VL, av 1 T di L dt T 0 dt VL, av 1 T L di T 0 VL, av L T I T 0 VL, av L I 0 IT 0 T T EQUAL AREAS T 0 v(t ) dt V1 t1 Prof R T Kennedy 0 V2 t2 POWER ELECTRONICS 2 15 ‘IDEAL’ BUCK ANALYSIS CCM VOLT-TIME INTEGRAL APPROACH INDUCTOR VOLTAGE IL 0 Ein -Vout VL area A 0 area B Dsw T Prof R T Kennedy -Vout Dfwd T POWER ELECTRONICS 2 t 16 ‘IDEAL’ BUCK ANALYSIS CCM VOLT-TIME INTEGRAL APPROACH INDUCTOR VOLTAGE area A area B 0 ( Ein Vout ) Dsw T Vout (1 Dsw ) T 0 ( Ein Vout ) Dsw T Vout (1 Dsw ) T Vout Ein Dsw Prof R T Kennedy POWER ELECTRONICS 2 17 BUCK CONVERTER CCM voltage & current waveforms ‘ideal’ • refer to msw notelet Prof R T Kennedy POWER ELECTRONICS 2 18 Vgs I L , rise Ein (1 Dsw ) dt L 0 I out Iout I C , rms 0 Ic Dsw Ein R I L I L 12 d D E (1 Dsw ) R I L, M sw in 1 R 2 L f sw 0 ( Ein Vout ) Dsw I C L f sw I L , fall dt s D E sw in L k a I out Vout IL 0 I L, m Dsw Ein R (1 Dsw ) R 1 2 L f sw I L, rms Dsw ( Ein Vout ) 12 L f sw 2 1 I I ds, rms I out Dsw 1 L 12 I out I ds, av Dsw I out I out Ids 0 I out Ifwd I fwd, av D fwd I out 0 d s k 2 1 I I fwd , rms I out D fwd 1 L 12 I out a Ein Ein 0 Ein Ids Vds Vds 0 0 Vfwd Ei n Ein Ein Vout Vgs fsw VL L IL Iout IC Vfwd C Ifwd Iout R VL 0 Vout Vout Vout Dsw Ein 0 Dfwd = 1-Dsw DfwdT swTT Kennedy ProfDR POWER ELECTRONICS 2 19 INDUCTOR CURRENT WAVEFORMS • CCM or DCM operational mode • component current stress • capacitor ripple current • output voltage ripple • converter efficiency • closed loop regulation performance Prof R T Kennedy POWER ELECTRONICS 2 20 INDUCTOR CURRENT v INDUCTANCE REDUCTION in L IL Iout 0 EinVout VL 0 -Vout t DswT Prof R T Kennedy Dfwd T POWER ELECTRONICS 2 21 INDUCTOR CURRENT v INDUCTANCE increased REDUCTION in L Isw,max IL Ifwd,max Iout 0 IC,ripple Ein-Vout VL Vout,ripple 0 -Vout t DswT dI L, rise dI L, fall dt dt Dfwd T Prof R T Kennedy POWER ELECTRONICS 2 22 INDUCTOR CURRENT I L, M I L, M I out I L 2 I L Vout Vout (1 Dsw ) R 2 L f sw Vout (1 Dsw ) Ein Dsw (1 Dsw ) L f sw L f sw V 1 M I L out R L (1 Dsw ) R 1 2 L f sw I L, M Vout R I L, M Dsw Ein R (1 Dsw ) R 1 2 L f sw I L, m V 1 M I L, M out 1 R 2 L Dsw Ein R (1 Dsw ) R 1 2 L f sw V 1 M I L, m out 1 R 2 L V M out Ein L f sw L RR Tsw R Prof T Kennedy L POWER ELECTRONICS 2 23 INDUCTOR CURRENT Dsw > 0.5 Dsw= 0.5 I L IL Iout I L Dsw < 0.5 I L 0 Dsw = 0.2 Dsw = 0.5 Dsw = 0.8 Prof R T Kennedy t POWER ELECTRONICS 2 24 INDUCTOR CURRENT dI L, rise dt Ein (1 Dsw ) L dI L, fall dt Ein Dsw L DOWNSLOPE UPSLOPE I L IL I L I L 0 t Prof R T Kennedy POWER ELECTRONICS 2 25 INDUCTOR PEAK-PEAK RIPPLE CURRENT I L Ein Dsw (1 Dsw ) L f sw I L f n Dsw (1 Dsw ) I L, max I L 0 Prof R T Kennedy 0.5 Dsw POWER ELECTRONICS 2 1 26 J IL t 0 IL t 0 IL t 0 Prof R T Kennedy POWER ELECTRONICS 2 27 L IL t 0 IL t 0 IL t 0 Prof R T Kennedy POWER ELECTRONICS 2 28 L IL t 0 IL t 0 IL t 0 Prof R T Kennedy POWER ELECTRONICS 2 29 ‘IDEAL’ BUCK CCM DEVICE CURRENT I out IL I sw, M I sw I sw, rms I sw, av I fwd I fwd, M I fwd, rms I fwd, av Dsw Prof R T Kennedy D fwd POWER ELECTRONICS 2 30 ‘IDEAL’ BUCK CCM DEVICE CURRENT I out IL I sw, M I sw I sw, rms I sw, av I fwd I fwd, M I fwd, rms I fwd, av Dsw Prof R T Kennedy D fwd POWER ELECTRONICS 2 31 ‘IDEAL’ BUCK CCM TRANSISTOR CURRENT CCM TRANSISTOR CURRENT IM Vout 1 Dsw R 1 R 2 L f sw Vout 1 M 1 R 2 L Iav Vout Dsw R Vout M R Irms Dsw (1 Dsw ) 2 R 2 Vout Vout Dsw Dsw R 12 Lf R sw IL 2 Vout 1 1 M Vout M 1 M R 12 2 L R R Vout 1 Dsw R L f sw Vout 1 M R L V M out Ein Prof R T Kennedy POWER ELECTRONICS 2 L L f sw R 32 ‘IDEAL’ BUCK CCM RECTIFIER CURRENT CCM RECTIFIER CURRENT Vout D fwd 1 R 2 IM Vout D fwd R Iav Irms rms av R Vout D fwd R L f sw D fwd D fwd 12 1 Vout 1 M 1 R 2 L Vout 1 M R ( D fwd ) 3 R 2 V Vout out D fwd D fwd R R 12 L f sw IL ffi R L f sw 1 1 M 2 V Vout out M M 1 R 12 2 L R Vout 1 M R L M 1 M 2 R 1 L f D fwd sw V M out Ein Prof R T Kennedy POWER ELECTRONICS 2 L L f sw R 33 OUTPUT EFFECTS L Ei n Iin 0 Prof R T Kennedy C s/c Vout= 0 dI in Ein dt L t POWER ELECTRONICS 2 34 OUTPUT EFFECTS L Ei n C o/c VoutEin Prof R T Kennedy POWER ELECTRONICS 2 35 POWER - UP EFFECT L Ei n Prof R T Kennedy C POWER ELECTRONICS 2 Vc = 0 R Vout 36 POWER - DOWN EFFECT L Ei n Prof R T Kennedy C POWER ELECTRONICS 2 R Vout 37 CCM-DCM BOUNDARY I L I out 2 IL I out 0 t Dsw T L f sw 1 Dsw R 2 I L 2 I out Vout R Vout (1 Dsw ) 2 L f sw L Lcritical Prof R T Kennedy I L I out 2 POWER ELECTRONICS 2 (1 Dsw ) R 2 f sw 38 CCM-DCM BOUNDARY 0.5 0.45 0.4 CCM : 0.35 0.3 L f sw 1 Dsw R 2 boundary L f sw 1 Dsw R 2 L f sw 0.25 R 0.2 0.15 DCM : 0.1 0.05 0 L Tsw 0 L f sw 1 Dsw R 2 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Dsw normalised L f sw Prof R R T Kennedy inductor time constant POWER ELECTRONICS 2 39 CCM-DCM BOUNDARY 0.5 0.45 0.4 CCM 0.35 0.3 L f sw 0.25 R boundary 0.2 0.15 0.1 0.05 0 DCM 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Dsw CCM Prof R T Kennedy POWER ELECTRONICS 2 40 CCM-DCM BOUNDARY L Dsw fsw 0.5 0.45 0.4 constant CCM / DCM determined by R CCM 0.35 0.3 L f sw 0.25 INCREASE R R 0.2 ‘light loading’ 0.15 0.1 0.05 0 to ensure a desired CCM DCM 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 does not transfer to DCM 1 Dsw specify a minimum load current (maximum R) avoid open circuit operation Prof R T Kennedy POWER ELECTRONICS 2 41 CCM-DCM BOUNDARY R Dsw fsw 0.5 0.45 0.4 constant CCM / DCM determined by L CCM 0.35 0.3 L f sw 0.25 DECREASE L R 0.2 0.15 0.1 0.05 to ensure a desired CCM 0 DCM 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 does not transfer to DCM 1 Dsw design for CMM at lowest inductance including L v I Prof R T Kennedy POWER ELECTRONICS 2 42 CCM-DCM BOUNDARY R Dsw fsw 0.5 0.45 0.4 constant CCM / DCM determined by fsw CCM 0.35 0.3 L f sw 0.25 DECREASE fsw R 0.2 0.15 0.1 0.05 to ensure a desired CCM 0 DCM 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 does not transfer to DCM 1 Dsw design for CMM at lowest frequency Prof R T Kennedy POWER ELECTRONICS 2 43 CCM-DCM BOUNDARY L R fsw 0.5 0.45 0.4 constant CCM / DCM determined by Dsw CCM 0.35 0.3 L f sw 0.25 DECREASE Dsw R 0.2 0.15 0.1 0.05 to ensure a desired CCM 0 DCM 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 does not transfer to DCM 1 Dsw design for CMM at lowest duty cycle Prof R T Kennedy POWER ELECTRONICS 2 44 LINE & LOAD REGULATION 1 M DCM M DCM M CCM V M out Ein DCM 0.9 L f sw R 0.8 0.7 CCM 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Dsw Prof R T Kennedy POWER ELECTRONICS 2 0.8 0.9 1 Dsw 45 LINE & LOAD REGULATION 1 V M out Ein DCM 0.9 L f sw R 0.8 0.7 CCM 0.6 M 0.5 0.4 0.3 0.2 0.1 0 0 0.1 0.2 0.3 0.4 Dsw, dcm Prof R T Kennedy 0.5 0.6 0.7 0.8 D sw, ccm POWER ELECTRONICS 2 0.9 1 Dsw 46