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GPRS Chipset
Iota
Analog Base Band
PROPRIETARY INFORMATION
System Overview
ClockGene (CKG)
INT2
Micro-control
Serial Port (USP)
Base Band
Serial Port (BSP)
Voltage Regulator (1.8V, 2.7V)
(VREG)
Internal
Bus
Controller
(IBIC)
Timing
Serial Port
(TSP)
APC, AFC,
ADAC
Voice Band
Serial Port (VSP)
Voice
Band
Codec
(VBC)
SIM Card
Regulator and
Level Shifters
3V, 1.8V
(SIMS)
Test Access Port
(TAP)
Base Band
Codec (BBC)
Voltage Reference
Power-On Control (VRPC)
Battery Charger
Interface (BCI)
Monitoring
ADC
(MADC)
PROPRIETARY INFORMATION
2
Block Description: Codecs
• Voice Band Codec (VBC)
– Voice Coder/Decoder
– Uplink: ADC converted samples sent to DSP
speech coder
– Downlink: DAC converted samples received from
DSP
– Programmable Gain, Volume Control and Side
Tone
PROPRIETARY INFORMATION
3
Voice Band
PROPRIETARY INFORMATION
4
Block Description: Codecs
•Base Band Codec (BBC)
–Base band uplink and downlink paths
–Uplink: Modulates burst data from DSP
–Downlink: Converts I/Q data from RF to digital
samples
–Activity timing controlled by TPU of DBB
–2 x 160-bit burst buffers for multislot capability
PROPRIETARY INFORMATION
5
Baseband Uplink
PROPRIETARY INFORMATION
6
Baseband Downlink
PROPRIETARY INFORMATION
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Block Description: Serial Ports
• Voice band serial port (VSP)
• Time Serial Port (TSP)
–
–
–
–
Control real time radio activation windows of Iota:
BUL/BDL power-on, calibration, TX/RX, and ADC startup
Processed by TPU in DBB
6.5 MHz serial clock
• Microcontroller Serial Port (USP)
– 3 terminal synchronous serial port (UDX, UDR, UEN)
– 13 MHz serial clock (from master clock)
– Access to all internal register through IBC
• Base Band Serial Port
– Bi-directional serial port with double buffered TX/RX, 13 MHz
– Read/Write access of all internal registers through IBC
– Format: 16-bit + Frame Sync
PROPRIETARY INFORMATION
8
Voice Band Serial Interface
PROPRIETARY INFORMATION
9
TSP Block Diagram
Baseband Uplink
Baseband Downlink
MADC
Bit 6 : BULON : Power-on window of the baseband uplink
Bit 5 : BULCAL : Offset calibration window of the baseband uplink.
Bit 4 : BULENA : Transmission window of the basband uplink
Bit 3 : BDLON : Power-on window of the baseband downlink
Bit 2 : BDLCAL : Offset calibration window of the baseband downlink.
Bit 1 : BDLENA : Transmission window of the basband downlink
Bit 0 : STARTADC : Window for ADC conversion control
PROPRIETARY INFORMATION
10
USP
Calypso
Iota
PROPRIETARY INFORMATION
11
USP Data Format
• Writing to Internal Registers :
– Bit 0: At zero it indicates a write operation.
– Bit 1 to 5: This field shall contain the address of the register to be
accessed.
– Bit 6 to 15: This field shall contain the data to be written into the
internal register.
• Reading from Internal Registers :
– Bit 0: At one it indicates a read operation.
– Bit 1 to 5: This field shall contain the address of the register to be
accessed.
– Bit 6 to 15: This filed don’ t care in a read requestPROPRIETARY
operation.INFORMATION
12
Baseband Serial Port
Calypso
Iota
PROPRIETARY INFORMATION
13
Block Description: RF Control
• Automatic Power Control (APC)
– Generate envelope signal for RF burst power ramp
control
– Supports single slot and multislot transmission with
smooth power transitions between consecutive
bursts at different power levels
– Includes 10 bit DAC and RAM for digital storage of
power ramp edge shapes of envelope signals
– Timing is controlled by TSP signals
PROPRIETARY INFORMATION
14
APC Control
16steps
5bits
2.167MHz,4x16 steps
interpolation
PROPRIETARY INFORMATION
15
APC Control
When SEL256128=0
 steplev 

  up i   (1  sign step )  dwi  sign step 

256

i 0 
n
PA _ LEVEL n  levelinit 
When SEL256128=1
PA _ LEVEL n  levelinit 
 2  steplev 
  up i   (1  sign step )  dwi  sign step 
256

i 0
n
 
PROPRIETARY INFORMATION
16
Block Description: RF Control
•Automatic Frequency Control (AFC)
–Controls GSM 13 MHz oscillator to synchronize
with base station
–DAC optimized for high resolution conversion
using 13 bit accuracy
PROPRIETARY INFORMATION
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AFC Control
BSP or USP
0 ~ 2.4V
25 KOhm
33 nF
PROPRIETARY INFORMATION
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Block Description: MADC
• Monitoring ADC (MADC)
– Consists of 10-bit ADC with 8 analog multiplexed
inputs
– 4 internal inputs dedicated to monitoring:
•
•
•
•
Main battery voltage
Backup battery voltage
Charger voltage
Charger current
– 4 inputs externally accessible
PROPRIETARY INFORMATION
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Block Description: VREG
• Voltage Regulation (VREG)
– VRDBB - Programmable - (1.8V, 1.5V, 1.3V) for
DBB core
– VRIO - 2.8V supply for digital core and I/Os of Iota
– VRMEM - 2.8V, 1.8V supply for external flash and
DBB memory interface
– VRRAM - 2.8V or 1.8V for SRAM and DBB
memory interface
– VRABB - 2.8V for Iota analog functions
– VRSIM - 2.9V,1.8V for SIM and SIM drivers
PROPRIETARY INFORMATION
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SIMS- Block Diagram
•SIM Card Level Shifters
(SIMS)
–Allows use of both 3V
and 1.8V SIM card types
PROPRIETARY INFORMATION
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Block Description
• Voltage Reference / Power On Control (VRPC)
- providing internal references currents and voltages, internal clock.
- checking of power supplies levels: batteries and LDO output voltages
- detection of Switch ON condition,
- controlling step by step Switch OFF to Switch ON logic sequence and
Switch ON to Switch OFF logic sequence,
- generation of interrupts.
- generation of emergency Switch OFF request.
PROPRIETARY INFORMATION
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VRPC - Pins Description
VREF
REFGND
IBIAS
VRPC
(Voltage Reference Power-on Control)
PRWON
RTC_ALARM
PWON
TESTRESETZ
RESPWRONZ
INT1/INT2
ONNOFF
PROPRIETARY INFORMATION
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Clock Generator
• Source:
– Squared digital system master clock, CK13M, of 13Mhz.
– CLK32K_OUT used by the DBB as reference clock for low power modes
• Target:
– Serial Interfaces and the Bus Controller: CKUSP (13MHz) , CKIBIC
(13MHz) , CKBSP (13MHz) , CKTSP (13 MHz).
– Baseband Codec: CKBDL (13 MHz) and CKBUL (4.3 MHz).
– Auxiliary function: CKMADC (13 MHz), CKAPC (13 MHz) and
CKAFC (4.3 MHz).
– Voice Codec: CKVBC (13 MHz).
– SIM Card Clock: CKSIM ( SCLK3 External Clock ) or OSCAS.
– VREG Clock: CKVREG (13 MHz).
PROPRIETARY INFORMATION
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LED drivers
•LEDA is dedicated for paging indication.
•LEDB is dedicated for LCD backlight and Keypad backlight.
•LEDC is dedicated for charging indication with hardware switch on.
PROPRIETARY INFORMATION
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Block Description
• Test Access Port (TAP)
– Meets JTAG test standard (IEEE 1131.1)
– Allows JTAG instructions debug/test modes
– 4 pins: TDO, TDI, TCK, TMS
• Auxiliary DAC (ADAC)
– General purpose 10-bit DAC
• Battery Charger Interface (BCI)
– Support for 1-cell Li-Ion and 3-cell NiMH
– MADC used for monitoring battery voltage, temperature,
type, charge current, and charger input voltage
– Voltage levels controlled by register accessible through BSP
or USP
PROPRIETARY INFORMATION
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Block Description
• Internal Bus and Interrupt Controller (IBIC)
– Provides read/write access to all internal registers through
BSP or USP
– Arbitrates access to internal Iota bus and direct read data to
the proper serial port
PROPRIETARY INFORMATION
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CK13M
ClockGene (CKG)
UDX
UDR
UEN
INT2
BFSX
BDX
BFSR
BDR
VCK
VFS
VDX
VDR
Micro-control
Serial Port (USP)
Voltage Regulator (1.8V, 2.7V)
(VREG)
Timing
Serial Port
(TSP)
Internal
Bus
Controller
(IBIC)
Voice Band
Serial Port (VSP)
Test Access Port
(TAP)
Voltage Reference
Power-On Control (VRPC)
Battery Charger
Interface (BCI)
ICTL
VCHG
VBAT
SIM Card
Regulator and
Level Shifters
3V, 5V
(SIMS)
OSCAS
PWON
PRWON
INT1
RESPWRONZ
VREF
REFGND
RTC_ALARM
ON/OFF#
IBIAS
TESTRESETZ
SCLK3
SCLK5
SIO3
SIO5
SRST3
SRST5
SVDD
VAUX
VS1
VS2
TMS
TCK
TDI
TDO
Base Band
Serial Port (BSP)
BULIP
BULIM
BULQP
BULQM
BDLIP
BDLIM
BDLQP
BDLQM
TDR
TEN
BULON/TEST1
BULENA/TEST2
BDLON/TEST3
BDLENA/TEST4
COMP
FDBK
GND1
GND2
GND3
SWITCH
UPR
VBACKUP
VCC1
VCC2
VCC3
VR1BOUT
VR1OUT
VR2BOUT
VR2IN
VR2OUT
VR2SEL
VR3OUT
Pinout Overview
Base Band
Codec (BBC)
APC, AFC,
ADAC
APC
AFC
DAC
AUXGND
Voice
Band
Codec
(VBC)
BUZOP
AUXON
AUXOP
EARP
EARN
MICIN
MINIP
AUXI
AGNDAI
MICBIAS
Monitoring
ADC
(MADC)
ADIN1
ADIN2
ADIN3
ADIN4/TSCXP
ADIN5/TSCYP
TSCXM
TXCYM
LCDSYNC
PROPRIETARY INFORMATION
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