Download Sub-threshold current. I 1

Sub-threshold Design of
Ultra Low Power CMOS Circuits
Supervisors:
Students:
Dmitry Vaysman
Alexander Gertsman
Motivation and goal: Research and development of ultra low power digital circuits
operating in the sub-threshold regime of operation. Power consumption reduction of
low/medium performance circuits.
Special Thanks to Dr. Alex Fish and Sagi
Fisher for guidance and assistance.
Why sub-threshold regime?
Why should we care about power consumption?
Micro sensors
Source: Intel
Power Density (W/cm2)
10000
Sun’s
Surface
Rocket
Nozzle
Portable electronics
Medical devices
1000
Nuclear
Reactor
100
Prof. Natan Kopeika
Prof. Orly Yadid-Pecht
Alexander Belenky
Leakage power vs technology scaling
Hot Plate
8086
10 4004
8008 8085
386
286
8080
1
1970
Technology scaling trends
P6
Pentium®
Low/Medium Performance
Applications
486
1980
1990
Year
2000
-“When this leakage power is about 50% of total
power, further supply voltage scaling does not make
sense” (Intel, 2006)
2010
Sub-threshold characteristics
Transistor Leakages
Sub-threshold benefits
Polysilicon Gate
Source
n+
I3
I5
Oxide
I2
Ptotal  Psw  Psc  Pleak
Drain
n+
I4
I1
I6
- Psw is the switching (dynamic) power consumption
- Psc is the short-circuit consumption
- Pleak is the leakage power consumption
P-substrate
I1 – pn junction Reverse
I2 – Sub-threshold current.
I3 – Tunneling into gate oxide
I4 – Hot carriers injection
I5 – Gate Induced Drain Leakage (GIDL)
I6 – Punchthrough
The most significant component of
the IOFF is the Sub-Threshold current.
I SUB  I 0e
VGS VT
Vth
e
VDS
Vth

 1 e
VDS / Vth

Transistor MOS drain current vs. Vgs
VT=threshold voltage
ζ = DIBL coefficient
η = sub-threshold slope factor
Vth = thermal voltage
PSW    (CL  VDD  fCLK )
PSC  I SC  VDD
- CL is the loading capacitance
- fCLK is the clock frequency
- α is the activity factor
- ISC Short circuit current
2
ID versus VDS (VDD=1.8V)
Pleak  Ileak  VDD
- Ileak Leakage current
Reducing VDD to a sub-threshold levels will:
ID versus VDS (VDD=500mV)
•Reduce the switching component by 4 to 81 times!!!
•Reduce the ISC leading to “double reduction”: lower VDD and lower ISC
•Reduce leakage power by 2.5 to 9 times.
- Sub-thershold logic operates with VDD<VT
- Both “on” and “off” currents are sub-threshols leakages
In total it gives us a reduction of leakage power by 5 to 90 times!!!
Instead of fight it we use it!
Innovation
-Operation of the MOS transistor in the
sub-threshold region is something that most
designers try to eliminate.
Does subthreshold operation
is the right way to go?
Ring oscillator
DUT
Gate
Transistor
type
Inverter
typ
hvt
OUT
Ring oscillator setup
-We want to employ the sub-threshold
leakage and make our circuit work at this
area.
lvt
VDD
200mV
VDD
320mV
VDD
1V
4.4MHz 58.7MHz 7.7GHz
NR
NR
7.7GHz
4.4MHz 58.7MHz 7.7GHz
Oscillation frequencies
-Develop methodologies for
sub-threshold logic circuits design.
Static Power consumption of CMOS 90nm Inverter
VTC of CMOS 90nm Inverter
Vdd
[mV]
-Investigate the most appropriate logic style
for operation in the sub-threshold regime.
308.571
Temp
VIL
[mV]
VoH
[mV]
VIH
[mV]
VoL
[mV]
NML
[mV]
NMH
[mV]
125
98.1
291.7
159.3
25
73.1
132.4
25
108.4
298
160
19.2
89.2
138
-40
116.2
301.3
162
15.8
100.4
139.3
Total energy of ring oscillator
Inverter based ring oscillator
Static
Static
parameters
parametersofof
Inverter
Inverter
Four stages 90nm shift register
implemented in tree different topologies.
Sequential Circuit
1
Q
1
MUX
D
1
0
MUX
Delay
0
Q_bar
MUX
Basic FF circuits:
1
MUX
CLK
0
0
0
Average power
consumption of SR
Q
1
D
Q
MUX
D
CLK
CLK
Time domain simulation represents 200mV operation voltage and 500KHz Clk.
Power dissipation of SR is 55nW when operated with 200mV.
Q_bar
1
MUX
Q_bar
It Works!!!
0
Time domain simulation result
Test
Results
Setup time of each topology
when `0` is shifted.
Setup time of each topology
when `1` is shifted.
800
30
700
25
600
ns
500
IMSFF
3IFF
MSFF
400
300
200
20
IMSFF
15
3IFF
10
MSFF
5
100
0
0
Test Circuit
ns
200mV
250mV
300mV
350mV
200mV
250mV
300mV
350mV
Future Steps
- Research different logic families.
-To build generic test circuit.
- Operate this test bench with
different activity factors.
-Evaluate minimum energy point.
-Develop methodology for
minimum energy point operation.
-Test chip fabrication and results
verification.
-Fitting transistor models for
sub-threshold operation.
-Create basic logic cells library.