Download View Presentation

Sub-threshold Design of
Ultra Low Power CMOS Circuits
Annual Projects Conference
July 2nd, 2008
Students:
Dmitry Vaysman
Alexander Gertsman
Supervisors:
Prof. Natan Kopeika
Prof. Orly Yadid-Pecht
Alexander Belenky
Motivation for Power Reduction
in CMOS circuits
Sun’s
10000
Rocket
Micro sensors
Surface
Nozzle
1000
Power Density (W/cm2)
Medical devices
Nuclear
Reactor
100
Portable electronics
8086
10
Hot Plate
4004
8008 8085
Pentium®
286
1
P6
386
486
Low/Medium
Performance
Applications
8080
1970
1980
Source: Intel
Alexander Gertsman
Dmitry Vaysman
1990
2000
2010
Year
2
2/7/2008
Some Trends – Vdd, VT, Energy/Operation
Source: www.intel.com
Sources: Mary Jane Irwin course, ITRS roadmap for semiconductors
Alexander Gertsman
Dmitry Vaysman
3
2/7/2008
Some Trends – Subthreshold Leakage
Sub-threshold leakage power
Sub-threshold leakage power as a
percentage of total power
Source: www.intel.com
Source: www.intel.com
-
Sub-threshold leakage power as a percentage of total power, and it is
already approaching the practical limit of 50%
-
“When this leakage power is about 50% of total power, further supply
voltage scaling does not make sense” (Intel, 2006)
Alexander Gertsman
Dmitry Vaysman
4
2/7/2008
Transistor Leakages
Polysilicon Gate
Source
n+
I3
I5
Oxide
I2
I4
Drain
n+
I1
I6
P-substrate
I1 – pn junction Reverse
I2 – Sub-threshold current.
The most significant component of the IOFF
I3 – Tunneling into gate oxide
is the Sub-Threshold current.
I4 – Hot carriers injection
I5 – Gate Induced Drain Leakage (GIDL)
I6 – Punchthrough
I SUB  I 0e
VGS VT
Vth
e
VDS
Vth

 1  eVDS / Vth

VT=threshold voltage
ζ = DIBL coefficient
η = sub-threshold slope factor
Vth = thermal voltage
Alexander Gertsman
Dmitry Vaysman
Instead of fight it we use it!
5
2/7/2008
Sub-threshold benefits
Ptotal  Psw  Psc  Pleak
- Psw is the switching (dynamic) power consumption
- Psc is the short-circuit consumption
- Pleak is the leakage power consumption
PSW    (CL  VDD  fCLK )
PSC  I SC  VDD
2
- CL is the loading capacitance
- fCLK is the clock frequency
- α is the activity factor
- ISC Short circuit current
Pleak  Ileak  VDD
- Ileak Leakage current
Reducing VDD to a sub-threshold levels will:
•Reduce the switching component by 4 to 81 times!!!
•Reduce the ISC leading to “double reduction”: lower VDD and lower ISC
•Reduce leakage power by 2.5 to 9 times.
In total it gives us a reduction of leakage power by 5 to 90 times!!!
Alexander Gertsman
Dmitry Vaysman
6
2/7/2008
Does subthreshold operation
is the right way to go?
Static Power consumption of
CMOS 90nm Inverter
VTC of CMOS 90nm Inverter
Vdd
[mV]
308.571
Temp
VIL
[mV]
VoH
[mV]
VIH
[mV]
VoL
[mV]
NML
[mV]
NMH
[mV]
125
98.1
291.7
159.3
25
73.1
132.4
25
108.4
298
160
19.2
89.2
138
-40
116.2
301.3
162
15.8
100.4
139.3
Alexander Gertsman
Dmitry Vaysman
7
Good noise margins
2/7/2008
Innovation
-Operation of the MOS transistor in the sub-threshold region is
something that most designers try to eliminate.
-We want to employ the sub-threshold leakage and make our circuit
work at this area.
-Develop methodologies for
sub-threshold logic circuits design.
-Investigate the most appropriate logic style for operation in the subthreshold regime.
Alexander Gertsman
Dmitry Vaysman
8
2/7/2008
Simulation results -Ring oscillator
DUT
Ring oscillator setup
OUT
Gate
Transistor
type
VDD
200mV
VDD
320mV
VDD
1V
Inverter
typ
4.4MHz
58.7MHz
7.7GHz
hvt
NR
NR
7.7GHz
lvt
4.4MHz
58.7MHz
7.7GHz
Oscillation frequencies
Inverter based ring oscillator
Total energy of ring oscillator
Alexander Gertsman
Dmitry Vaysman
9
2/7/2008
Simulation results –Sequential Circuit
Four stages 90nm shift register implemented in three different topologies.
Basic FF circuits:
Q
1
D
MUX
1
0
MUX
Delay
0
Q_bar
CLK
Q
1
D
MUX
1
0
MUX
Q_bar
0
CLK
Q_bar
1
MUX
1
Q
0
Test Circuit
MUX
D
CLK
0
Alexander Gertsman
Dmitry Vaysman
10
2/7/2008
Simulation results –Sequential Circuit
Cont’
Time domain simulation result
Average power consumption of SR
It Works!!!
Time domain simulation represents 200mV operation voltage and 500KHz Clk.
Power dissipation of SR is 55nW when operated with 200mV.
Alexander Gertsman
Dmitry Vaysman
11
2/7/2008
Future Steps
- Research different logic families.
- To build generic test circuit.
- Operate this test bench with different activity factors.
- Evaluate minimum energy point.
- Develop methodology for minimum energy point operation.
- Test chip fabrication and results verification.
- Fitting transistor models for sub-threshold operation.
- Create basic logic cells library.
Alexander Gertsman
Dmitry Vaysman
12
2/7/2008
Any questions?
Alexander Gertsman
Dmitry Vaysman
13
2/7/2008