Download Low Power Consumption (cont.)

Lecture 11 Low Power Modes &
Watchdog Timers
Outline



RX210 Reset Sources
RX210 Low Power Modes
RX210 Watchdog Timers
RX210 Reset source
 There are nine types of resets
 The internal state and pins are initialized by a reset
 When a reset is canceled, the reset exception handling starts
RX210 Reset source (cont.)
 RES# Pin Reset
 Generated by the RES# pin

When the RES# pin is driven low, all the processing in progress is
aborted and the LSI enters a reset state
 To unfailingly reset the LSI, the RES# pin should be held low
for the specified power supply stabilization time at a power-on
 When the RES# pin is driven high from low, the internal reset
is canceled after the post-RES# cancellation wait time
(tRESWT) has elapsed

The CPU starts the reset exception handling
 Power-On Reset
 An internal reset generated by the power-on reset circuit

If the RES# pin is in a high level state when power is supplied, a
power-on reset is generated
 After VCC has exceeded VPOR and the specified period (poweron reset time) has elapsed, the internal reset is canceled

The CPU starts the reset exception handling
RX210 Reset source (cont.)

The power-on reset time is a stabilization period of the external
power supply and the LSI circuit
 After a power-on reset has been generated, the PORF flag in
RSTSR0 is set to 1

The PORF flag is initialized by RES# pin reset
 Voltage Monitoring 0 Reset
 An internal reset generated by the voltage monitoring circuit

If the voltage detection circuit 0 start bit (LVDAS) in option function
select register 1 (OFS1) is 0 (voltage monitoring 0 reset is enabled
after a reset) and VCC falls below Vdet0

The RSTSR0.LVD0RF flag becomes 1 and the voltage detection
circuit generates the reset

Clear the OFS1.LVDAS bit to 0 if the voltage monitoring 0 reset is
to be used
 Release from the voltage monitoring 0 reset state occurs when
VCC rises above Vdet0 and the LVD0 reset time (tLVD0)
elapses

The CPU starts the reset exception handling
RX210 Reset source (cont.)
RX210 Reset source (cont.)
 Voltage Monitoring 1 Reset
 An internal resets generated by the voltage monitoring circuit

When the voltage monitoring 1 interrupt/reset enable bit (LVD1RIE)
is set to 1 (enabling generation of a reset or interrupt by the
voltage detection circuit) and the voltage monitoring 1 circuit mode
select bit (LVD1RI) is set to 1 (selecting generation of a reset in
response to detection of a low voltage) in the voltage monitoring 1
circuit control register 0 (LVD1CR0)

The RSTSR0.LVD1RF flag is set to 1 and the voltage-detection
circuit generates a voltage monitoring 1 reset if VCC falls to or
below Vdet1
 Timing for release from the reset state is selectable with the
voltage monitoring 1 reset negation select bit (LVD1RN) in the
LVD1CR0 register

When the LVD1CR0.LVD1RN bit is 0, the CPU is released from the
internal reset state and starts reset exception handling once the
voltage monitoring 1 reset time (tLVD1) has elapsed after VCC has
risen above Vdet1
RX210 Reset source (cont.)

When the LVD1CR0.LVD1RN bit is 1, the CPU is released from the
internal reset state and starts reset exception handling once the
voltage monitoring 1 reset time (tLVD1) has elapsed
 Voltage Monitoring 2 Reset
 An internal resets generated by the voltage monitoring circuit

When the voltage monitoring 2 interrupt/reset enable bit (LVD2RIE)
is set to 1 (enabling generation of a reset or interrupt by the
voltage detection circuit) and the voltage monitoring 2 circuit mode
select bit (LVD2RI) is set to 1 (selecting generation of a reset in
response to detection of a low voltage) in voltage monitoring 2
circuit control register 0 (LVD2CR0)

The RSTSR0.LVD2RF flag is set to 1 and the voltage detection
circuit generates a voltage monitoring 2 reset if VCC falls to or
below Vdet2
 Timing for release from the reset state is selectable by setting
the voltage monitoring 2/comparator A2 reset negation select
bit (LVD2RN) in the LVD2CR0 register
 Detection levels Vdet1 and Vdet2 can be changed by settings in
the voltage detection level select register (LVDLVLR)
RX210 Reset source (cont.)
 Deep Software Standby Reset
 An internal reset generated when deep software standby mode
is canceled by an interrupt

When a deep software standby mode cancellation source is
generated, a deep software standby reset is generated
 The deep software standby reset is canceled after tDSBY
(return time after deep software standby mode cancellation)
has elapsed

Deep software standby mode is also canceled
 When tDSBYWT (wait time after deep software standby mode
cancellation) has elapsed after deep software standby mode
has been canceled, the internal reset is canceled

The CPU starts the reset exception handling
 Independent Watchdog Timer Reset
 An internal reset generated by the independent watchdog timer

Output of the reset from the independent watchdog timer can be
selected by setting the IWDT reset control register (IWDTRCR) and
option function select register 0 (OFS0)
RX210 Reset source (cont.)

A reset is generated if the independent watchdog timer underflows

Or if data is written outside the refresh-permitted period
 When the internal reset time (tRESW2) has elapsed after the
reset has been generated, the internal reset is canceled

The CPU starts the reset exception handling
 Watchdog Timer Reset
 An internal reset from the watchdog timer

Output of the watchdog timer reset from the independent watchdog
timer can be selected by setting the WDT reset control register
(WDTRCR) and option function select register 0 (OFS0)

A reset is generated if the watchdog timer underflows

Or if data is written outside the refresh-permitted period
 When the internal reset time (tRESW2) has elapsed after the
reset is generated, the internal reset is canceled

The CPU starts the reset exception handling
RX210 Reset source (cont.)
 Software Reset
 An internal reset generated by the software reset circuit
 When A501h is written to SWRR, a reset is generated
 When the internal reset time (tRESW2) has elapsed after the
reset is generated, the internal reset is canceled

The CPU starts the reset exception handling
 By reading the CWSF flag in RSTSR1, the type of reset
processing caused can be identified
 A power-on reset has caused the reset processing (cold start)
 Or a reset signal input during operation has caused the reset
processing (warm start)

The CWSF flag in RSTSR1 is set to 0 when a power-on reset occurs
(cold start)

Otherwise the flag is not set to 0
 Reading RSTSR0 and RSTSR2 determines which reset was
used to execute the reset exception handling
RX210 Reset source (cont.)
 Reset Status Register 0 (RSTSR0)
RX210 Reset source (cont.)
 Reset Status Register 1 (RSTSR1)
 Software Reset Register (SWRR)
RX210 Reset source (cont.)
 Reset Status Register 2 (RSTSR2)
Low Power Consumption
 RX210 has some functions for reducing power consumption





Switching of clock signals to reduce power consumption
BCLK output control
Stopping modules
Functions for low power consumption in normal operation
Transitions to low power consumption states
 Reducing Power Consumption by Switching Clock Signals
 When the SCKCR.FCK[3:0], ICK[3:0], BCK[3:0], PCKB[3:0],
and PCKD[3:0] bits are set, the clock frequency changes

The CPU, DMAC, DTC, ROM, and RAM operate on the operating
clock specified by the ICK[3:0] bits

Peripheral modules operate on the operating clock specified by the
PCKB[3:0], and PCKD[3:0] bits

The flash memory interface operates on the operating clock
specified by the FCK[3:0] bits

The external bus operates on the operating clock specified by the
BCK[3:0] bits
Low Power Consumption (cont.)
 Module Stop Function
 Can be set for each on-chip peripheral module
 The specified module stops operating and enters the module
stop state, but the CPU continues to operate independently

When the MSTPmi bit (m = A to C, i = 0 to 31) in MSTPCRA to
MSTPCRC is set to 1
 Clearing the MSTPmi bit to 0 cancels the module stop state

Allowing the module to restart operating at the end of the bus cycle
 The internal states of modules are retained in the stop state
 After a reset is canceled, all modules other than the DMAC,
DTC, and RAM are placed in the module stop state
 Read/write access cannot be made to the registers of the
module that are in the module stop state
 Power consumption can be reduced
 By selecting an appropriate operating power consumption
control mode according to the operating frequency and
operating voltage
Low Power Consumption (cont.)
 Sleep mode
 The CPU enters sleep mode

When the WAIT instruction is executed as the SBYCR.SSBY bit is 0
 The CPU stops operating

The contents of its internal registers are retained
 Other peripheral functions do not stop
 The WDT stops counting when sleep mode is entered
 Counting by the IWDT stops

If a transition to sleep mode is made while the IWDT is being used
in auto-start mode and the OFS0.IWDTSLCSTP bit is 1

If a transition to sleep mode is made while the IWDT is being used
in register start mode and the SLCSTP bit in IWDTCSTPR is 1
 Counting by the IWDT continues

If a transition to sleep mode is made while the IWDT is being used
in auto-start mode and the OFS0.IWDTSLCSTP bit is 0

If a transition to sleep mode is made while the IWDT is being used
in register start mode and the SLCSTP bit in IWDTCSTPR is 0
Low Power Consumption (cont.)
 To use sleep mode, make the following settings and then
execute a WAIT instruction

Clear the PSW.I bit of the CPU to 0

Set the interrupt destination to be used for recovery from sleep
mode to the CPU

Set the priority of the above interrupt to a level higher than the
setting of the PSW.IPL[3:0] bits of the CPU

Set the IERm.IENj bit for the interrupt to 1

For the last I/O register to which writing proceeded, read the
register to confirm that the value written has been reflected

Execute the WAIT instruction, which automatically sets the I bit in
the PSW of the CPU to 1
 Sleep mode is canceled by any interrupt

And the reset signal from the RES# pin, a power-on reset, a
voltage monitoring reset, or a reset caused by an IWDT underflow
 Canceling by an interrupt

When an interrupt occurs, sleep mode is canceled and the interrupt
exception handling starts
Low Power Consumption (cont.)

If a maskable interrupt has been masked by the CPU, sleep mode is
not canceled
 Canceling by the RES# pin

When the RES# pin is driven low, the LSI enters the reset state

When the RES# pin is driven high after the reset input for a
predefined time period, the CPU starts the reset exception handling
 Canceling by a power-on reset

Sleep mode is canceled by a power-on reset
 Canceling by a voltage monitoring reset

Sleep mode is canceled by a voltage monitoring reset from the
voltage detection circuit
 Canceling by the independent watchdog timer reset

Sleep mode is canceled by an internal reset generated by an IWDT
underflow

When OFS0.IWDTSTRT = 0 and OFS0.IWDTSLCSTP = 1, or
OFS0.IWDTSTRT = 1 and IWDTCSTPR.SLCSTP = 1, the IWDT is
stopped in sleep mode and sleep mode cannot be canceled by the
independent watchdog timer reset
Low Power Consumption (cont.)
 To switch the clock source used on return from sleep mode

The clock used after return needs to be set by the sleep mode
return clock source switching register (RSTCKCR)

The wait control register needs to be set for each clock source

When the return interrupt is generated, the clock source is
automatically switched, and operation returns from sleep mode

The registers related to clock source switching are automatically
rewritten

If a transition is made to sleep mode with the OSTDCR.OSTDE bit
being 1 (oscillation stop detection function enabled), the sleep
mode return clock source switching function is disabled
 All-module clock stop mode
 The CPU enters all-module clock stop mode

Executing a WAIT instruction while the SBYCR.SSBY bit is 0 after
setting the MSTPCRA.ACSE bit to 1 and placing modules controlled
by MSTPCRA, MSTPCRB, and MSTPCRC registers in the module stop
state (MSTPCRA = FFFF FF[C-F]Fh, MSTPCRB = FFFF FFFFh,
MSTPCRC[31:16] = FFFFh)
Low Power Consumption (cont.)
 Stops the bus controller, I/O ports, and all modules except for
the 8-bit timers, POE, IWDT, RTC, power-on reset circuit,
voltage detection circuit at the end of the current bus cycle
 The WDT stops counting when the mode is entered
 Counting by the IWDT stops

If a transition to the mode is made while the IWDT is being used in
auto-start mode and the OFS0.IWDTSLCSTP bit is 1

If a transition to the mode is made while the IWDT is being used in
register start mode and the SLCSTP bit in IWDTCSTPR is 1
 Counting by the IWDT continues

If a transition to the mode is made while the IWDT is being used in
auto-start mode and the OFS0.IWDTSLCSTP bit is 0 (counting by
the IWDT continues through transitions to low power modes)

If a transition to the mode is made while the IWDT is being used in
register start mode and the SLCSTP bit in IWDTCSTPR is 0
 To use all-module clock stop mode, make the following settings
and then execute a WAIT instruction

Clear the PSW.I bit of the CPU to 0
Low Power Consumption (cont.)

Set the interrupt destination to be used for recovery from allmodule clock stop mode to the CPU

Set the priority of the above interrupt to a level higher than the
setting of the PSW.IPL[3:0] bits of the CPU

Set the IERm.IENj bit for the interrupt to be used for recovery from
all-module clock stop mode to 1

For the last I/O register to which writing proceeded, read the
register to confirm that the value written has been reflected

Execute the WAIT instruction, which automatically sets the I bit in
the PSW of the CPU to 1
 Release from all-module clock stop mode is initiated by an
external pin interrupt (the NMI or IRQ0 to IRQ7)

And a peripheral interrupt (8-bit timer, RTC alarm, RTC periodic,
IWDT, voltage monitoring 1, voltage monitoring 2, or oscillatorstopped detection interrupt)

And a RES# pin reset, a power-on reset, a voltage monitoring
reset, or an independent watchdog timer reset
 The transition to the normal program execution state proceeds
via exception processing for the given interrupt or reset
Low Power Consumption (cont.)
 The interrupt will not cancel all-module clock stop mode

If a maskable interrupt has been masked by the CPU or a maskable
interrupt has been set up as a trigger to activate the DTC or DMAC
 Software standby mode
 The CPU enters software standby mode

When a WAIT instruction is executed with the SBYCR.SSBY bit set
to 1 and the DPSBYCR.DPSBY bit cleared to 0
 The CPU, on-chip peripheral functions, and all the oscillator
functions stop

The contents of the CPU internal registers, RAM data, on-chip
peripheral functions, and the states of the I/O ports are retained

Whether the address bus and bus control signals are placed in the
high-impedance or the output state is retained can be specified by
the SBYCR.OPE bit
 This mode allows significant reduction in power consumption

The oscillator stops in this mode

Further reduction of power consumption is possible by using the
FHSSBYCR register
Low Power Consumption (cont.)
 Clear the DMAST.DMST bit of the DMAC and the DTCST.DTCST
bit of the DTC to 0 before executing the WAIT instruction
 The WDT stops counting because the oscillator stops
 Counting by the IWDT stops

If a transition to the mode is made while the IWDT is being used in
auto-start mode and the OFS0.IWDTSLCSTP bit is 1

If a transition to the mode is made while the IWDT is being used in
register start mode and the SLCSTP bit in IWDTCSTPR is 1
 Counting by the IWDT continues

If a transition to the mode is made while the IWDT is being used in
auto-start mode and the OFS0.IWDTSLCSTP bit is 0 (counting by
the IWDT continues through transitions to low power modes)

If a transition to the mode is made while the IWDT is being used in
register start mode and the SLCSTP bit in IWDTCSTPR is 0
 When the oscillation stop detection function is enabled,
software standby mode cannot be entered

Execute a WAIT instruction after disabling the oscillation stop
detection function (OSTDCR.OSTDE = 0)
Low Power Consumption (cont.)
 To use software standby mode, make the following settings and
then execute a WAIT instruction

Clear the PSW.I bit of the CPU to 0

Set the interrupt destination to be used for recovery from software
standby mode to the CPU

Set the priority of the above interrupt to a level higher than the
setting of the PSW.IPL[3:0] bits of the CPU

Set the IERm.IENj bit for the interrupt to be used for recovery from
all-module clock stop mode to 1

For the last I/O register to which writing proceeded, read the
register to confirm that the value written has been reflected

Execute the WAIT instruction, which automatically sets the I bit in
the PSW of the CPU to 1
 Release from software standby mode is initiated by an external
pin interrupt (the NMI or IRQ0 to IRQ7)

And peripheral interrupts (the RTC alarm, RTC periodic, IWDT,
voltage monitoring 1, and voltage monitoring 2 interrupts), an
RES# pin reset, a power-on reset, a voltage monitoring reset, or an
independent watchdog timer reset
Low Power Consumption (cont.)
 Release due to an interrupt

When an interrupt request from among the NMI, IRQ0 to IRQ7, RTC
alarm, RTC periodic, IWDT, voltage monitoring 1, and voltage
monitoring 2 interrupts is generated, each of the oscillators which
was operating before the transition to software standby mode
resumes oscillation

After the time set by the MOSCWTCR.MSTS[4:0],
SOSCWTCR.SSTS[4:0], HOCOWTCR2.HSTS2[3:0], or
PLLWTCR.PSTS[4:0] bits has elapsed, the chip is released from
software standby mode and starts interrupt exception processing
 Release due to a reset on the RES# pin

Clock oscillation starts as the low level is applied to the RES# pin

Clock supply for the LSI starts at the same time

Keep the level on the RES# pin low over the time required for
oscillation of the clocks to become stable

Reset exception processing starts when the high level is applied to
the RES# pin
 Release due to a power-on reset
Low Power Consumption (cont.)

Release from software standby mode proceeds after a fall in the
power-supply voltage leads to the generation of a power-on reset
 Release due to a voltage monitoring reset

Release from the mode proceeds after a fall in the power-supply
voltage leads to the generation of a voltage monitoring reset
 Release due to an independent watchdog timer reset
 An internal reset due to an underflow of the IWDT leads to
release from software standby mode

If a condition for the independent watchdog timer to stop counting
applied at the time of a transition to software standby, using a
reset from the independent watchdog timer to release the chip from
software standby is impossible because the independent watchdog
timer is stopped
 An example of a transition to software standby mode

Made at the falling edge and canceled at the rising edge of IRQn pin

An IRQn interrupt is accepted with the IRQCRi.IRQMD[1:0] bits of
the ICU set to 01b (falling edge)

Then the IRQCRi.IRQMD[1:0] bits are set to 10b (rising edge)
Low Power Consumption (cont.)
Low Power Consumption (cont.)
 Deep software standby mode
 A transition to software standby mode is made

When the WAIT instruction is executed with SBYCR.SSBY set to 1
 The CPU, internal peripheral modules and all functions of the
oscillators are stopped

Except for the RTC alarm, RTC periodic, SCL-DS, and SDA-DS
 The internal supply of power for these modules is stopped

Power consumption is markedly reduced
 The contents of all the registers of the CPU and on-chip
peripheral modules and the RAM data become undefined
 When the DPSBYCR .DEEPCUT1 bit is set to 1

The voltage detection circuit is stopped

The power consumption reduction function by the power-on reset
circuit is enabled

Further reducing power consumption

This varies the voltage detection characteristic of the power-on
reset circuit
Low Power Consumption (cont.)
 When the WDT is in use, counting also stops

The oscillators and power supply to the WDT are stopped by the
transition to deep software standby mode
 Power supply to the IWDT-dedicated LOCO is stopped

The IWDT is stopped and counting by the IWDT stops
 A transition to deep software standby mode cannot be made,
but to software standby

When the voltage monitoring 1 reset function (LVD1CR0.LVD1RI =
1) or voltage monitoring 2 reset function (LVD2CR0.LVD2RI = 1) is
selected for the voltage detection circuit
 Release from deep software standby mode is initiated by any of
the external pin interrupt source pins (the NMI, IRQ0- DS to
IRQ7-DS, SCL-DS, or SDA-DS)

And peripheral interrupts (the RTC alarm, RTC periodic, voltage
monitoring 1, and voltage monitoring 2 interrupts)

And an RES# pin reset, a power-on reset, or a voltage monitoring 0
reset
Low Power Consumption (cont.)
 Canceling by external interrupt pin or internal interrupt signal

Cancellation of the mode is controlled by DPSIERn (n = 0, 2) and
DPSIFRn (n = 0, 2)

When an interrupt is generated, the corresponding flag in DPSIFRn
is set to 1

if the canceling source is enabled in DPSIERn, the mode is canceled

Rising edge or falling edge can be selected by DPSIEGRn (n = 0, 2)

The interrupts for which an edge can be selected are the NMI,
IRQ0-DS to IRQ7-DS, SCL-DS, SDA-DS, voltage monitoring 1, and
voltage monitoring 2 interrupts

When a canceling source is generated, the internal power supply
and LOCO clock oscillation begin

The internal reset (deep software standby reset) is generated for
the entire LSI

A stable LOCO clock is then supplied to the entire LSI

Deep software standby reset is canceled

Deep software standby mode is canceled and the reset exception
handling starts
Low Power Consumption (cont.)

When the mode is canceled by an external interrupt pin or internal
interrupt signal, the RSTSR0.DPSRSTF (Deep Software Standby
Reset Detect Flag) is set to 1
 Release due to a reset on the RES# pin

Canceled when the low level is applied to the RES# pin

Reset exception processing starts when the high level is applied to
the RES# pin
 Release due to a power-on reset

Release from the mode proceeds after a fall in the power-supply
voltage leads to the generation of a power-on reset
 Release due to a voltage monitoring 0 reset

Release from the mode proceeds after a fall in the power-supply
voltage leads to the generation of a voltage monitoring 0 reset
 In deep software standby mode, the I/O ports retain the same
states from software standby mode
 The inside of the LSI is initialized by an internal reset generated
when deep software standby mode is canceled
Low Power Consumption (cont.)

Upon cancellation of deep software standby mode, the reset
exception handling starts immediately
 Whether to initialize the I/O ports or to keep retaining the I/O
port states at the time of software standby mode can be
selected by the DPSBYCR.IOKEEP bit.

When the DPSBYCR.IOKEEP bit = 0, I/O ports are initialized by an
internal reset generated when the mode is canceled

When the DPSBYCR.IOKEEP bit = 1, the inside of the LSI is
initialized by an internal reset generated

The I/O port states remain unchanged from software standby mode
even if settings of I/O ports or peripheral modules are made

The retained I/O port states are released by clearing the
DPSBYCR.IOKEEP bit to 0

The LSI operates according to the internal state.

The DPSBYCR.IOKEEP bit is not initialized by an internal reset
generated when deep software standby mode is canceled
 An example of a transition to deep software standby mode

Made at the falling edge of the IRQn-DS pin, and canceled at the
rising edge of the IRQn-DS pin
Low Power Consumption (cont.)
 Module Stop Control Register A (MSTPCRA)
Low Power Consumption (cont.)
 Standby Control Register (SBYCR)
Low Power Consumption (cont.)
 Sleep Mode Return Clock Source Switching Register
(RSTCKCR)
Low Power Consumption (cont.)
 Main Clock Oscillator Wait Control Register (MOSCWTCR)
 Used to control the oscillation stabilization wait time of the
main clock oscillator
Low Power Consumption (cont.)
 Deep Standby Control Register (DPSBYCR)
Low Power Consumption (cont.)
 Deep Standby Interrupt Enable Register 0 (DPSIER0)
Low Power Consumption (cont.)
 Deep Standby Interrupt Flag Register 0 (DPSIFR0)
Low Power Consumption (cont.)
 Deep Standby Interrupt Edge Register 0 (DPSIEGR0)
Watchdog Timer
 The watchdog timer detects programs being out of control
 Has a 14-bit down-counter

Can be set up to reset the chip by a reset output

When counting down from the initial value causes an underflow of
the counter

Alternatively, generation of an interrupt request is selectable when
the counter underflows

The initial value for counting can be restored to the down-counter
by refreshing its value

The interval over which refreshing is possible can also be selected

Refreshing the counter during this interval will restore its initial
value for counting

Attempting to refresh the counter beyond this interval leads to the
output of a reset or interrupt request

The refresh interval can be adjusted and used to detect the
program entering runaway conditions

The WDT stops counting after an underflow or an attempt at
refreshing the counter beyond the allowed interval
Watchdog Timer (cont.)

Counting is restarted by refreshing the counter when the WDT is in
register start mode

When the WDT is in auto-start mode, counting is restarted
automatically after output of the reset or interrupt request
 The WDT has two start modes:
 Auto-start mode

Counting automatically starts after release from the reset state
 Register start mode

Counting is started by refreshing the WDT (writing to the register)
 In auto-start mode, necessary settings should be made in
option function select register 0 (OFS0) before release from the
reset state
 In register start mode, necessary settings should be made in
the respective registers before the counter is started by
refreshing after release from the reset state

Clock division ratio, refresh window start and end positions, timeout period, reset or non-maskable interrupt request output at an
underflow
Watchdog Timer (cont.)
 Block diagram of WDT
Watchdog Timer (cont.)
 Set the WDT start mode select bit (OFS0.WDTSTRT bit) to
select auto-start mode or register start mode
 When auto-start mode is selected (OFS0.WDTSTRT = 0)

The WDT control register (WDTCR), and WDT reset control register
(WDTRCR) settings are disabled

The settings of option function select register 0 (OFS0) are enabled
 When register start mode is selected (OFS0.WDTSTRT = 1)

The settings of option function select register 0 (OFS0) are disabled

The WDTCR and WDTRCR settings are enabled
 Register start mode
 After canceling from the reset

Set the clock division ratio, window start and end positions, and
time-out period in the WDTCR register

Set the reset or interrupt request output in the WDTRCR register

Refresh the down-counter to start counting down from the value
selected by setting the time-out period selection
(WDTCR.TOPS[1:0]) bits
Watchdog Timer (cont.)
 The WDTCR.TOPS[1:0] bits select the time-out period

Period until the down-counter underflows from among 1,024,
4,096, 8,192, and 16,384 cycles

Taking the divided clock specified by the WDTCR.CKS[3:0] bits as
one cycle

After the down-counter is refreshed, the combination of the
CKS[3:0] and TOPS[1:0] bits determines the time (number of PCLK
cycles) until the counter underflows
 The WDT does not output the reset signal

As long as the program continues normal operation and the counter
is refreshed in the refresh-permitted period

The interval between the window start position and window end
position is the refresh-permitted period and the other periods are
refresh-prohibited periods

The value in the counter is re-set each time the counter is refreshed
and counting down continues
 The WDT outputs a reset signal or a non-maskable interrupt
request (WUNI)
Watchdog Timer (cont.)

If the down-counter underflows due to a program runaway

If a refresh error occurs because the counter was refreshed outside
the refresh-permitted period
 Select reset output or interrupt request output

By setting the reset interrupt request selection (WDTRCR.RSTIRQS
 An example of operation under the register start mode

The WDT start mode select bit (OFS0.WDTSTRT) is 1 (register start
mode)

The reset interrupt request selection bit (WDTRCR.RSTIRQS) is 1
(reset output is enabled)

The window start position selection bits (WDTCR.RPSS[1:0]) are
10b (75%)

The window end position selection bits (WDTCR.RPES[1:0]) are 10b
(25%)
Watchdog Timer (cont.)
 Auto-start mode
 Within the reset state

The clock division ratio, window start and end positions, time-out
period, reset output or interrupt request output should be specified
in option function select register 0 (OFS0)
 When the reset state is canceled, the down-counter
automatically starts counting down from the value selected by

The WDT time-out period selection (OFS0.WDTTOPS[1:0]) bits
 The WDT does not output the reset signal

As long as the program continues normal operation and the counter
is refreshed in the refresh-permitted period

The value in the counter is re-set when the counter is refreshed and
counting down continues
 The WDT outputs the reset signal or non-maskable interrupt
request (WUNI)

If the down-counter underflows due to the program having entered
crashed execution
Watchdog Timer (cont.)

If a refresh error occurs due to refreshing outside the refreshpermitted period
 The reset output or interrupt request output can be selected

Through the WDT reset interrupt request selection
(OFS0.WDTRSTIRQS) bit
 An example of operation under the auto-start mode

The WDT start mode select bit (OFS0.WDTSTRT) is 0 (auto-start
mode)

The reset interrupt request select bit (OFS0.WDTRSTIRQS) is 0
(non-maskable interrupt request output is enabled)

The window start position select bits (OFS0.WDTRPSS[1:0]) are
10b (75%)

The window end position select bits (OFS0.WDTRPES[1:0]) are 10b
(25%)
Watchdog Timer (cont.)
 Writing to the WDT control register (WDTCR) or WDT reset
control register (WDTRCR) is only possible once
 Between the release from the reset state and the first refresh
operation
 After a refresh operation (counting starts) or by writing to
WDTCR or WDTRCR, the protection signal in WDT becomes 1

To protect WDTCR and WDTRCR against subsequent attempts at
writing
 This protection is released by the reset source of the WDT

With other reset sources, the protection is not released
 The refresh error (WDTSR.REFEF) and underflow
(WDTSR.UNDFF) flags retain the source of the reset signal
output or the source of the interrupt request from the WDT

After release from the reset state or interrupt request generation,
read the WDTSR.REFEF and WDTSR.UNDFF flags to check for the
reset or interrupt source

For each flag, writing 0 clears the bit and writing 1 has no effect
Watchdog Timer (cont.)

Leaving the status flags unchanged does not affect operation

If the flags are not cleared, at the time of the next reset or
interrupt request from the WDT, the earlier reset or interrupt
source is cleared

The new reset or interrupt source is written
 A reset signal is output for one-count cycle when an
underflow in the down-counter or a refresh error occurs
 When the reset interrupt selection (WDTRCR.RSTIRQS) bit is
set to 1 in register start mode
 Or when the WDT reset interrupt request selection
(OFS0.WDTRSTIRQS) bit in option function select register 0
(OFS0) is set to 1 in auto-start mode
 In register start mode, the down-counter is initialized (all bits
cleared to 0) and kept in that state after the reset signal

After the reset is canceled and the program is restarted, the
counter is set up again and counting down is started by refreshing
 In auto-start mode, counting down automatically starts after
the reset output
Watchdog Timer (cont.)

Leaving the status flags unchanged does not affect operation

If the flags are not cleared, at the time of the next reset or
interrupt request from the WDT, the earlier reset or interrupt
source is cleared

The new reset or interrupt source is written
 A reset signal is output for one-count cycle when an
underflow in the down-counter or a refresh error occurs
 When the reset interrupt selection (WDTRCR.RSTIRQS) bit is
set to 1 in register start mode
 Or when the WDT reset interrupt request selection
(OFS0.WDTRSTIRQS) bit in option function select register 0
(OFS0) is set to 1 in auto-start mode
 In register start mode, the down-counter is initialized (all bits
cleared to 0) and kept in that state after the reset signal

After the reset is canceled and the program is restarted, the
counter is set up again and counting down is started by refreshing
 In auto-start mode, counting down automatically starts after
the reset output
Watchdog Timer (cont.)
 The WDT stores the counter value in the down-counter value
(WDTSR.CNTVAL[13:0]) bits of the WDT status register
 The counter value can be checked through the
WDTSR.CNTVAL[13:0] bits
 Correspondence between option function select register 0
(OFS0) and the WDT registers (WDT control register
(WDTCR) and WDT reset control register (WDTRCR))
Watchdog Timer (cont.)
 WDT Status Register (WDTSR)
 WDT Control Register (WDTCR)
Watchdog Timer (cont.)
 WDT Refresh Register (WDTRR)
 WDT Reset Control Register (WDTRCR)