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EE 466/586 VLSI Design Partha Pande School of EECS Washington State University [email protected] Lecture 5 MOS Inverter Circuits Saturated Enhancement Load A single NMOS transistor with the gate connected to the drain can be used as a load device. Saturated Enhancement Load (Cont’d) The load transistor can operate only in saturation or cutoff (VGS = VDS ) The other NMOS device pulls down the output node The relative sizes of the two transistors determine the output voltage Saturated Enhancement Load (cont’d) The output high level VOH is not equal to VDD The pull-up transistor ceases to conduct after its gate-source voltage decreases to the threshold voltage. The output node never rises above VDD-VTL VTL is no longer VT0 Output voltage appears as a body bias Follow board notes Saturated Enhancement Load (Cont’d) How to find VOL? For the inverting transistor, with VGS=VOH the output voltage should be lower than VT0 Pull down transistor is in the linear region VDS<VGS - VTI IDI(lin)= IDL (Sat) Follow board notes Linear Enhancement load The output high level of the saturated enhancement load configuration is not sufficient Linear Enhancement Load (Cont’d) The load device can pull the output all the way to VDD For the pull up device VDS<VGS-VTL The pull-up device, operates in the linear region