Download Finding the root cause of ESD problems

Finding the root cause of ESD
problems
Dr. David Pommerenke
With contributions from all members of the EMC laboratory
University Missouri Rolla – EMC laboratory
[email protected]
#1
Content
 ESD is combines many tests in one test
 ESD failure analysis
 Susceptibility scanning
 Voltage in traces during ESD testing
#2
Definitions
Hard-error: Any error that leads to a physical failure of the IC.
(Excessive leakage current, loss of functionality)
Soft-error: Any error that can be cured by resetting the system
(logical errors: bit error, false reset)
#3
Physical parameters that may lead to an ESD failure
Energie
Direct discharge into a PIN of a connector
Dielletric breakdown
Spark through a plastik front panel
Current
Voltage drop accross a protection circuit
ESD combines many different tests
into one test standard.
From
electrostatics,
via breakdown physics
to a 1 GHz 20kV/m pulse.
Current derivative
Insufficient response of a protection circuit
Secondary breakdown
Current raises chassies potential until secondary breakdown occurs
inside the chassie
Near field
Discharge to the metallic chasies. Fields couple through a nearby opening.
Fields couple into a cable.
Farfield
Fields from a distant ESD induce currents on the chassis.
#4
It has failed! - What to do now?
It failed, what now?
 Is it a soft or a hard failure?
 At which test point did it fail?
 At which voltage did it fail?
 Was it in contact or air discharge mode?
How repeatable is the failure?
Question: What do you do to debug ESD problems?
#5
How to fix it?
Exact circuit understanding
Shielding
Pro: The most cost efficient solution.
Learn how to design in the future.
Pro: No system understanding needed.
If it works, the fast!
Contra:
Need to understand software
Need to understand circuits
Requires specialized equipment
May require special firmware
Contra:
Often more expensive solution
Adds material
But how to do it?
#6
Local probing around the EUT
A first start of finding the root cause may be:
@ 8kV,
restart
display
EUT
20mm
50mm
200mm
@
10kV
restart
@ 15kV
restart
Locating sensitivity on the outside might help to correlate to the affected IC or trace, but:
• Outside location may only be a result of breach in shielding
• Outside location is too broad to correlate to details inside:
#7
Let’s go inside!
Different coupling mechanisms require different probes
Injection can be done:
#8
•
To the enclosure
-
dm
•
To cables
-
cm
•
To connectors
-
mm
•
To boards
-
cm2
•
To board traces
-
5 mil (using microscope)
•
To lead-frames traces -
1 mil (using microscope)
Probes used for injection
#9
Different coupling mechanisms require different probes
Direct injection between to “grounds”.
In selecting the right injection method
one has to try to emulate the same
excitation mechanism as occurs during
the standardized test or at the customer
site.
Anticipating the right method is often
guided by carefully observing the
differences of failure signature at
different test points.
# 10
Disturbance sources: TLP and narrow pulse
The Output of the High Voltage Transmission Line Pulse Generator
1000
The measurement of the high voltage
transmission line pulse generator
output pulse, about 500 ps rise (2080%)
800
400
0.16
200
0.14
0
0.12
Less than 200 ps
pulse
0.1
-200
0
20
40
60
80
100
Time [ns]
Voltage on trace [V]
Voltage [V]
600
0.08
0.06
0.04
0.02
0
-0.02
Narrow pulse generator
# 11
-0.04
0
0.2
0.4
0.6
0.8
1
1.2
Time [ns]
1.4
1.6
1.8
2
Automated Susceptibility Scanning system of UMR
Brief explanation
The system moves injection
probes to predefined locations,
injects pulses and observes the
system response.
In most cases, pulses are “ESDlike”, e.g., having rise times 0.1 2 ns.
Injection is done using different
injection probes for testing direct
coupling, E and H-field coupling.
If needed, the voltages at the
input of the IC are measured
during the ESD event.
# 12
Automated Susceptibility Scanning system of UMR
TLP triggering signal
TLP
Motion
Control
Probe position data, motion control
Power
S/W
Scope
Pulse injection
signal
probing
Control
Computer
System monitor
(parallel port)
Critical is the error feedback: A test code needs to be operating on the EUT. The test
code signals to the control PC if a malfunction has occurred. If so, the level of injected
noise (by source setting, not by induced voltage) is recorded and the EUT is reset.
# 13
Test flow diagram
# 14
Example: Identifying sensitive nets
•
•
Besides direct coupling to an IC, four sensitive nets are identified
Only 4 nets are sensitive, but there sensitivity is 10X as strong as any other net
Net 2
310
Net 4
300
290
450
280
400
270
Net 2
350
Net 1
Net 3
260
Net 4
300
250
Net 3
250
Net 1
240
50
180
# 15
190
200
210
220
230
240
250
100
150
200
250
Example: Identifying sensitive nets
The same area is scanned
using different polarization
of the H-field probe.
Probe Polarization : ←
310
The difference between the
“left” and the “right”
polarization is the polarity of
the induced noise voltage.
300
290
280
The sensitive traces are
identified by circuit diagram.
270
Scanned in next stage
260
250
240
180
# 16
190
200
210
220
230
240
250
If needed a finer scan is
performed.
Example: Identifying sensitive nets
256
254
252
250
248
246
244
242
240
1.5mm
238
178 180 182 184 186 188 190 192 194
1mm
• A critical part of the board in the previous scanned area has been fine-scanned
using very small magnetic field probe to identify the correct trace
• The scan resolution was set to 0.5mm x 0.5mm
• The small probe couples less energy into the trace, but in a highly localized area
# 17
Modification to a sensitive net
Net 2
310
450
Net 3
300
400
290
Net 2
350
280
Net 3
300
270
Net 1
Net 2
260
Net 2
250
250
Net 1
50
100
150
200
250
240
180
190
200
210
220
230
240
250
250
• After comparing the identified sensitive nets with PCB layout, three nets
have been identified to be sensitive to ESD
• The sensitivity of those nets have been quantified in terms of applied
voltage in the HV generator
• Induced current direction on the each sensitive net has been identified
# 18
Modification to a sensitive net
Simple Low Pass
100ohm
TX
RX
330pF
Filter Location
# 19
Modification to a sensitive net
Before
After
460
460
440
440
420
420
400
400
380
380
360
360
340
340
320
320
300
300
280
280
260
260
60
80 100 120 140 160 180 200 220 240 260
60
80 100 120 140 160 180 200 220 240 260
Filter location
# 20
Direct coupling to ICs
310
305
Medium Magnetic Probe
300
295
290
285
Scanned Area
280
275
70 75 80 85 90 95 100 105
• The top side of the PCB is scanned using the medium size magnetic probe with
four different polarization
• Some sensitive areas on the IC are identified
# 21
Direct coupling to ICs
Signal couples directly into the IC
IC reacts to narrow pulses much
narrower than the intended signals
0.5
40
0
30
-0.5
V
35
25
-1
20
-1.5
15
-2
10
300ps
-2.5
2.5
5
5
10
15
20
25
30
35
3
Time [ns]
3.5
4
40
For such an ICs, no PCB or shielding solution is economical.
Scanning can identify such situations and help to verify improvements
in the IC design, packaging (e.g., flip-chip) or the control software.
In our experience, direct coupling to ICs is growing problem:
• Fast IC process technology is used more and more in badly shielded products.
• Coupling to PCBs is reduced by burried layers and traces
• Dense PCBs have hardly any traces visible (BGA packages)
# 22
New is better, well ….
Shown are the voltage settings of a pulse generator at which an upset occurs if
A narrow pulse (less than 300 ps width at 50% amplitude) is causing an upset of the IC.
Note: the new IC performed worse!
Worsening ESD soft-error performance is a significant risk if new processes
are introduced, or if I/O structures are modified.
# 23
Voltages on traces
Trace voltage [V]
8
6
4
2
0
-2
-10
-5
0
5
time [ns]
10
15
20
Trace voltage [V]
8
6
4
2
0
-2
-2
# 24
-1.5
-1
-0.5
0
time [ns]
0.5
1
1.5
2
How measure in-circuit while pulsing?
Semi rigid coax cable, connected to 20GS/sec
6 GHz bandwidth scope
The trace is loaded
by 470 + 50 Ohm.
GND VIA
(close to the
Trace)
470 Ohm
# 25
The small loop area
ensures little dB/dt
coupling and good
frequency response
of the probing
method.
Voltages on a status line
1.4
Coaxial Probe
attached here
connects to
another IC
75ohm
1.2
IC
of interest
100pF
Inner layer trace
1000
75ohm
75ohm
Pulse injection
here
Voltage[V]
56pF
1
Very Narrow pulse on
slow status line (< 150ps)
leads to crash
connects to
another IC
0.8
56pF
0
1
2
3
Time [ns]
 Three traces have been isolated by terminating/filtering circuits
 Double pulse has been eliminated
 The reset line still reacts to this narrow pulse (the system crashed)
 It has been shown that the IC of interest is causing the crash, reacting
# 26
to a very narrow pulse
4
5
Differential clock
315
Clock_N
Clock_P
310
305
Clock_N
(Ch 1 on
scope)
300
295
290
290
285
285
200 202 204 206 208 210 212 214 216 218
280
200ps pulse
injection
here!
Clock_P
(Ch 2 on
scope)
275
270
Pulse has been applied repeatedly, increasing
the voltage until system crashes
265
208 210 212 214 216 218 220 222 224
# 27
Waveforms are recorded (20 GHz / 6
Gsample/sec).
ESD Event on differential clock
Coaxial Probe
attached here
50
Drive IC
33
Pulse injection
here
50
Voltage on trace [V]
33
Receiver
IC
-5V, on DP, crashed - 2
0.8
0.4
0
0
10
Voltage difference
Voltage[V]
1
Very sensitive to noise
the transition
#during
28
20
crash
0
-1
0
10
20
Time [ns]
1
0
0
4
Voltage[V]
1
16
20
-8V, on DP, Crashed - 2
1
crash
0
0
4
1
0
-1
8
12
Voltage difference
Voltage on trace [V]
20V, on DP, Not crashed - 1
2
Voltage[V]
Voltage on trace [V]
ESD Event on differential clock
No crash!
0
4
8
12
Time [ns]
16
20
8
12
Voltage difference
16
Crash
threshold
: approx. 0.2V
0
-1
0
4
8
12
Time [ns]
16
Crash threshold
: approx. 0.2V
Clock_P
+
Clock_N
# 29
20
Differential input
has an offset
-
20
Noise increased differential voltage
13V, on DP, crashed - 2
Voltage on trace [V]
2
1.5
1
0.5
0
-0.5
0
5
10
15
20
25
20
25
Time [ns]
Voltage difference
1.5
Voltage[V]
1
0.5
0
-0.5
-1
0
5
10
15
Time [ns]
The result is repeatable. Increasing difference should not lead to a system crash.
#Why?
30
Voltage on trace [V]
ESD on differential clock – Common Mode disturbance
2
No crash
If the common mode voltage is
relatively low, the differential input
will suppress the common mode
signal.
2x330
1
0
0
4
8
12
16
20
16
20
Voltage difference
Voltage[V]
1
0
-1
# 31
0
4
8
12
Time [ns]
Common mode: Not crashed
CK PE 100M ICH DN/DP(inject on DP/DN -100V)
Voltage on trace [V]
2
1
0
-1
no crash
-2
-3
0
2
4
6
8
10
12
Time [ns]
Voltage difference
14
16
18
20
18
20
Voltage[V]
1
0
no crash
-1
-2
0
2
4
6
8
10
12
Time [ns]
14
16
No crash, although the differential signal is already strongly disturbed
# 32
Common mode: Crashed
CK PE 100M ICH DN/DP(inject
CK
on DP/DN
PE
120V)
100M ICH DN/DP(inject on
Voltage on trace [V]
3 3
2 2
1 1
0 0
-1-1
0
02
4
62
8
10
4
12
Time [ns]
Voltage difference
14
16 618
20
16 618
20
8
10
12
Time [ns]
Voltage difference
1 1
Voltage[V]
Voltage[V]
Voltage on trace [V]
4 4
0.5
0.5
crash
0 0
-0.5
-0.5
-1-1
0
02
4
62
8
10
4
12
Time [ns]
120V from the HV generator was
injected on both Clock_P and
Clock_N
 Crashed
# 33
14
8
10
Time [ns]
Differential Mode is about as robust
as single ended signaling. Design
details matter: (conversion, common
mode termination etc.)
12
How an IC can react to pulses
• Voltage surpasses threshold for a sufficiently long time
• Linear network, bond wire inductance and input
capacitance, ring or peak the pulse, leading to a
softerror.
• Voltage triggers non-linear effect on the input buffer
• Voltage causes ESD protection to forward bias, causes
substrate injection or internal power fluctuations, leading
to crash
• Current leads to latch-up, or latch-up like situation.
# 34
Open Questions
 Immunity problems caused by global coupling vs.
local coupling to one trace.
 Correlation system level – board level.
 IC level immunity test methods and robustness guidelines
for IC design are not well developed yet.
 IC level immunity standards.
 Software for improving immunity.
 Latch-up and ESD protection circuit recovery, how many
of the observed soft errors are caused by latch-up?
# 35
Conclusion
 Using local injection the disturbed traced can be identified.
 The sensitivity of I/O ports can be quantified.
 These data can be used to analyze the function of circuits
designed to reduce ESD sensitivity.
 In-circuit measurements can be done while doing local
injection, as the amount of common mode signal is vastly
reduced.
This is a developing field, many questions are still out there,
just waiting to be solved.
# 36
IC and system level ESD testing
IC ESD
System level ESD
Consequence
Destructive
Destructive and Upset
Standard
CDM / HBM / MM
IEC 61000-4-2
Voltage
Typically < 3000
Typically < 15 000
DUT
IC, sub system
System
Operating?
System is not powered
System is operating
Application method
Direct to the IC PINs
Enclosure, PINs
Tested properties
IC protection circuits
System design
When does it occur?
Manufacturing, handling
Qualification tests,
Customer site
# 37
Example: Identifying sensitive nets
Induced Current
on the net
Probe
Polarization
• The board has been scanned with four different probe polarization (up,
down, left, right) to take account of the induced current on the board
• The medium size magnetic field probe was used with 1.5mm x 1.5mm
scan resolution
• ESD sensitive net can be identified roughly, but the resolution is not so
fine enough to pin point a single trace.
# 38