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TED Integrated tool set for electro-thermal evaluation of ICs Pultronics Inc. Outline Introduction Pultronics approach Algorithm description Test results Conclusion Increasing heat flux Heat flux exceeding 10 W/cm2 High temperatures Failure rate doubles approx. every 10oC Technolo gy Devices Power [W] Size [mm2] Heat Flux [W/cm2] Intel Pentium 0.35µm Pro BiCMOS 5,500,000 30 195 15.30 UltraSPARC II 0.35m CMOS 5,400,000 25 149 16.77 Exponential X-704 0.5µm BiCMOS 2,700,000 85 150 56.67 Impact on expected performances Device mismatch thermal offset signal level mismatch decreased noise margin Thermally induced signal delay Reliability electro-migration Solution -> electro-thermal analysis Previous work Thermal solvers [Wuns97] Thermal solvers FEM, FDM Fourier series Analytical Precision High Medium to low Medium to low Complexity High Medium Low Execution time High medium low Limitations Limited set of Flat sources in semi geometries, systems, infinite substrate boundary conditions Type of system Applicability Memory Execution time a Very few sources Flat sources on multi- High number of in a complex layer substrate sources but in simple system system Device level Device System Small system Large number sources of History 1977 - Fukahori, coupled set of electro-thermal equations to model device 1986 - Smith, temperature distribution for GaAs FETs, analytical solution 1993 - Lee, Allstot, electro-thermal simulation, FDM, relaxation 1994 - Petegem, relaxation, FEM 1996 - Szekely, direct coupling, Fourier series 1996 - Szekely, electro-thermal and logi-thermal 1997 - Wunsche, relaxation, FEM, transient analysis TED characteristics integration within design framework r/w access to design database efficient electro-thermal analysis sufficiently precise fast (thermal, electro-thermal) robust in memory usage automated modular and extensible Used approach Simulator coupling smaller circuit, lower node count, memory efficient, faster simulation time Analytical solution fastest and sufficiently precise One extraction, one netlist No changes to the device model, no additional masks for extraction R/W Access to design database Electro-thermal loop / Flowchart begin initialize circuit simulator power update circuit simulator dual netlist initialize thermal simulator thermal solver Temperature update Y Temperature converges Assign new temperatures N Thermal algorithm Steady state heat conduction (kT) q Solution for point heat source Thermal algorithm Kirhoff’s integral transformation to accommodate k=f(T) 1 T T 0 k (T 0 ) k(T ) dT T Back transform n n 1 ( n 1 )( T ) n 1 T Τ T 0 0 Thermal algorithm Additional features modeled metal interconnects substrate depth boundary conditions element grouping Verification against FEM solver Device thermal model GaAs substrate temperature dependent conductivity 50x0.6mm DFET device only no metal 50 mW dissipation boundary conditions forced 50oC on the bottom side and top walls non conducting 50 oC 3D model constructed for FEM solver (FlexPDTM) 5-20k nodes mesh 10min+ execution time, PC, PentiumII Mutual heating, 2 DFETs, 30mm spaced Superposition of thermal effects Dangerous when clustering dissipating devices Temperature distribution in presence of metal interconnects 1 FET with metal 50 oC Thermal conductivity device-metal important heat flux through metal path Over-estimated temperatures if not modeled new model required New method versus full 3D Result- very good match Tmax = 98.5 oC Tmax = 95.8 oC Full device Pultronics model Examples Bi-directional buffer, 0.6mm GaAs Bi-directional buffer 650 devices transient analysis 3 iterations (max temperature 144, 65.5, 68 oC) thermal analysis - 1 to 10 sec / iteration HspiceTM - 2.5min / iteration Calculated thermal map Different boundary conditions defined for NW and SE GaAs, operational amplifier operational amplifier, GaAs different temperatures for parallel devices self-heating model not sufficient Output stage Thermally induced offset Operational amplifier, GaAs local temperature raise (output stage) Constant T device mismatch offset voltage Updated T Major contribution Development of global methodology allowing practical steady-state electro-thermal analysis of large integrated circuits within much shorter execution time than existing one applicable for very large circuits Development of algorithms necessary to implement the methodology Development of algorithm allowing thermal modeling of integrated circuits with metal interconnections Electro-thermal evaluation of chosen circuits (HBT, GaAs)