Download ESD Dynamic Methodology for Diagnosis and

2012 EOS/ESD Symposium
ESD Dynamic Methodology for
Diagnosis and Predictive
Simulation of HBM/CDM Events
Ting-Sheng Ku, Jau-Wen Chen, George Kokai,
Norman Chang, Shen Lin, Yu Liu,
Ying-Shiun Li, Bo Hu
Outline
●
Introduction
●
ESD dynamic analysis methodology
●
Requirements for ESD dynamic simulation
●
Application Examples
●
Summary
Slide 2
Worsening Trend in ESD
●
Thinner oxide, lower junction
thermal breakdown voltages
●
Reduced failure current
density limit
●
Worsening CDM issue for
high-frequency designs
White paper 2: A case for lowering component level CDM
ESD specifications and requirements, April, 2010 Slide 3
ESD Dynamic Analysis Methodology
●
Perform diagnosis of potential failure mechanisms when
silicon failures occurred
●
Verify fixed solution robustness by comparing differential
stressed values of the failed junctions
●
Strategic check on potential CDM design weaknesses
before tape-out on mixed-signal / IO blocks
Slide 4
Target Applications for ESD
Dynamic Analysis
●
Initial target users are ESD experts
●
Eventual usage by mixed-signal macros designers
●
Transistor count per macro : ~200K in most cases and
can go up to ~1M
●
What can a dynamic ESD check provide beyond a
static one?
●
●
●
●
Physically correct modeling of CDM discharging behavior
Explicit detection of worst transient voltage stressed junctions
Evaluation of clamp transient effectiveness related to design
and placement
Ability to perform trade-off on peak versus duration device
failure mode
Slide 5
Cross-domain Check and Possible CDM Failure Mechanism
•+
VDD1
VDD2
Power
Power
Clamp
Clamp
1
Vgs
VSS1
1
VSS2
GND
Rbus
for possible Vgs junction failure due to disparate discharging rate
from gate and source nodes to CDM grounded pin.
See more CDM checks in “ESD Electronic Design Automation Checks”,
Technical report # TR 18.0-01-11
Outline
●
Introduction
●
ESD dynamic analysis methodology
●
Requirements for ESD dynamic simulation
●
Application Examples
●
●
HBM event
●
CDM event
Summary
Slide 7
Requirements for ESD Dynamic
Simulation
●
●
Modeling
●
Handling of snap-back
behavior in clamp
●
P/g RLC and coupled signal RC
●
Substrate R/C and Well diodes
●
Nonlinear devices modeling w/
high voltage consideration
High performance and large capacity for the
post-layout macro designs
Metal Grid RLC and Substrate Model
• Metal grid L extraction needed in addition to RC for fast slew rate
• Extraction of substrate well diodes and RC grid
• Modeling of distributive effect due to substrate
P-well
N-well
P-substrate
Slide 9
Modeling of Capacitance between Chip
Substrate to Charging Plate
●
●
Cdut is defined as between the silicon die and metal lid that is
separated by Thermal Interface Material (TIM)
This figure of merit can be used to tune the Ipeak of Pogo pin
to match user’s expected Ipeak in simulation
Courtesy of J. Karp, EOS/ESD Sym 2008
Slide 10
The Impact of Simulated Block Size on the
Stress Ranking and Value
It was observed that the target CDM and HBM simulation block size can
be reduced from full-chip to a smaller circuit block containing the zapping
pin. The requirements are
1. Primary ESD discharge paths must be included
2. Simulation coverage is limited to the simulated circuit block only
3. The Pogo pin peak current can be maintained through tuning of
substrate_to_gnd_cap to satisfy JEDEC standard
Following these steps ensure consistent absolute stress value. More
importantly little impact on failure junction ranking
Slide 11
Smaller circuit block
Bigger circuit block
Block-based ESD Dynamic Flow
●
●
●
●
Import DSPF (Detailed Standard Parasitic Format) of coupled signal
RC netlist and create P/G contact pins
Extract metal grid RLC, substrate RC, and well diodes
Hook up the two netlist above through contact pins and create test
bench for HBM or CDM zapping condition
Perform the simulation on the final netlist above and generate
junction stress report
Slide 12
Outline
●
Introduction
●
ESD dynamic analysis methodology
●
Requirements for ESD dynamic simulation
●
Application Examples
●
●
HBM event
●
CDM event
Summary
Slide 13
HBM Case Comparison :
Failed/Passed Test due to Grounded vs. Floating
P-well Guard Ring in RC-based Clamp
• Both test cases with AGND -2000V HBM zap and AVDD
grounded
• Case with P-well guard ring grounded failed HBM test,
while case with P-well guard ring floating passed
AVDD
Pwell guard ring
grounded
sig
_
AVDD
Pwell guard ring
floating
sig
_
AGND
Failed clamp
AGND
Passed clamp
Slide 14
Snapshot of HBM Failure Case
AVDD
P-well guard
ring grounded
sig
_
AGND
Failed clamp
Lab de-processed result of failed HBM test
on I/O with P-well guard ring grounded
Slide 15
HBM Test Case
• Device count :
12K subckt (xmos), 6K Diodes
• Extracted elements:
5.79M RLCs
• Simulation Conditions: Initialized at -2000V (HBM test)
Zap
Init at -2000V
3.0u
1525ohm
AGND
VDD
P/G RLC
100pf
0.1f
AVDD
Macro Block
w/ coupled signal RC
GND
Substrate RC w/ Well diode
HBM Analysis
setup – 48min
simulation : 16hr
Peak memory – 15 GB
Slide 16
HBM Failure on Melt-down of Center Finger of
RC-based Clamp Due to Parasitic BJT Turn-on
• Center finger furthest from Pwell grounded guard ring resulting in largest
resistance from the AGND zap point
• Vbs of finger higher due to substrate node distance from Pwell guard ring
• Higher Vbs of center finger with higher Ids current may turn on parasitic
bipolar earlier than other fingers, causing center finger melt down
AGND
X
AVDD
Center Finger of RC-based Clamp
Slide 17
D/G/S/B Node Waveforms of the RC-based Clamp
Fingers with Substrate Pwell Guard Ring Grounded
1.37ns
Vg
Vd
Vb of
different
fingers w/
the center
finger having
largest Vbs
Vs
Vbs of different clamp fingers are very different in amplitude,
with center finger having largest Vbs making non-uniform turn-on
of the center finger, and triggering its parasitic BJT
Slide 18
D/G/S/B Node Waveforms of the RC-based Clamp
Fingers with Substrate Pwell Guard Ring Floating
1.37ns
Vg
Vd
Vb of
different
fingers
Vs
Vbs of different clamp fingers are similar in amplitude,
making the uniform turn-on among all fingers
Slide 19
Worst Stress Movie for HBM
AGND -2000V Zap with Hot Spot on Center
Finger of RC-based Clamp
Hot spot at 1.37nsec of the HBM zap at the center
RC-based clamp finger
Slide 20
Outline
●
Introduction
●
ESD dynamic analysis methodology
●
Requirements for ESD dynamic simulation
●
Application Examples
●
●
HBM event
●
CDM event
Summary
Slide 21
Example CDM Test Case
• Device count :
62,256 subckt (xmos), 541 Diodes
• Extracted elements:
3,709,648 RLCs
• Simulation Conditions: Initialized at -500V (CDM test)
Lpogo
Zap
Rpogo
IOP
ION
P/G RLC
VDD
VDDP
Cpogo
Macro Block
w/ coupled signal RC
GND
Substrate RC w/ well diode
CDM Analysis
setup - 1hr20m
simulation : 8hr25m
Peak memory – 25 GB
Cdut of 3pF evenly distributed among
substrate and can be tuned to match
expected pogo pin peak current
Slide 22
Example CDM Failure due to Race Condition
in Discharging Paths
Worst
Junction
Worst junction voltage waveform
Pogo pin current waveform
• Impedance mismatch between I/O (sig) and LDO bias net caused
large Vgd junction stress on -500V zap due to bias net being heavily
referenced to ground
Slide 23
Stress Movie on the CDM Test Case :
IOP Zap at -500V
-500V Zap at IO Pin
Highest stress occurred at failed junction (Vgd) on the top
around 137psec; the 2nd ranked stressed junction with the
similar design issue except the IO transistor size is much larger
Slide 24
Failure Emission Image for
the CDM Test Case
emission site
Lab emission result of failed CDM test on high-speed I/O
Slide 25
Addition of PMOS Passgate as Proposed Fix
for Failed Junction Stress Reduction
PMOS passgate inserted
Worst junction voltage waveform
• PMOS passgate inserted at gate of failed NMOS serves to
isolate junction from loading the bias net, which allows
junction voltage delta to stay within device tolerance
Slide 26
Summary
●
With tighter design margin in 65/45/28/20nm
technology nodes, ESD verification is a must for
SoC, mixed-signal design, and custom designs
●
A comprehensive ESD dynamic methodology
outlined for diagnosis and predictive simulation
of HBM/CDM discharging events
●
Example test cases with failure point correlation
between simulation and silicon measurement
provided
Slide 27