Download Efficient Multi-domain ESD Analysis and

Efficient Multi-domain ESD Analysis and Verification for
Large SoC Designs
Norman Chang, Youlin Liao, Ying-Shiun Li, Pritesh Johari, Aveek Sarkar
Apache Design Solutions, Inc., 2645 Zanker Road, San Jose, CA 95134 USA
tel.: 408-457-2012, e-mail: {norman,youlin,ying,pritesh,[email protected]}
Abstract –An efficient layout-based multi-domain ESD analysis and verification method has been
developed for large SoC designs containing thousands of bumps. A fast resistance and current density
check for ESD discharging paths across multiple diodes/clamps represented as I-V curves is
performed, including on-chip signal/power/ground/package grid. Real application examples are
shown.
I. Introduction
Given the complexity of today’s System-on-chip
(SoC) designs, with higher resistance of power
and ground meshes, increased device density, and
greater sensitivity to device/metal structures
breaking down in submicron technology nodes,
the proper design and placement of electro-static
discharge (ESD) protection circuitry has become
quite critical [1]. Most engineering teams use
well-defined rules for placement. However,
advanced verification technologies aimed at
checking the proper placement and connectivity
of the protection circuitry are either not available,
or rarely used. Visual inspection, plot checking,
and design rule based checks are usually
employed, although these methods do not provide
sufficient verification coverage to ensure: (a)
proper connectivity is maintained; (b) the overall
resistance of discharge paths is below threshold
limits; and, (c) junctions/wires are not subjected
to breaking down from the discharge current and
voltage build-up. Also schematic-only ESD check
may not provide actual discharge path resistance
from the layout. Therefore, efficient layout-based
multi-domain ESD analysis and verification is
required to address the needs of large SoC
designs containing several hundred package pins
in a wirebond package or thousands of Controlled
Collapse Chip Connection (C4) bumps of a flip
chip package [2,3].
II. Static ESD Check Methodology
We are outlining a technology that is intended for
verifying, at the full-chip level, the placement and
connectivity of ESD protection circuitry for
various discharge mechanisms. Figure 1 outlines
the analysis flow. One of the input data is the
layout of the SoC (usually in the form of a
DEF/GDSII file), which provides all the
power/ground/signal geometries (wires and vias)
connecting the ESD circuits to the pads. The
layout also contains placement information for
the standard cells, memories, pads, analog blocks,
and the diodes/clamps. Other input includes the
ESD rules defining the maximum allowed
resistance between various structures such as a
pad to a clamp cell, one clamp cell to another; or
one pad to another pad. For the current density
analysis, users also need to provide the I-V
curves of diodes/clamps and the peak ESD
electro-migration (EM) limits for metal/via
layers.
Figure 1: Full-chip ESD verification flow.
Two broad categories of checks were performed.
The first check was to ensure all the pads were
connected to the clamp cells in one or multiple
stages and have proper discharge paths to
grounded pads; meeting the associated design
rules (for HBM and MM discharge events). The
second check was to ensure all the
instances/transistors in the circuit have proper
connectivity to the clamp circuits (for CDM
discharge events). For the first category of
checks, the tool is used at the full-chip level to
measure the effective resistance between the
following elements: a pad to a clamp cell, a pad
to another pad through one or more clamp cells,
and a clamp to another clamp. It performs this
calculation using a built-in, multi-threaded, high
capacity extraction and simulation technology.
The resistance limits are defined, for example,
between a pad to a clamp and from one pad to
another pad.
Figure 2 illustrates the technique employed for
verifying a pad (e.g. a power pad “VDD bump
A”) to pad (e.g. a ground pad “VSS bump B”)
connection through diode/clamp cells. First, the
loop resistance from the power pad to the ground
pad through each of the three clamps is verified
individually. This is done by solving for the
conduction path between pads through the power
and ground wire and via structures. If the
conduction path through any one clamp does not
meet the loop R threshold limit, that path is
eliminated from the final effective resistance
computation between the two pads. Assuming the
remaining two clamps do meet the loop threshold
criteria (and are observed participating in the
ESD discharge event), the subsequent effective
resistance calculation between the two pads is
performed, with Ron used for the two clamps. The
individual loop R is defined as the effective
resistance for the bump pair considering only one
possible on-clamp path as shown in Figure 3. The
loop R threshold and effective parallel R limits
are defined by the users for the designs. For
example, the loop R limit can be set as 4 ohms
and effective R limit can be defined as 2 ohms [4]
for a typical design. By using this technology for
large SoC designs with multi-million gates, the
analysis of more than 1000 bump pairs covering
thousands of clamp devices in the P/G mesh
network usually takes less than five hours. The
HBM/MM analysis can also be done, including
the package netlist, with several hundreds of pins.
Figure 4 illustrates the HBM/MM check from a
signal pad to the power/ground/signal pads that
are typically found on an IO circuit.
Figure 2: HBM/MM check through multiple diodes/clamps.
Figure 3: Individual loop R for a bump pair through
power clamps (PC).
Figure 4: HBM/MM resistance check for I/O pads where D*
are diodes, PC* are power clamps, and P* are signal pads.
For the full-chip static ESD check, the substrate
resistance network do not need to be included in
the analysis due to its higher resistance compared
to the resistance of the metal layers. Therefore the
loop R or effective R of a bump pair will not be
affected, without or with the substrate R network.
On the other hand, the package resistance netlist
should be included since it provides lower
resistance paths between wirebond pads or C4
bumps. In HBM analysis, an individual loop with
minimum resistance path will help diagnosis a
large effective resistance failure of a bump pair.
For the 2nd category of checks (CDM check) [5],
the tool finds the smallest resistance from a
power/ground node of an instance to the near-by
clamps. If the instance is a large macro (for
example, custom macro), more power/ground
locations of the macro are checked for their
resistance to their respective near-by clamp. This
instance-clamp loop check is illustrated in Figure
5. If a large resistance exists between a macro to
the clamp outside of a macro, static analysis will
provide first level check of the potential CDM
issues. In addition, the resistance on
power/ground nodes of a cross-domain pair (i.e.
driver-receiver pair with different power or
ground domains) can be checked for similar
resistive values. If the resistance value is very
unbalanced between driver-receiver pair, it would
possibly indicate a potential problem for large
Vgs stress on the receiver circuitry. Due to subnanosecond
discharging
waveform,
a
comprehensive CDM check analysis, that
considers metal layer L/C, die substrate R/C and
well diodes are needed, such as the technology
that is described in [6].
Figure 5: the CDM loop R check for standard, memory/IP,
and IO cells.
The above-mentioned ESD check methods can
also be applied to an early floorplan stage where
the top-layer power/ground mesh is designed and
before detailed instance placement is available.
Clamps can be easily added to create initial ESD
protection design implementation as shown in
Figure 6. This enables designers to perform whatif analysis and optimization in early design stage
as well as in late stage fine-tuning for clamp
placement.
Figure 6: ESD cells can be optimized in the early analysis
flow.
III. Discharging Current Density Check
An innovative and robust method has been
developed for analyzing ESD current density in
multi-million gate SoC designs. It verifies the
ability to handle a high current flow of the wires
and vias in ESD protection implementation, by
checking the current density against the
established ESD EM limits. The analysis also
provides the voltage stress levels in the design
during HBM/MM/CDM discharge events.
For analyzing a HBM/MM ESD event, we apply
a zapping source to a pair of pads, or through a
pair of package pins, and perform DC analysis to
determine and report:
a). among hundreds/thousands of clamp devices,
the ones that are turned into ‘on’ state and
provide ESD discharging path. The non-linearity
in I-V characteristics of snapback clamp or diode
is included in the analysis.
b). The voltages and currents in the design
including that in all clamp devices, and EM
percentages for the wires and vias are computed
based on the state of the art ESD EM rules and
limits.
Figure 7 shows a pad-to-pad ESD check through
possible multiple discharging paths, with the
typical I-V curves for a snapback clamp or diode
(simple turn-on without snapback), shown in
Figure 8. I-V curves of diodes/clamps are usually
provided from the foundry or in-house TLP
measurement. Simulation containing multiple
iterations will determine which clamps are on or
off and its I-V value will lay on their respective IV curves. Therefore the resulting current density
on wires and vias represent a most likely scenario
that need to be checked against ESD EM limits.
Figure 7: Current density check of an HBM/MM event with
diodes/clamps represented as I-V curves.
Figure 8: Typical I-V curve for a snapback clamp and I-V
curve for a diode is a degenerate case with Vh=Vt1.
For ease of use, the tool also allows users the
flexibility to determine the clamp devices that are
involved in a particular scenario. The user can
instruct the tool to include and analyze a
particular list of clamp devices; or analyze one of
the scenarios as in the pad-to-pad resistance
check, where the loop R threshold is used to
select on-state clamp devices. Hundreds and
thousands of pad-to-pad pairs can be analyzed
automatically with minimal user intervention.
Performing current density analysis for pad-topad ESD event as described above helps study
particular HBM/MM events. At the same time as
part of the ESD sign-off coverage test,
systematically analyzing the important ESD
protection paths provides assurance for a
successful tape-out.
For example, as the I/O pads depicted in Figure 4,
the ESD current density checks can be
automatically performed for every pad-to-clamp
pair, (P* to D*). For this situation multiple I/O
nets are simulated in parallel, since they are
disjoint in the layout space, and the execution is
very quick. If multiple fingers of ESD
diodes/clamps are extracted in the current density
flow, it can be used to study the non-uniform
current flow through the fingers as shown in [7].
For CDM events, it is crucially important to make
sure that the critical connections in the layout
have adequate capacity to sustain the high
currents and at the same time, low enough
resistances to provide protection against high
voltage stress levels. For example, as in Figure 4,
the paths between the HBM/CDM diodes and the
power clamps are designed to provide lowresistance discharge path during a CDM event, so
that the design components connected along these
paths will sustain low enough differential
voltages. Our tool can perform hundreds and
thousands of simulations for these paths
automatically, and report the EM violations and
voltage stress levels on the design elements.
The results for ESD current density simulations
are stored in the database and are readily
available to load into a GUI for closer look at
analyzing and debugging the layout problems.
Figure 10: Histogram of a bump2bump analysis result.
IV. Application Examples
Two application examples are shown using the
ESD checking methodology outlined above. The
first example is an HBM/CDM analysis with 162
power/ground pads for a complex SoC design, as
shown in Figure 9. A histogram can be generated
for Bump2Bump analysis as shown in Figure 10.
Figure 11 shows that a large discharging path
resistance issue is identified when performing a
CDM analysis (i.e. resistance check between
instance power/ground nodes and near-by
clamps) on the same example. A typical problem
occurs when the instance is inside of an IP, while
the cross-domain clamp is outside the IP [5], and
the designers does have no control on their
placement.
Figure 11: Layout issue identified in the connectivity of a
core instance to its near-by clamp during CDM analysis.
The second example is a very large SoC (40M
instances) with about 20 power/ground and 600
signal domains, as shown in Figure 12. The run
time to perform the Bump2Bump checks
covering several thousand power/ground/signal
bumps and including discharge paths across
multiple P/G domains connected by clamp
devices, is shown in Figure 13
Figure 9: Full-chip HBM analysis result on a complex SoC.
Figure 14: Current density map of the VSS->D5 diode->
Figure 12: an example of large SoC Chip.
AVSS->D2 diode->P2 signal_pad (refer to Figure 4)
with -2000Volt zap at P2.
Figure 13: Run time and memory usage.
ESD check on IO part of the design, similar to
those shown in Figure 4, found a high effective
resistance path from VSS bump to Pad p2,
through back-to-back diode and diode D2*. This
failed the HBM testing. Further ESD discharge
path analysis uncovered high resistance between
D5 to D2, which caused the HBM failure with 2000Volt zap at P2. Figures 14 and 15 show
corresponding current density and ESD EM maps
from current density check. For diodes/clamps,
all the fingers are taken into account since the
current flow may not be uniform throughout the
finger arrays. Also, after the current density
analysis, all of the node voltages are available
and can be used to check the power/ground pin
voltages of the cross-domain instances as shown
in Figure 16.
Figure 15: ESD EM map shows the HBM failure on P2 and
AVSS nets.
Figure 16: Voltage difference check on
Vdd1/Vdd2/Vss1/Vss2 during HBM current density check
on driver-receiver pair.
V. Summary
We have outlined a comprehensive ESD analysis
and verification methodology for static
HBM/MM/CDM
layout-based
resistance
checking. A high-capacity pin-pair (or bump-pair)
HBM/MM check was developed to meet the
needs of large SoC ESD verification, including
on-chip power/ground/signal grid and package
netlists. This innovative and robust method for
current density checking can simultaneously
consider multiple snapback (or non-snapback) IV curves to reach an analysis result. Two
application examples have been provided, and
their problems have been identified and
illustrated to highlight the critical importance of
full-chip ESD analysis and verification.
Acknowledgements
We would like to thank J. Wang for providing
ESD domain expertise at early phase of the
project. Thanks to D. Tremouilles for providing
much feedback on the paper. Also thanks to J.
Pollayil, K. Sahni, K. Srinivasan, J. Kook, A.
Kitahara, H. Lee, Y. Liu, S. Lin, D. Yang, and A.
Yang for providing continuously stimulating
discussion on solving real world ESD problems.
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