Download A 100MS/s 10-bit Split-SAR ADC with Capacitor Mismatch

2016 IEEE 25th North Atlantic Test Workshop
A 100MS/s 10-bit Split-SAR ADC with Capacitor
Mismatch Compensation Using Built-In Calibration
Yongsuk Choi and Yong-Bin Kim
College of Engineering
Northeastern University
Boston, MA, USA
[email protected], [email protected]
In-Seok Jung
SIC Center IPT Team
LG Electronics
Seoul, Korea
[email protected]
increases the area needed for the capacitor array as well as the
input capacitance during the sampling phase of operation. As
a solution to minimize the size of the capacitor, split
capacitive DAC is widely used [3]-[4]. In spite of the spatial
advantage, the split capacitive DAC has a major drawback,
which is high sensitivity to the parasitic capacitors that
destroys the desired binary ratio of the capacitive DAC array
causing degradation of the conversion linearity. Consequently,
the capacitor mismatch compensation is an essential technique
to design high performance ADCs. There are many published
capacitor mismatch calibration methods to resolve the
linearity problem [3].
Abstract—A 100MS/s 10-bit ADC design using a 130nm
standard CMOS technology is presented in this paper. The
proposed design adopted the split capacitor array digital-toanalog converter (DAC) to build successive approximation
register (SAR) analog-to-digital converter (ADC) structure
using a single input. On-chip mismatch calibration feature is
utilized to compensate the capacitor mismatches of the DAC
and to calibrate the input offset voltage of a comparator. The
proposed calibration uses a simple and efficient algorithm and
optimizes the capacitor mismatches of the DAC by using
inverter-based capacitor comparison technique and by
controlling additional auxiliary capacitor arrays in calibration
mode. The ADC achieves 41.9dB of SNR and consumes 1.1mW
with 1.2V supply voltage.
Especially in the SAR based ADC design case, there are
several challenges that make it more difficult to accomplish
high resolution using single-ended input due to the capacitor
array mismatch on charge redistribution and offset voltage of
the comparator. For independent DACs on general purpose,
the dynamic element matching (DEM) technique accepts
matching errors as inevitable and dynamically rearranges the
interconnections of the mismatched elements so that all
element values are nearly equal to the average [5]. However,
because the DAC in SAR ADC usually operates with binary
search algorithm and consists of binary weighted capacitor or
resister, the DEM is not suitable technique for DAC in SAR
ADC. Therefore, as an efficient solution of the problems, a
single-ended input SAR ADC using a self-calibration method
is proposed in this paper.
Keywords—successive approximation register (SAR) ADC;
spilt-capacitor array DAC; built-in calibration (BIC); offset
calibration; capacitor mismatch compensation
I. INTRODUCTION
Communication systems such as cellular radios, fiber
optic links, and cable modems employ analog-to-digital
converters (ADCs) in their receivers to convert analog signals
to digital signals. There is a growing trend in building alldigital receivers by moving the ADC, traditionally placed at
the end of the receiver chain, closer to the front-end [1]. By
doing so, many of the analog circuits such as mixers and
filters, can be implemented digitally to benefit directly from
technology scaling. On the other hand, with the scaling down
of CMOS technology, successive approximation register
(SAR) ADCs are widely used because of their high power
efficiency and small area. In a 10-bit resolution, the operating
frequency of the conventional SAR ADCs is increased up to
100MHz by asynchronous internal clocks, error compensation,
and capacitor switching techniques. Therefore, the SAR is an
attractive solution among ADC designs for portable and
mobile applications due to their inherent structural advantages
such as non-required amplifiers, lower power consumption,
and less area overheads [2].
Specifically, this paper presents a SAR based ADC design
using a charge-redistribution DAC with built-in calibration to
satisfy a high resolution and low power consumption. In this
work, we developed a design technique from our previous
work [6] to minimize capacitive area, and developed
mismatch compensation technqiue using the on-chip built-in
self-calibration (BIST) method.
II. COMPARATOR OFFSET VOLTAGE CALIBRATION
The input referred offset of a comparator in ADC degrades
the overall resolution of the ADC. The main reasons of the
offset voltage are the device mismatch of the differential pair,
parasitic capacitances of internal nodes, and device parameter
mismatches such as
and
. The offset voltage is
primarily correlated to threshold mismatch, current factor
mismatch, and transistor dimension as following.
A common way to design the SAR ADC is based on
charge redistribution with a capacitor DAC array which
consumes dominant area of the whole ADC. The ratio of the
largest capacitor to the smallest capacitor increases
exponentially with the increased number of bits. This
978-1-4673-8949-5/16 $31.00 © 2016 IEEE
DOI 10.1109/NATW.2016.9
1
M6
VIN+
M2
Vbias
Clk
VOUT+
M10
Di+
M4
M3
output nodes are monitored and fed back to calibration logic
to control the imbalance.
M15
VOUT-
Clk
Di-
M13 M14
Clk
Di-
VIN-
M8
M9
Di+
M7
Clk
M1
In Fig. 1, the comparator for the SAR ADC is illustrated
with capacitor arrays for offset voltage calibration. The offset
voltage of the differential input stage can be derived as [11]
M11
Cos+[0]
Cos+[4]
Fig. 1. Schematic of comparator with pre-amplifier for the SAR ADC and
capacitor arrays for offset compensation.
Vos
En
SHA
En
DAC cap.
array
In+
Out-
In-
Out+
En
Valid
En
Vcm
Cos-[4:0]
Cos+[4:0]
SAR
Logic
Offset
Controller
)=
√ ∙
,
(
)
=
√ ∙
,
+∆
,
.
(2)
In this section, an efficient and fast algorithm to
compensate DAC mismatch is introduced. In addition, the
inverter based comparison is proposed for an accurate
comparison of capacitors. The comparator in the ADC should
be able to detect the voltage difference at least 1 LSB. In the
10-bit ADC with 1V reference voltage, the 1 LSB should be
1V/210 = 0.976mV. However, the offset voltage in the
reported comparators used for offset calibration is larger than
10mV [12]-[13]. Therefore, a new capacitor comparison
technique is introduced, which has better accuracy than the
Fig. 2. Block diagram of voltage offset calibration for the comparator.
σ(
,
,
III. SAR ADC WITH PROPOSED CALIBRATION APPROACH
MUX
DAC
Driver
∆
Fig. 2 shows the overall block diagram of the voltage
offset calibration approach for the comparator. When the
offset voltage calibration mode is enabled ( signal is on),
input sample, and hold circuit is disconnected from the
comparator and digital control signals for the DAC driver is
reset to turn off all of the capacitors. In the meantime, both of
the comparator inputs are connected to the common-mode
voltage. The offset controller manipulates the offset capacitor
switches and once the binary codes are stabilized, the digital
bits for offset array is kept and the offset calibration mode is
disabled.
Vcm
VIN
+
/
) at the
Since the internal node capacitances (
differential output pair of pre-amplifier ( / ) can be
digitally controlled, the offset voltage can be calibrated. The
5-bit binary-weighted capacitor arrays (C [4: 0]/C [4: 0])
consist of metal-oxide-metal capacitors using PMOS
transistors.
Cos-[0]
Cos-[4]
∆
,
=
,
(1)
is the threshold voltage difference,
where ( =
/ ) is current factor difference, and both
and
are technology-dependent proportionality constants [7]. To
reduce the offset voltage in half, the transistor size needs to be
increased square, which means the sizing is not a practical or
efficient solution due to the cost of excessive power and area
consumption.
VIN
SHA
Cu
Calib.
Calib.
C10
Therefore, the impact of the mismatch becomes serious
with technology scaling. In addition, the matching of the
minimal size device degrades with scaling. This is an
important concern for the design of digital circuits since the
device mismatch starts affecting the noise margin and
mismatch mitigation techniques cannot be widely applied due
to their large area overhead. However, offset calibration is
necessary to efficiently achieve high accuracy. The basic idea
for the calibration is to deliberately introduce imbalance to
compensate the offset. Such imbalance can be either by
capacitance loading, current injection, or even voltage
difference [8]-[10]. In the offset voltage calibration mode, the
differential inputs are tied to common mode voltage and the
Caux_j
C6
Caux_f
Calib.
C5
Caux_e
Calib.
C1
Caux_a
C0
SAR
Logic
DAC
Driver
DATA OUT
M12
M5
VREF
ΔV
Calibration Controller
Register
Fig. 3. SAR ADC structure with comparator offset calibration and capacitive
DAC mismatch compensation.
2
α
C1
C0
C1
VREF/2
V1
C0
C1
β
C1
C0
C1
C0
C0
γ
C1
C2
C0
C1
C2
C0
VREF
α or β
(a)
CLK1
Reconfigure
CLK1
VREF1
C1
C2
C0
C1
C2
C0
V1
CLK2
α or β
C0
C1
V2
V3
VREF2
CLK1
Fig. 4. Capacitor comparison algorithm for DAC mismatch calibration
CLK2
conventional method.
A. DAC Mismatch Calibration in SAR ADC
Fig. 3 shows the proposed split-DAC based SAR ADC
structure and the main conceptual strategy of the proposed
self-calibration for DAC in the ADC to reduce capacitor
mismatch error. The calibration method adjusts the auxiliary
capacitors that are connected in parallel to each capacitor (C1C10) of the DAC to minimize the mismatch error. In the
calibration mode, the 4-bit control code for the auxiliary
capacitors determines to select additional parallel capacitances
in each of the capacitor. After all of the calibration procedures
for the 10 bits are done, each of the control codes are stored in
registers and the ADC operates without the calibration
controller preventing from additional power consumption.
(b)
Fig. 5. Capacitor comparison techniques (a) Conventional comparison
concept (b) Proposed ΔV sensing circuit
B. An Inverter-Based Comparison of Capacitor
In order to use the voltage comparator for the capacitor
comparison, the charge in capacitors should be converted to
the voltage level. A conventional capacitor comparison
technique is shown in Fig. 5(a). Both of the capacitors are
discharged at initial state, after that C1 is charged to VREF and
the input voltage of the comparator is given as
The DAC mismatch calibration algorithm is depicted in
Fig. 4. The main idea of the proposed algorithm is to decrease
possible branches among selectable cases, thereby decrease
calibration time and complexity of the controller circuit. The
case D increases complexity of the controller because it
requires to reconfigure and compare capacitor sizes in the
previous steps. This makes circuitry more complicated to
control the auxiliary capacitor switches.
=
(3)
which is half of the reference voltage in ideal. A drawback of
the conventional technique is that the difference (or C0/C1)
cannot be amplified. Therefore, the output voltage is smaller
than offset voltage of the comparator, which even leads to
increase mismatch errors.
The schematic of the proposed inverter based V sensing
circuit is shown in Fig. 5(b). When the CLK1 goes high, VREF1
is connected to V1 and then, V2 and V3 are shorted so that the
C1 is discharged. Therefore, the charge of C0 and C1 is given
by (4) and (5).
The calibration process starts with comparing the unit
capacitors and the capacitor for LSB, C0 and C1, as shown in
case A. Depending on its outcome, proper size of auxiliary
capacitor is added on either C0 or C1. Next, C2 is compared
with C1+C0 value. Ideally, C2 should be two times of the unit
capacitance, however, the C2 is designed 15% less than the
2C0 deliberately and the insufficient size of capacitance needs
to be added from auxiliary capacitor at the mismatch
calibration. In this way, all the capacitor values can be
calibrated from LSB to MSB array.
=
−
×
,
(4)
=0
=
3
−
×
,
=
−
(5)
×
Also, the comparison voltage V3 is finally driven as
=
−
+
(6)
where, V3 is decided by the multiplication between the ratio of
C1 and C2 and the difference V1 and V2. By adding the (V1 V2) term, V3 is amplified.
The outputs of the each technique can be easily compared.
As an example, for the 5% mismatch between C0 and C1, the
conventional capacitor comparison results in 13mV difference
with 1.2V reference voltage. On the other hand, output
voltage difference in the proposed design is 25mV when
VREF1 and VREF2 are 1.2V and 0.7V, respectively. For 10% of
the capacitance mismatch, the voltage difference shows
28.5mV and 50mV, respectively.
(a)
The V sensing circuits are only connected to capacitor
array of DAC when the self-calibration mode turns on. The
mismatch calibration is cooperated with 1/8 of the ADC
sampling clock, which is at least 80 times slower than the
DAC comparison clock. Therefore, the large size of switch is
not necessary and settling time restriction is satisfied for
different size of the switches for suitable operation margin in
addition to low power consumption.
IV. SIMULATION RESULTS
The proposed 10-bit split capacitive DAC based SAR
ADC is designed with a 130nm standard CMOS technology
and its performance metrics are shown in this section.
The offset voltage calibration for the comparator is
demonstrated and its results are shown in Fig. 6. The unit
calacitance of the metal-oxide-metal capacitors using PMOS
transistors is designed as 6fF. The sampling clock is devided
by 8 with T flip-flops, therefore the settling time for the
capacitors is 80ns in each switching operation. The
histograms display data from 200 samples of Monte Carlo
simulations with supported device mismatch parameters from
process design kit including 1-sigma difference in threhold
voltage. In Fig. 6 (a), the input offset voltages are spread from
-30mV to 30mV forming Gaussian distribution, which is
before the calibration. On the contrary, the offset voltages are
concentrated in the center of the histogram in Fig. 6 (b) after
the calibration is performed. The standard deviation of the
offset voltage distribution has been improved from 12.9mV to
6.0mV from the simulation results.
(b)
Fig. 6. Histogram of the comparator offset voltages from Monte Carlo
simulations (a) Without offset voltage calibration (b) After the proposed
calibration is performed
TABLE 1. SUMMARY OF PERFORMANCE
In the SAR ADC structure, the input signal capacitance
for smaple and hold amplifier (S/H) and total capacitance
used in the split DAC array are 1.05pF and 3.2pF,
respectively. Those two capacitor components are designed
with metal-insulator-metal (MIM) capacitors. The calibration
operation for the DAC mismatch compensation in the SAR
ADC is performed in the same manner. The basic structure of
the ADC is utilized in the calibration mode to optimize
hardware usage such as the pulse signals that are generated
from SAR logic, which are also used in the calibration mode
to choose capacitors to be compared.
4
Specifications
This work
Technology
130 nm CMOS
Supply Voltage
1.2 V
Resolultion
10 bit
Sampling Rate
100 MS/s
Input Range
1. 0 Vpp
DNL
-0.84 ~ 0.91 LSB
INL
-1.63 ~ 1.71 LSB
ENOB
9.23 bit
SNR
41.9 dB
SFDR
51.6 dB
THD
-49.9 dB
Total Power
1.1 mW
power and area efficient calibration algorithm. The paper
demonstrates that the mismatch error of the DAC can be
minimized and the SAR based ADC operates without any
extra power dissipation for the circuitry of self-calibration
during normal operation. The prototype circuit was designed
using 0.13μm standard CMOS technology, and the ADC
accomplished SNR of 41.9dB and power consumption of
1.1mW with 1.2V supply voltage and sampling rate of 100
MS/s.
1.00
0.75
DNL (LSB)
0.50
0.25
0.00
-0.25
-0.50
REFERENCES
-0.75
[1]
-1.00
2.00
[2]
1.50
INL (LSB)
1.00
0.50
[3]
0.00
-0.50
-1.00
[4]
-1.50
-2.00
0
64
128
192
256
320
384
448
512
576
640
704
768
832
896
960
[5]
OUTPUT CODE
[6]
Fig. 7. Static linearity of the proposed ADC versus output code.
To verify the operation of the ADC and the calibration
circuitry, a 50kHz input signal is applied and sampled at
100MS/s. From Fig. 7, the static performances of the ADC is
shown with -0.84~0.91 LSBs and -1.63~1.71 LSBs in DNL
and INL, respectively. A 10kHz input smapled at 100Ms/s for
the simulation. The simulated results show that the split
capacitor array does not suffer from linearity degradation after
the proposed mismatch calibration. In addition, the dynamic
performance of the ADC is also represented as 41.9dB of
SNR and 51.6dB of SFDR. The average power consumption
is 1.1mW at 100 MS/s including the output buffers and the
calibration circuits. The overall performance of the ADC is
summarized in TABLE 1.
[7]
[8]
[9]
[10]
[11]
V. CONCLUSION
[12]
In this work, we proposed a split-capacitive DAC based
10-bit SAR ADC operating at 100MS/s sampling rate. To
ensure the performance of the comparator in ADC with high
accuracy, voltage offset calibration logic is proposed.
Moreover, capacitor mismatch of DAC is compensated using
on-chip self-calibration technique, which includes a novel
[13]
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