Download FSD210 Fairchild Power Switch (FPS)

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FSD210
Fairchild Power Switch(FPS)
Features
Description
• Single Chip 700V SenseFET Power Switch
• Precision Fixed Operating Frequency (134kHz)
• Consumes under 0.1W at 265VAC at no load with an
Advanced Burst-Mode Operation
• Internal Start-up Switch and Soft Start
• UVLO with Hysteresis (6.7V/8.7V)
• Pulse by Pulse Current Limit
• Over Load Protection
• Internal Thermal Shutdown Function (Hysteresis)
• Secondary Side Regulation
• Auto-Restart Mode
• Frequency Modulation for EMI
The FSD210 is specially designed for an off-line SMPS with
minimal external components. The FSD210 is a monolithic
high voltage power switching regulator that combines an
LDMOS SenseFET with a voltage mode PWM control
block. The integrated PWM controller features: A fixed
oscillator with frequency modulation for reduced EMI.
Under voltage lock out. Leading edge blanking(LEB).
Optimized gate turn-on/turn-off driver. Thermal shut down
protection. Temperature compensated precision current
sources for loop compensation and fault protection circuitry.
Compared to a discrete MOSFET and controller or RCC
switching converter solution, an FSD210 can reduce total
component count, design size, weight and at the same time
increase efficiency, productivity, and system reliability. It is
a basic platform well suited for cost effective design of
flyback converters.
Applications
• Charger & Adaptor for Mobile Phone, PDA & MP3
• Auxiliary Power for PC, C-TV & Monitor
7-DIP
1.2.3.GND 4.Vfb 5.Vcc 7.Drain 8.Vstr
Internal Block Diagram
Vstr
8
Vcc < 6.7V
Vcc 5
Voltage
Ref.
UVLO
Internal
Bias
7 Drain
Vcc > 8.7V
Frequency
Modulation
5uA
Vck
OSC
SFET
DRIVER
250uA
S
Vfb 4
Q
R
BURST
V BURST
LEB
OLP
Reset
Iover
S
V SD
Q
Rsense
Vth
R
TSD
His 50
UVLO Reset
(Vcc<6.7V)
S/S
3mS
1, 2, 3
GND
Rev.1.0.0
©2003 Fairchild Semiconductor Corporation
FSD210
Absolute Maximum Ratings
(Ta=25°C unless otherwise specified)
Parameter
Symbol
Value
Unit
Maximum Vstr Pin Voltage
Vstr,max
700
V
Maximum Supply Voltage
VCC,MAX
20
V
VFB
−0.3 to VSD
V
TA
−25 to +85
°C
TSTG
−55 to +150
°C
Input Voltage Range
Operating Ambient Temperature
Storage Temperature Range
Pin Definitions
Pin Number
Pin Name
1, 2, 3
GND
Vfb
This pin is the inverting input of the PWM comparator. It operates normally
between 0.5V and 2.5V. It has a 0.25mA current source connected internally
and a capacitor and opto coupler connected externally. A feedback voltage
of 3V to 4V triggers overload protection (OLP). There is a time delay due to
the 5uA current source, which prevents false triggering under transient
conditions but still allows the protection mechanism to operate under true
overload conditions.
5
Vcc
This is the positive supply voltage input. During start up, current is supplied
to this pin from Pin 7 via an internal switch. When Vcc reaches the UVLO
upper threshold (8.7V), the internal switch start-up switch (Vstr) opens and
power is supplied from auxiliary transformer winding.
7
Drain
4
8
2
Pin Function Description
These pins are the control ground and the SenseFET Source.
Vstr
This pin is designed to directly drive the converter transformer and is
capable of switching a maximum of 700V.
This pin connects directly to the rectified AC line voltage source. At start up
the internal switch supplies internal bias and charges an external capacitor
that connects from the Vcc pin to ground. once this reaches 8.7V, the
internal current source is disabled.
FSD210
Electrical Characteristics
(Ta=25°C unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
700
-
-
V
-
-
100
µA
SENSEFET SECTION
Drain-Source Breakdown Voltage
Off-State Current
BVdss
Idss
VCC = 0V, ID = 100µA
VDS = 560V
Tj = 25°C ID = 25mA
-
28
32
Ω
Rise Time
TR
VDS = 325V, ID = 50mA
-
100
-
nS
Fall Time
TF
VDS = 325V, lD = 25mA
-
50
-
nS
126
134
142
-
±4
-
0.22
0.25
0.28
mA
On-State Resistence
RDS(ON)
CONTROL SECTION
Output Frequency
Feedback Source Current
Fosc
Tj = 25°C
Ifb
Vfb = 0V
kHz
Maximum Duty Cycle
Dmax
Vfb = 3.5V
60
64
68
%
Minimum Duty Cycle
Dmin
Vfb = 0V
0
0
0
%
8.0
8.7
9.4
V
6.0
6.7
7.4
V
-
3
-
mS
-
0.64
-
V
-
60
-
mV
0.26
0.30
0.34
A
125
145
-
°C
-
50
-
°C
3.5
4.0
4.5
V
UVLO Threshold Voltage
Internal Soft Start Time
Vstart
Vstop
After turn on
TS/S
BURST MODE SECTION
Burst Mode Voltage
VBURST
Hysteresis
PROTECTION SECTION
Drain to Source Peak Current Limit
Iover
Thermal Shutdown Temperature (Tj) (1)
TSD
Shutdown Feedback Voltage
VSD
Feedback Shutdown Delay Current
Idelay
Vfb = 4.0V
3
5
7
µA
IOP
Vcc = 11V
-
700
-
µA
Istart
Vcc = 0V
-
670
840
µA
Hysteresis
-
TOTAL DEVICE SECTION
Operating Supply Current
Start Up Current
Note:
1. These parameters, although guaranteed, are not 100% tested in production
3
FSD210
Typical Performance Characteristics
(These characteristic graphs are normalized at Ta=25°C)
O u tp u t Fre q u e n c y
O pe r a ti ng Cur re n t
1.2
0.8
1
0.75
0.8
0.7
0.6
0.65
0.4
0.6
0.2
0.55
0
0.5
-25
0
25
50
75
100
125
-25
0
25
Fo s c
50
75
100
125
Temp
O pe ra t in g Cu rr e nt
Figure 2. Operating Current vs. Temp
Figure 1. Freqency vs. Temp
Over Current
Feedback Current
1.20
1.2
1.00
1
0.80
0.8
0.60
0.6
0.40
0.4
0.20
0.2
0
0.00
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Feedback Current
Iover
Figure 4. Feedback Source Current vs. Temp
Figure 3. Peak Current Limit vs. Temp
Under Voltage Lockout (FSD210)
Shutdow n Feedback Voltage
1.2
1
0.8
0.6
0.4
0.2
0
-25
0
25
50
75
100
125
Shutdow n Feedback Voltage
Figure 5. ShutDown Feedback Voltage vs. Temp
4
Figure 6. Operating Current vs. Vcc Voltage
FSD210
Typical Performance Characteristics (Continued)
(These characteristic graphs are normalized at Ta=25°C)
Breakdow n Voltage
On_State_Resistance
900
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
850
800
750
700
-40
-25
0
25
50
75
100
Rds(on)
Figure 7. On State Resistance vs. Temp
125
650
-25
0
25
50
75
100
125
Breakdow n Voltage
Figure 8. Breakdown Voltage vs. Temp
5
FSD210
Typical Circuit
Snubber
Circuit
+
+
+
FSD210
Feedback
Circuit
PWM
+
6
Load
FSD210
Product Information
Basic system topology of FSD200/210 is the same as
the original FSDH565/0165 devices. The FSD210
devices require a bias winding, whereas the FSD200
devices do not. Other features of the two types of
devices are almost the same and are listed below.
With Bias Winding
Product Parameter
Without Bias Winding
FSD210
FSD211
FSD200
FSD201
700V
BCDMOS
700V
BCDMOS
700V
BCDMOS
700V
BCDMOS
32ohm
18ohm
32ohm
18ohm
0.3A
0.48A
0.3A
0.48A
Switching Frequency
134kHz
134kHz
134kHz
134kHz
Frequency Modulation
±4kHz
±4kHz
±4kHz
±4kHz
Operating Current (max)
770uA
770uA
770uA
770uA
o
o
o
o
145℃(Hys 50℃)
145℃(Hys 50℃)
145℃(Hys 50℃)
145℃(Hys 50℃)
7DIP/7SMD
7DIP/7SMD
7DIP/7SMD
7DIP/7SMD
4W
6W
4W
6W
Breakdown voltage (min)
On-state Resistance (max)
Current Limit (typ.Iover)
Burst function
Thermal Shutdown(typ.)
Package Type
Output
Power
85~265VAC
the KA431 reference pin voltage exceeds the internal
reference voltage of 2.5V, the optocoupler LED current
increase pulling down the feedback voltage and
reducing the duty cycle. This will happen when the
input voltage increases or the output load decreases.
3. Leading edge blanking (LEB) : When the MOSFET
turns on, there will usually be a large current spike
through the MOSFET. This is caused by primary side
capacitance and secondary side rectifier reverse
recovery. This could cause premature termination of
the switching pulse if it exceeded the over-current
threshold. Therefore, the FPS uses a leading edge
blanking (LEB) circuit. This circuit inhibits the pvercurrent comparator for a short time after the MOSFET
is turned on.
Figure 1. Line-up Table
Vcc
5uA
Functional Description
Vin,dc
Istr
Istr
Vstr
Vcc
Vcc<6.7V
on
Vstr
Vcc
Vcc>8.7V
off
HV
Reg.
7V
FSD21x
FSD20x
0.25mA
Gate
driver
FB
4
Cfb
1. Startup : At startup, an internal high voltage current
source supplies the internal bias and charges the
external Vcc capacitor as shown in Figure 1. In the
case of the FSD210, when Vcc reaches 8.7V the
device starts switching and the internal high voltage
current source is disabled. The device continues to
switch provided that Vcc does not drop below 6.7V.
After startup the bias is supplied from the auxiliary
transformer winding. In the case of FSD200, Vcc is
continuously supplied from the external high voltage
source and Vcc is regulated to 7V by an internal high
voltage regulator (HV Reg). The internal startup switch
is not disabled and an auxiliary winding is not required.
Figure 2.
Vin,dc
Vfb
Vo
OSC
Vref
R
KA431
VSD
OLP
Figure 3. PWM and feedback circuit
4. Protection Circuit : The FSD200/210 has 2 self
protection functions: over-load protection (OLP) and
thermal shutdown (TSD). Because these protection
circuits are fully integrated into the IC with no external
components, system reliability is improved without cost
increase. If either of these functions are triggered, the
FPS starts an auto-restart cycle. Once the fault
condition occurs, switching is terminated and the
MOSFET remains off. This cause Vcc to fall. When Vcc
reaches the UVLO stop voltage (6.7:FSD210,
6V:FSD200), the protection is reset and the internal
high voltage current source charges the Vcc capacitor.
When Vcc reaches the UVLO start voltage
(8.7V:FSD210, 7V:FSD200), the device attempts to
resume normal operation. If the fault condition is no
longer present start up will be successful. If it is still
present the cycle is repeated. This is shown in Figure 4.
Figure 2. Internal startup circuit
2. Feedback Control : The FSD200/210 are voltage
mode devices as shown in Figure 3. Usually, an optocoupler and KA431 type voltage reference are used to
implement the feedbacknetwork. The feedback voltage
is compared with an internally generated sawtooth
waveform. This directly controls the duty cycle. When
7
FSD210
Vfb
10V
OSC
5uA
250uA
4
R
Cfb
S
+
-
Vfb
GATE
DRIVER
Q
R
3V
OLP
4V
3V
OLP
FPS Switching Area
S
RESET
Vth 4V
TSD
His 50℃
R
/8
Q
FSD2xx
OLP, TSD
Protection Block
Idelay (5uA) charges Cfb
Figure 4. Protection block
4.1 Over Load Protection (OLP) : Overload is a load
current that exceeds a pre-set level due to an abnormal
situation. If this occurs, the protection circuit should be
triggered to protect the SMPS. It is possible that a short
term load transient can occur under normal operation. If
this occurs the system should not shut down. In order
to avoid false shut-downs, the over load protection
circuit is designed to trigger after a delay. Therefore the
device can discriminate between transient overloads
and true faul conditions. The device is pulse-by-pulse
current limited and therefore, for a given input voltage,
the maximum input power is limited. If the load tries to
draw more than this, the output voltage will drop below
its set value. This reduces the opto-coupler LED
current which in turn will reduce the photo-transistor
current. Therefore, the 250uA current source will
charge the feedback pin capacitor, Cfb, and the
feedback voltage, Vfb, will increase. The input to the
feedback comparator is clamped at around 3V.
Therefore, once Vfb reaches 3V, the device is
switching at maximum power. At this point the 250uA
current source is blocked and the 5uA source continues
to charge Cfb. Once Vfb reaches 4V, switching stops.
Therefore the shutdown delay time is set by the time
required to charge Cfb from 3V to 4V with 5uA as
shown in Fig. 5.
t
t1
t2
t3
t1<<t2, t3
t1 = -1/RCΧ ln( 1-v(t1)/R )
t2 = CΧ [v(t1+t2)-v(t1)]
Χ Idelay
v(t1)=3V
[v(t1+t2)-v(t1)]=1V, Idelay=5uA
Figure 5. Over load protection delay
4.2 Thermal Shutdown (TSD) : The SenseFET and
the control IC are assembled in one package. This
makes it easy for the control IC to detect the
temperature of the SenseFET. When the temperature
exceeds approximately 150°C, thermal shutdown is
activated. Thermal shutdown has a Hysteresis of 50°C
and so the temperature must drop to 100°C before the
device attempts to restart.
Temperature
TSD(℃)
FPS Switching Area
TSD - 50℃
TSD Hysteresis
t
5. Soft Start : FSD200/210 has an internal soft start
circuit that increases the feedback voltage together
with the MOSFET current slowly at start up. The soft
start time is 3msec in FSD200/210.
8
FSD210
I(A)
Vo
3mS
0.3A
Voset
Iover
0.25A
0.2A
VFB
0.6V
0.5V
t
Ids
FSD200/210
6. Burst operation : In order to minimize the power
dissipation in standby mode, the FSD200/210
implements burst mode.
Vds
time
OSC
S
5uA
250uA
Q
GATE
DRIVER
R
4
Figure 7. Burst mode operation
7. Frequency Modulation
on/off
Vfb
0.6V
/0.5V
130kHz
FSD2xx
Burst Operation Block
C
131kHz
132kHz
133kHz
134kHz
Figure 6. Circuit for burst operation
B
135kHz
136kHz
As the load decreases, the feedback voltage
decreases. The device automatically enters burst mode
when the feedback voltage drops below 0.5V. At this
point switching stops and the output voltages start to
drop. This causes the feedback voltage to rise. Once is
passes 0.6V switching starts again. The feedback
voltage falls and the process repeats. Burst mode
operation alternately enables and disables switching of
the power MOSFET to reduce the switching loss in the
standby mode.
137kHz
A
138kHz
2mS
Sawtooth
waveform
Vfb
138kHz
134kHz
130kHz
B
C
Vdrain
Ton
Idrain
A
9
FSD210
Typical application circuit
1. Cellular Phone Charger Example Circuit
C6 152M-Y, 250Vac
R6
R7
4.7M 1/4W 4.7M, 1/4W
L1 330uH
AC
Fuse
R1 4.7k
1W, 10R
D1
1N4007
D2
1N4007
AC
D3
1N4007
R3
47k
C1
4.7UF 400V
D4
1N4007
7
L3
C3
102k 1kV
2
Vo
4uH
SB260
R9
56R
C7
330uF 16V
R4
47k
C2
4.7uF 400V
0
D7
TX1
1
8
R8
510R
U3
H11A817B
(5.2V/0.65A)
C8
330uF 16V
R10
2.2k
.
C9 470nF
D5
UF4007
7
C10
4.7uF 50V
Drain
GND
4
Vfb
R5
1
Q1
KSP2222A
TH1 10k
3
R19
510R
C5
33uF 50V
R15 3R0
R16 3R0
4
For FSD21x
R12
2k
0
1N4148 39R
H11A817B
3
GND
GND
Vstr
1
U1
FSD210
D6
5
Vcc
2
8
U2
TL431
R17 3R0
0
C4
100nF
Reference
Part #
Quantity
Description
Requirement/Comment
D1,D2,D3,D4
1N4007
4
1A/1000V Junction Rectifier
DO41 Type
D5
UF4007
1
1A/1000V Ultra Fast Diode
DO41 Type
D6
1N4148
1
10mA/100V Junction Diode
D0-213 Type
D7
SB260
1
2A/60V Schottky Diode
D0-41 Type
Q1
KSP2222A
1
Ic=600mA, Vce=30V
TO-92 Type
U1
FSD210
(FSD200)
1
0.5A/700V
Iover=0.3A, Fairchildsemi
U2
KA431AZ
1
Vref=2.495V(Typ.)
TO-92 Type, LM431
U3
H11A817A
1
CTR 80~160%
-
1. Schematic diagram(Top view)
2mm
1
8
2
7
2mm
W4
W3
3
W2
6
W1
4
5
2. Core & Bobbin
CORE : EE1616
BOBBIN : EE1616(H)
3 . W in d in g s p e c if ic a t io n
No.
P in
in (S → F )
W1
1 →
2
W ir e
T u rn s
W in d iin
n g M e th o d
0 .1 6 Φ Χ 1
99 Ts
S O L E N O ID W IN D IN G
I N S U L A T IO N : P O L Y E S T E R T A P E t = 0 .0 2 5 m m / 1 0 m m , 2 T s
W2
4 → 3
0 .1 6 Φ Χ 1
18 Ts
C E N T E R S O L E N O ID
W IN D I N G
I N S U L A T IO N : P O L Y E S T E R T A P E t = 0 .0 2 5 m m / 1 0 m m , 2 T s
W3
1 → open
0 .1 6 Φ Χ 1
50 Ts
S O L E N O ID W IN D IN G
I N S U L A T IO N : P O L Y E S T E R T A P E t = 0 .0 2 5 m m / 1 0 m m , 3 T s
W4
8 → 7
0 .4 0 Φ Χ 1
9 Ts
S O L E N O ID W IN D IN G
I N S U L A T IO N : P O L Y E S T E R T A P E t = 0 .0 2 5 m m / 1 0 m m , 3 T s
4 . E le c t r ic a l c h a r a c t e r is ttic
ic
10
IT E M
T E R M IIN
NAL
S P E C I F IC A T I O N
IN D U C T A N C E
1 – 2
1 .6 m H
REM ARKS
1kH z, 1V
LEAKAG E L
1 – 2
50uH
3 ,4 ,7 , 8 s h o r t
100kH z, 1V
FSD210
2. Buck Convertor
Typical application circuit
Vin,dc
Vin,dc
C1
4.7uF/400V
Drain
GND
GND
Q1
Vfb
5
4
3
C3
47uF 25V
Vstr
GND
7
D2
Vcc
2
U1
FSD20x
ZD1
1N759A
R1 100
C2
10uF/50V
8
UF4004
R2
100
1
4
GND
GND
GND
Vfb
5
3
2
C1
4.7uF/400V
Vstr
1
8
U1
FSD21x
Drain
7
D2
Vcc
C5
4.7uF/50V
C2
10uF/50V
2N3904
R3
750
D1
L1
D1
GND
12V
R4
5.6k
R1 100
Q1
C3
47uF 25V
2N3904
R3
750
L1
GND
12V
1mH
UF4004
UF4004
R2
100
ZD1
1N759A
UF4004
C4
680uF 16V
C4
680uF 16V
GND
0
1mH
GND
0
Reference
Part #
Quantity
Description
Requirement/Comment
D1,D2
UF4007
2
1A/1000V Ultra Fast Diode
DO41 Type
Q1
2N3904
1
Ic=200mA, Vce=40V
TO-92 Type
ZD1
1N759A
1
12V 0.5W
DO-35 Type
U1
FSD210
(FSD200)
1
0.5A/700V
Iover=0.3A, Fairchild
11
FSD210
Package Dimensions
7-DIP
12
FSD210
Ordering Information
Product Number
Package
Rating
Topr (°C)
FSD210
7DIP
700V, 0.5A
−25°C to +85°C
13
FSD210
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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