Download Three Stage Low Noise Operational Amplifier Design for a 0.18 um

Three Stage Low Noise Operational Amplifier Design for a 0.18 um
CMOS Process
A. Soltani, M. Yaghmaie, B. Razeghi, R. Pourandoost, S. Izadpanah Tous1, and A. Golmakani
Department of Electrical Engineering, Sadjad Institute of Higher Education, Mashhad, Iran
E-mail: [email protected]
Abstract –– A new three stage low-noise, high-gain
operational amplifier (Op-Amp) is proposed in this paper.
Design strategies are discussed for minimizing noise and
increasing gain. Multipath nested Miller compensation used for
three stage operational amplifier. The circuit is designed in the
0.18µm CMOS technology. The HSPICE software was used for
simulation. The simulation results show that the amplifier has
a 128.5 dB open-loop DC gain and a unity gain-bandwidth of
794 MHz. Also input-referred noise of this circuit is 1.233
⁄√
at 1 MHz frequency.
the input stage allowing for designs with low input current
noise [2].
The first stage of proposed amplifier is shown in Fig. 2.
As you know the noise contributions of the Second and third
stages of the Op-Amp are negligible, because they are
divided by the gain of the previous stages when referred to
the main input. Also noise contribution of current source
is negligible.
Keywords –– Noise, three stage operational Amplifier,
Thermal noise, Flicker noise, Nested Miller compensation.
I. INTRODUCTION
The low noise operational amplifier is one of the most
important circuits used in analog design. In MOSFET
devices, there are two important noise sources, which are
flicker noise (below 1MHz) and thermal noise. Fig. 1 shows
device noise as a function of frequency. First, the noise
follows a 1⁄
dependence and is referred to as flicker
noise (v 0.8 1.2) or 1⁄ noise. Above the corner
frequency, , the noise normally is frequency independent
(thermal and shot noise). Above the second characteristic
frequency, , the noise increases sharply due to parasitic
capacitances coupling noise between different regions of the
device [1].
Fig. 2. First stage of the operational amplifier
⁄
⁄
With the assumption that
and
⁄
⁄
the total input-referred flicker noise
Power Spectral Density (PSD) and thermal noise PSD of the
circuit are described by:
2
·
2
1
·
1
·
(1)
and
8
Fig. 1. Power spectral density of flicker noise and thermal noise [1]
Operational amplifiers designed using bipolar
technology has achieved a wide bandwidth and superior
voltage noise performance. However, a bipolar Op-Amp
needs several milliamps of input current to bias the input
stage. Though CMOS amplifiers tend to be noisier than
bipolar amplifiers, only minimal bias current is needed for
8
·
(2)
Where
is capacitance per unit area of the gate oxide, W
and L are the channel width and length respectively,
is
NMOS flicker noise coefficient,
is PMOS flicker noise
coefficient, k is the Boltzmann constant and T is the absolute
temperature. The derived coefficient is equal 2/3 for longchannel transistors and may need to be replaced by a larger
value for submicron MOSFETs. It also varies to some extent
with the drain- source voltage [3]. The transconductance
can be found as presented in (3).
2
(3)
Where
is the carrier mobility for NMOS.
II. PARAMETER DETERMINATION TO ACHIEVE LOW NOISE
According to (1), (2) and (3), we find there are three
techniques that can be used to reduce the noise:
1. Determination of the input pair type for ,
2. Optimization of the bias current
of the input
pair
3. Optimization of the sizes and aspect ratios of the
MOSFETs
A. Determination of the input pair type for
,
The first approach to minimizing the 1⁄ noise uses
circuit topology and transistor selection. The transistor
selection is easy [4]. In this structure, NMOS should be
chosen for the input pair , for the following three reasons:
1. Selecting a NMOS transistor for the input pair
reduces thermal noise according to Equations (2)
and (3), since NMOS transistors have lager carrier
mobility than PMOS transistors.
2. The NMOS flicker noise coefficient
is smaller
than that of PMOS flicker noise coefficient
for
the process we use (In the 0.18
TSMC CMOS
process flicker noise coefficient for PMOS is
2.932E-23 and for NMOS is 3.564E-24), which is
helpful for achieving lower flicker noise according
to (1).
3. NMOS transistors have a higher transition
frequency
than PMOS transistors, which help to
achieve a higher bandwidth.
B. Bias Current
of the input pair
The bias current
, must be
maximized to decrease both types of noise. This is achieved
by selecting a large size and high aspect ratio for the input
pair.
C. Size and Aspect Ratio of MOSFET
⁄
To decrease the flicker noise, a large size for
is
chosen and the channel lengths , are designed larger than
that of the input pair
, based on (1). The aspect ratio
⁄
⁄
is maximized and made larger than
to
reduce the thermal noise according to (2) and (3). After
those choices, the input pair dominates the noise
contribution of both types. From (1), the change of the input
pair’s gate length can increase or decrease the flicker noise.
Fig. 3 shows the noise model for the structure in Fig. 2. The
noise contribution by each gate is referred back to their own
gate input, like the noise contribution of
, which is
represented by
connected in series to its gate.
Fig. 3. Noise Mosel
III. THREE STAGE OP-AMP
Fig. 4(a) shows the schematic of a three stage low noise,
high-gain operational amplifier based on the single stage
described above. When three or more voltage-gain stages
must be cascaded to achieve the desired gain, the op amp
will have three or more poles, and frequency compensation
becomes
complicated.
Multipath
Nested
Miller
compensation can be used with more than two gain stages.
This compensation scheme involves repeated, nested
application of Miller compensation [5]. Fig. 4(b) shows the
block diagram of nested Miller compensation applied to
three stages operational amplifier.
In this new structure, the parameters determining the DC
gain and noise floor are independent. Large bias currents are
used for the input pair to reduce thermal noise. The DC gain
of this amplifier is:
…
1
1
…
(4)
The gains of individual stages are:
|
|
|
|
|
|
(5)
1
1
(6)
(7)
The common source configuration is chosen for the output
stage of the operational amplifier. Such a stage can achieve
about 20-30 dB of gain
Vdd
M3
Vb1
M7
M4
M8
C2
M9
Vb2
M5
M6
R1 C1
Iref
Vout
Vin+
Mb1
M1
Mb2
M2
Vin-
R3
M2a
M1a
C3
Mb3
Mb4
(a)
(b)
Fig. 4. (a) New structure for a three stage low noise operational amplifier, (b) Block diagram for a three stage low noise operational amplifier with multipath
nested Miller compensation
IV. SIMULATION RESULTS
The proposed Op-amp is simulated in HSPICE with
BSIM3v3 model based on a standard 0.18 µm CMOS
process. The noise performance of the circuit shown in
Fig. 5 and the simulation of the ac performance of this
circuit is shown in Fig. 6. The simulation results shows a
considerable increase in unity-gain bandwidth to the value
of 794 MHz, the improved DC gain of 128.5 dB, and a
⁄√
phase margin of 59.5o. The noise level 1.233
is achieved at 1 MHz frequency.
The simulated performances for the different
compensation methods are expressed in Table I. Also,
detailed data obtained after simulating the proposed
Op-Amp is summarized in Table I. To evaluate this work
a figure of merit (FOM) can be defined as:
1000
(8)
Input-referred noise (V/√ Hz)
4
x 10
-7
3.5
3
2.5
2
1.5
1
0.5
0 0
10
X: 1e+006
Y: 1.233e-009
10
2
4
Parasitic Capacitances
Coupling Noise
6
10
10
Frequency (Hz)
Fig. 5. Noise performance
8
10
10
10
V. CONCLUSION
150
Gain (dB)
100
A three Stage low-noise, high-gain operational
amplifier in 0.18μm CMOS process is discussed. The
unity-gain bandwidth is maximized to 794MHz, and gain
is 128.5 dB. The amplifier can achieve low noise
performance and high gain simultaneously, something
that is often a tradeoff in normal operational amplifier
design.
X: 1
Y: 128.5
50
UGBW
0
X: 7.943e+008
Y: -0.01178
-50
0
10
2
10
4
6
10
10
Frequency (Hz)
8
REFERENCES
10
10
10
[1]
Phase (Degree)
200
Samuel Martin, Vance D. Archer III, David M. Boulin, Michel R.
Frei, Kwok K. Ng, and Ran-Hong Yan , “Device Noise in Silicon
RF Technologies,” Bell Labs Technical Journal, Summer 1997.
Zhineng Zhu, Raghu Tumati, Scott Collins, Rosemary Smith and
David E. Kotecki, “A Low-noise Low-offset Op Amp in 0.35μm
CMOS Process,” IEEE 2006.
B. Razavi, Design of Analog CMOS Integrated Circuits. New
York, NY: McGraw-Hill, 2001.
P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, New
York: Oxford University Press, 2002.
P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and
Design of Analog Integrated Circuits. Hoboken, NJ: John Wiley
and Sons, 2001.
Jirayuth Mahattanakul and Jamorn Chutichatuporn, “Design
Procedure for Two-Stage CMOS Op amp With Flexible NoisePower Balancing Scheme,” IEEE Transactions on Circuits and
Systems, vol. 52, NO. 8, August 2005.
Jui-Lin Lai, Ting-You Lin, Cheng-Fang Tai, Yi-Te Lai, and RongJian Chen, “Design a Low-Noise Operational Amplifier with
Constant-gm,” SICE Annual Conference 2010, August 2010.
[2]
100
[3]
[4]
0
[5]
-100
[6]
-200
0
10
X: 7.943e+008
Y: -120.5
2
10
4
6
10
10
Frequency (Hz)
8
10
10
10
[7]
Fig. 6. Simulated open loop gain and phase margin
TABLE I
PERFORMANCE SUMMARY
Performance
Supply Voltage (V)
Technology (
)
UGBW (MHz)
DC gain (dB)
Phase Margin (deg)
Input-referred noise
√
CMRR (dB)
Output swing -peak-to-peak (V)
FOM
[2]
[6]
[7]
3.3
0.35
380
110
10.6
1.297
(10MH)
N.A
N.A
12.66
2.5
N.A
6.15
85
65
44
(1MHz)
N.A
N.A
0.425
3.3
0.35
60
110
60
24.92
(1kH)
137.8
N.A
2
This work
3.3
0.18
794
128.5
59.5
1.233
(1MHz)
142
2.77
30.917