Download 4. Replace the BJT with one of its small-signal

JRE SCHOOL OF Engineering
PUT EXAMINATIONS MAY’15
Subject : ELECTRONIC CIRCUITS
Roll No. of Student
Date : 2nd MAY 2015
For IV SEM EC and AEI branches only
Subject Code
Max Marks
Max Duration
Time
NEC-402
100
3 HOURS
10:00 AM-01:00 PM
Note: Attempt all questions. Assume missing data if any.
Q.1. Attempt any four questions: (5X4=20 Marks)
a) Write down the essential properties of ideal OP-AMP and discuss about CMRR?
Soln.
CMRR : It stands for common mode rejection ratio.
Where AOL is differential gain and ACM is common mode gain.
b) Explain the closed loop frequency response of OP-AMP.
Soln.
dc gain is 10 (20 dB)
-10 case.
c) Find an expression for the output of the instrumentation amplifier.
Soln.
d) Explain the parameters affecting OP-AMP.
Soln.
1) Common-Mode Rejection Ratio: Common-mode rejection ratio, CMRR, is defined as the ratio
of the differential voltage amplification to the common-mode voltage amplification,
ADIF/ACOM. Ideally this ratio would be infinite with common mode voltages being totally
rejected.
2) Supply Voltage Rejection Ratio: Supply voltage rejection ratio, kSVR (power supply rejection
ratio, PSRR), is the ratio of power supply voltage change to output voltage change.
3) Slew Rate at Unity Gain Slew rate, SR, is the rate of change in the output voltage caused by
a step input. Its units are V/µs or V/ms.
4) Input Common Mode Voltage Range : The input common voltage is defined as the average
voltage at the inverting and non inverting input pins. If the common mode voltage gets too
high or too low, the inputs will shut down and proper operation ceases.
5) Differential Input Voltage Range Differential input voltage range is normally specified as an
absolute maximum. Exceeding the differential input voltage range can lead to breakdown
and part failure.
e)
Calculate the closed loop gain of OP-AMP in inverting configuration.
Soln.
Q.2. Attempt any two:
a)
(10*2 = 20Marks)
Find the midband gain AM and upper 3 db frequency fH of a CS Amplifier fed with the signal
source having an internal resistor Rsig= 100kΩ. The amplifier has RG= 4.7 MΩ, RD=RL= 15 kΩ,
gm= 1mA/V, r0= 150kΩ, Cgs= 1pF and Cgd= 0.4pF.
Soln.
b)
Draw the high frequency equivalent circuit model for the MOSFET and list all MOSFET internal
capacitances.
Soln.
 There are basically two types of internal capacitance in the MOSFET
A) Gate capacitance effect: the gate electrode forms a parallel-plate capacitor with gate oxide
in the middle
B) Junction capacitance effect: the source/body and drain/body are pn-junctions at reverse
bias
 The gate capacitive effect
MOSFET in triode region:
MOSFET in saturation region:
MOSFET in cutoff region:
C gs = C gd = Cov
C gb
WLCox
Overlap capacitance:
Cov
WLov Cox
 The Junction capacitance
Junction capacitance includes components from the bottom side and from the side
walls
The simplified expression are given by:
Sourse-body capacitance,
𝐶
𝐶𝑠𝑏𝑜
𝑠𝑏=
𝑉
√1+ 𝑠𝑏
𝑉𝑜
Where Csbo=value of Csb at zero body source bias
Vsb=magnitude of reverse bias voltage
Vo=junction built in voltage
Drain-body capacitance,
𝐶
𝐶𝑑𝑏𝑜
𝑑𝑏=
𝑉
√1+ 𝑑𝑏
𝑉𝑜
Where Cdbo=value of Cdb at zero body source bias
Vdb=magnitude of reverse bias voltage
Vo=junction built in voltage
c) Discuss all the regions of frequency response of an amplifier with a suitable diagram.
Soln.
Frequency response of amplifiers: It consists
of three different regions as follows:
1)
Midband region:
It is the frequency range of interest
for amplifiers
Large capacitors can be treated as
short circuit and small capacitors can
be treated as open circuit
Gain is constant and can be obtained
by small-signal analysis
Fig. Frequency response of an amplifier with all regions
2) Low-frequency band region:
In this region, g ain drops at frequencies lower than f L
Large capacitors can no longer be treated as short circuit
The gain roll-off is mainly due to coupling and by-pass capacitors
3) High-frequency band region:
In this region,g ain drops at frequencies higher than f H
Small capacitors can no longer treated as open circuit
The gain roll-off is mainly due to parasitic capacitances of the MOSFETs and BJTs.
Q.3. Attempt any two:
(10*2 = 20Marks)
a) Explain BJT as a switch and as an amplifier.
Soln. To operate the BJT as a switch, we utilize the cutoff and the saturation modes of operation. To
illustrate, consider the common-emitter circuit shown in Fig (1), as the input v in is varied.
1) CUT-OFF REGION ( SWITCH IS OPEN/OFF MODE )
Here the operating conditions of the transistor are zero input base current ( IB ), zero output
collector current ( IC ) and maximum collector voltage ( VCE ) which results in a large depletion layer
and no current flowing through the device. Therefore the transistor is switched “Fully-OFF”.
CUT-OFF characteristics:








The input and Base are grounded ( 0v )
Base-Emitter voltage VBE < 0.7v
Base-Emitter junction is reverse biased
Base-Collector junction is reverse biased
Transistor is “fully-OFF” ( Cut-off region )
No Collector current flows ( IC = 0 )
VOUT = VCE = VCC = ”1″
Transistor operates as an “open switch”
Fig 1(a) Switch is OPEN
Then we can define the “cut-off region” or “OFF mode” when using a bipolar transistor as a switch
as being, both junctions reverse biased, VB < 0.7v and IC = 0. For a PNP transistor, the Emitter
potential must be negative with respect to the Base.
2) SATURATION REGION ( SWITCH IS CLOSED )
Here the transistor will be biased so that the maximum amount of base current is applied, resulting
in maximum collector current resulting in the minimum collector emitter voltage drop which results
in the depletion layer being as small as possible and maximum current flowing through the
transistor. Therefore the transistor is switched “Fully-ON”.
Saturation Characteristics:









The input and Base are connected to VCC
Base-Emitter voltage VBE > 0.7v
Base-Emitter junction is forward biased
Base-Collector junction is forward biased
Transistor is “fully-ON” ( saturation region )
Max Collector current flows ( IC = Vcc/RL )
VCE = 0 ( ideal saturation )
VOUT = VCE = ”0″
Fig 1(b) Switch is CLOSED
Transistor operates as a “closed switch”
Then we can define the “saturation region” or “ON mode” when using a bipolar transistor as a
switch as being, both junctions forward biased, VB > 0.7v and IC = Maximum. For a PNP transistor,
the Emitter potential must be positive with respect to the Base.
The Common Emitter Amplifier Circuit
In the Common Emitter or grounded emitter configuration, the input signal is applied between the
base, while the output is taken from between the collector and the emitter as shown. In this type of
configuration, the current flowing out of the transistor must be equal to the currents flowing into
the transistor as the emitter current is given as Ie = Ic + Ib.As the load resistance ( RL ) is connected
in series with the collector, the current gain of the common emitter transistor configuration is quite
large as it is the ratio of Ic/Ib. A transistors current gain is given the Greek symbol of Beta, ( β ).As
the emitter current for a common emitter configuration is defined as Ie = Ic + Ib, the ratio of Ic/Ie is
called Alpha, given the Greek symbol of α. Note: that the value of Alpha will always be less than
unity. As we know that any small change in the base current ( Ib ), will result in a much larger
change in the collector current ( Ic ).Then, small changes in current flowing in the base will thus
control the current in the emitter-collector circuit. By combining the expressions for
both α and β, the mathematical relationship between these parameters and therefore the current
gain of the transistor can be given as:
Where: “Ic” is the current flowing into the collector terminal, “Ib” is the current flowing into the base
terminal and “Ie” is the current flowing out of the emitter terminal. This type of bipolar transistor
configuration has a large input impedance, current and power gain than that of the common base
configuration but its voltage gain is much lower. The common emitter configuration is an inverting
amplifier circuit. This means that the resulting output signal is 180o “out-of-phase” with the input
voltage signal.
b)
Write the steps through which small signal equivalent circuit model
can be used in the analysis of transistor amplifier.
Analyze the transistor amplifier given in Fig. 1 to determine
its voltage gain. Assume β=100.
Soln. 1. Determine the dc operating point of the BJT and in particular the dc collector current I C.
2. Calculate the values of the small-signal model parameters:
3. Eliminate the dc sources by replacing each dc voltage source with a short circuit and each dc
current source with an open circuit.
4. Replace the BJT with one of its small-signal equivalent circuit models. Although any one of the
models can be used, one might be more convenient than the others for the particular circuit being
analyzed.
5. Analyze the resulting circuit to determine the required quantities (e.g., voltage gain, input
resistance).
1. Determine the quiescent operating point. For this purpose we assume that vi=0.
The dc base current will be
The dc collector current will be
The dc voltage at the collector will be
Since VB at +0.7V is less than VC, it follows that in the
quiescent condition the transistor will be operating in
the active mode. The dc analysis is illustrated in Fig.3
(b).
2. Determine the small-signal model parameters:
Fig 3(a) Circuit 3(b) dc analysis
3. The dc supply voltage VCC has been replaced by a short circuit in the signal equivalent circuit
because the circuit terminal connected to VCC will always have a constant voltage. That is, the
signal voltage at this terminal will be zero. In other words, a circuit terminal connected to a
constant dc source can always be considered as a signal ground.
4. To carry out the small-signal analysis it is equally convenient to employ either of the two hybridπ equivalent circuit models as shown in Fig.3(c).
5. Analysis of the equivalent circuit in Fig.3(c) proceeds as follows:
The output voltage vo is given by
3(c) small-signal model
Thus the voltage gain will be
where the minus sign indicates a phase reversal.
c)
Derive the expression given below for the high frequency hybrid- π model of BJT:
𝒈𝒎
𝒇𝑻 =
𝟐𝝅(𝑪𝝅 + 𝑪𝝁 )
Soln.
Derivation of unity-gain bandwidth:
Consider the circuit shown in Fig. 4(b), in which the collector is shorted to the emitter. A node
equation at C provides the short-circuit collector current Ic as
A relationship between Vπ and Ib can be established by
multiplying Ib by the impedance seen between B′ and E:
Thus hfe can be obtained by
Fig.4(a) High frequency hybrid –π model
At the frequencies for which this model is
valid,
Thus we neglect the term
numerator and write
in the
Fig. 4(b)
Thus,
where 0 is the low-frequency value of . Thus hfe has a
single-pole (or STC) response with a 3-dB frequency at ω=ω,
where
Fig. 4( c)
Fig. 4(c) shows a Bode plot for
From the –6-dB/octave slope it follows that the frequency at
which
drops to unity, which is called the unity-gain bandwidth ωT, is given by
Thus,
Therefore,
Q.4. Attempt any two:
(10*2 = 20Marks)
a) Explain the small signal operation of MOS differential amplifier?
Soln.
Small-Signal Operation of the MOS Differential Pair: In this section we consider the detailed
operation of differential pair as a linear
amplifier.
Figure , shows the MOS differential amplifier
with input voltages. Here, VCM denotes a
common-mode dc voltage within the input
common mode range of the differential
amplifier. It is needed in order to set the dc
voltage of the MOSFET gates. Typically
VCM is at the middle value of the power
supply. Thus, for our case, where two
complementary supplies are utilized. VCM is
typically 0 V.
Differential gain:
id) is applied
in a complementary (or balanced) manner,
that is, vG1 is increased by vid/2 and vG2 is
decreased by vid/2.
-ended outputs (vo1 and vo2): output taken between one of the drains and ground.
od): output taken between the two drains.
-signal circuit analysis:
-ended gain:
b) Discuss the effect of resistance and transconductance mismatch in differential pair?
Soln.
Effect of resistance mismatch
-mode gain:
 Mismatch in RD causes a finite commonmode gain
-mode rejection ratio (CMRR):
 CMRR is defined as the ratio of differential-mode
gain and the common-mode gain
 A measure of the effectiveness of the differential pair in rejecting common-mode interference
 Is usually expressed in decibels
 Utilizes a bias current source with a high output resistance
 High degree of matching between the drain resistance
Effect of transconductance mismatch
Q1 andQ2
-mode gain:
c) Explain the Differential Amplifier with Active Load?
Soln.
Differential to single-ended conversion:
 Improved CMRR: suppress the influence of the common-mode
interference
 Higher voltage gain: gain is increased by a factor or 2
-ended output
 Certain applications require single-ended output
 A resistive load differential pair can simply provide the
differential to single-ended conversion
-loaded MOS differential pair
 Utilizes a current mirror (Q3 and Q4) as the active load
 Provides single-ended output for the differential pair
Basic circuit operation:
 Perfect matching case:
 Bias current is equally divided for Q1 and Q2
 The current of Q1 also flows through Q3
 Current of Q3 is mirrored to Q4
 All currents are identical (ID1 = ID2 =ID3 = ID4 = I/2)
 The currents of Q2 and Q4 balance out
 Zero output current to the following stage
 Quiescent output voltage = VDD  VSG3
 Mismatch in the devices:
 Nonzero net current at the output node
 The current flows into the output resistances of Q2 and Q4
 The output voltage deviates from VDD VSG3
 A difference current between Q1 and Q2
 The net difference current exists at the output.
Q.5. Attempt any two:
(10*2 = 20Marks)
a) Draw and explain all basic feedback topologies used for negative feedback amplifier. What
happens to input resistance and output resistance in case of voltage series feedback?
Soln.
THE FOUR BASIC FEEDBACK TOPOLOGIES
Based on the quantity to be amplified (voltage or current) and on the desired form of output
(voltage or current), amplifiers can be classified into four categories.
1) Voltage Amplifier (series-shunt feedback topology): Voltage amplifiers are intended to
amplify an input voltage signal and provide an output voltage signal. The voltage
amplifier is essentially a voltage-controlled voltage source. The input impedance is
required to be high, and the output impedance is required to be low. A suitable
feedback topology for the voltage amplifier is the voltage-mixing voltage-sampling
one shown in Fig.(a) . Because of the series connection at the input and the parallel or
shunt connection at the output, this feedback topology is also known as series-shunt
feedback.
2) Current Amplifier(shunt-series feedback topology):The input signal in a current
amplifier is essentially a current, and thus the signal source is most conveniently
represented by its Norton equivalent. The output quantity of interest is current; hence
the feedback network should sample the output current. The feedback signal should be in
current form so that it may be mixed in shunt with the source current. Thus the feedback
topology suitable for a current amplifier is the current-mixing current-sampling topology,
illustrated in Fig. (b).Because of the parallel (or shunt) connection at the input, and the
series connection at the output, this feedback topology is also known as shuntseries feedback. As will be shown, this topology not only stabilizes the current gain but also
results in a lower input resistance, and a higher output resistance, both desirable
properties for a current amplifier.
Fig. The four basic feedback topologies:
(a) voltage-mixing voltage-sampling (series–shunt) topology;
(b) current-mixing current-sampling (shunt–series) topology;
(c) voltage-mixing current-sampling (series–series) topology;
(d) current-mixing voltage- sampling (shunt–shunt) topology.
3) Transconductance Amplifier(series- series feedback topology): In transconductance
amplifiers the input signal is a voltage and the output signal is a current and the
appropriate feedback topology is the voltage-mixing current- sampling topology, illustrated
in Fig.(c). The presence of the series connection at both the input and the output gives this
feedback topology the alternative name series- series feedback.
4) Transresistance Amplifier(shunt-shunt feedback topology): In transresistance amplifiers,
the input signal is current and the output signal is voltage and the appropriate
feedback topology is of the current-mixing voltage-sampling type, as shown in Fig.(d),
The presence of the parallel (or shunt) connection at both the input and the output makes this
feedback topology also known as shunt-shunt feedback.
b) Explain the series-shunt feedback amplifier and calculate expressions for gain, input
resistance and output resistance.
Soln.
It consists of a unilateral open-loop amplifier (the A circuit) and an ideal voltage mixing voltagesampling feedback network (the β circuit). The A circuit has an input resistance Ri, a voltage gain A,
and an output resistance Ro. It is assumed that the source and load resistances have been included
inside the A circuit. Furthermore, note that the circuit does not load the A circuit; that is, connecting
the β circuit does not change the value of A (defined as A≡Vo ⁄ Vi).The circuit of Fig. 15(a) exactly
follows the ideal feedback model of Fig. 12.
Therefore the closed-loop voltage gain Af is given by
Fig 15
Note that A and β have reciprocal units. This in fact is
always the case, resulting in a dimensionless loop gain
A.The equivalent circuit model of the series-shunt feedback
amplifier is shown in Fig.15 (b). Here Rif and Rof denote the
input and output resistances with feedback. The relationship
between Rif and Ri can be established by considering the
circuit in Fig. 15(a):
Thus,
That is, in this case the negative feedback increases the input resistance by a factor equal to the
amount of feedback. Since the derivation above does not depend on the method of sampling (shunt or
series), it follows that the relationship between Rif and Ri is a function only of the method of mixing.
Note, however, that this result is not surprising and is physically intuitive: Since the feedback voltage
subtracts from Vs, the voltage that appears across Ri, that is, [ Vi=Vs⁄(1 +A )] becomes quite small.
Thus the input current Ii becomes correspondingly small and the
resistance seen by Vs, becomes large.
To find the output resistance, Rof of the feedback amplifier in
Fig. 15(a), we reduce Vo to zero and apply a test voltage Vt at
the output, as shown in Fig. 16.
From Fig 16 we can write
and since Vs= 0, it follows from Fig. 15(a) that
Fig. 16 Measuring the output resistance of the
feedback amplifier of Fig. 15(a): Rof :Vt/I.
That is, the negative feedback in this case reduces the output resistance by a factor equal to the
amount of feedback. With a little thought one can see that the derivation of Rof depends only on the
method of sampling. Again, this result is not surprising and is physically intuitive: Since the feedback
samples the output voltage Vo, it acts to stabilize the value of Vo ,that is, to reduce changes in the
value of Vo, including changes that might be brought about by changing the current drawn from the
amplifier14 output terminals. This, in effect, means that voltage-sampling feedback reduces the
output resistance.
c) Explain the working of Wein Bridge Oscillator. Derive an expression for the frequency of
Oscillation. Give its Merits and Demerits.
Soln.
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