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Proceedings of the 5th International Conference on Computing and Informatics, ICOCI 2015
11-12 August, 2015 Istanbul, Turkey. Universiti Utara Malaysia (http://www.uum.edu.my )
Paper No.
000
Design Of Low Voltage Bandgap Reference Circuit
Using Subthreshold MOSFET
Sushma S Sangolli,Rohini Hongal
1 Student
,B.V.B College of Engineering and Technology, Hubli, India, [email protected]
2Professor, B.V.B College of Engineering and Technology, Hubli, India. [email protected]
ABSTRACT. In this paper we present design of a low voltage bandgap reference (LVBGR) for supply voltage of 1.2V which can generate an output reference voltage of 0.364V. Traditional BJT based
bandgap reference circuits give very precise output reference but power and area consumed by these
BJT devices is larger so for low supply bandgap reference we chose MOSFETs operating in subthreshold region based reference circuits. LVBGR circuits with less sensitivity to supply voltage and temperature are used in both analog and digital circuits like high precise comparators used in data converter,
phase-locked loop, ring oscillator, memory systems, implantable biomedical product etc. In the proposed circuit subthreshold MOSFETs temperature characteristics are used to achieve temperature compensation of output voltage reference and it can work under very low supply voltage. A PMOS structure 2stage opamp which will be operating in subthreshold region is designed for the proposed LVBGR
circuit whose gain is 89.6dB and phase margin is 74 º. Hence a LVBGR is designed which generates
output voltage reference of 0.364V given with supply voltage of 1.2 V with 10 % variation and temperature coefficient of 240ppm/ º C is obtained for output reference voltage variation with respect to temperature over a range of 0 to 100 _C .The output reference voltage exhibits a variations of 230_ with
supply range of 1.08V to 1.32V at typical process corner. The proposed LVBGR circuit for 1.2V supply is designed in Mentor Graphics Pyxis tool using 130nm technology with EldoSpice simulator.
Overall current consumed by the circuit is 900nA and also the power consumed by the entire LVBGR
circuit is 0.9 _W and the PSRR of the LVBGR circuit is -70dB
Keywords: Bandgap reference circuit, PTAT, CTAT, temperature coefficient.
INTRODUCTION
Bandgap reference (BGR) is a circuit which provides a stable output voltage reference which
is temperature and supply insensitive. A precise and stable reference voltage is used in analog
to digital (A/D) and digital to analog (D/A) converters, voltage regulators, DRAM etc. As the
demands for smaller area, low power consumption and low sensitivity to the supply voltage
and temperature are increasing it becomes very essential that we design low voltage bandgap
reference circuit. Traditional bandgap reference which use bipolar transistors (BJT) temperature characteristic produce output voltage of 1.2 V which is very precise but the drawback of
this BGR is power consumed is very larger so for low supply and current we preferred CMOS
transistors which will be made to operate in subthreshold region so that its characters are
comparable to that of BJT because MOSFETs operating in subthreshold will operate at very
low power supply levels[1].In BGR circuits output reference which is less sensitive can be
obtained by adding (PTAT) proportional to absolute temperature voltage and complementary
to absolute temperature (CTAT) voltage where PTAT voltage has positive temperature coefficient and CTAT voltage has negative temperature coefficient .In traditional BGR circuits
PTAT voltage can be derived from the difference between the base to emitter voltages of the
two BJT devices and CTAT voltage can be derived from base to emitter voltage of single
diode connected BJT device. For low supply voltage i.e.1.2V and current in order to obtain a
stable reference voltage we use MOSFETs which are operate in subthreshold region because
these transistors operate near threshold voltage Vth so they minimize power supply voltage.
In the proposed circuit PTAT voltage is obtained by taking the difference between the gate to
Proceedings of the 5th International Conference on Computing and Informatics, ICOCI 2015
11-12 August, 2015 Istanbul, Turkey. Universiti Utara Malaysia (http://www.uum.edu.my )
Paper No.
000
source voltage of two MOSFETs which will be operating subthreshold and CTAT voltage is
taken from gate to source voltage of single MOSFET which is also operating subthreshold
region and finally by adding these two voltages we get output reference of 0.364V.
TRADITIONAL LVBGR CIRCUIT
Current-mode bandgap architecture was proposed so that it can works for low supply voltage
as shown in Figure1.In this architecture addition of currents is done so that it operates for low
supply voltages and advantage of this architecture is that it is can provide good PSRR. But the
drawback of this current mode architecture is that its output voltage is only temperature compensated current of output resistor so it’s more sensitive to power supply noise and resistor
mismatches as compared to traditional BGR. There are some more disadvantages in this current mode architecture i.e. these PNP transistors are process dependent. So in order to overcome these disadvantages we chose voltage mode architecture for low voltage bandgap reference circuit.
Figure 1. Traditional Current Mode BGR
Figure 2. Ireference generation circuit
PROPOSED LOW VOLTAGE BANDGAP REFERENCE CIRCUIT
The proposed low voltage bandgap reference (LVBGR) circuit uses voltage mode architecture
with subthreshold CMOS devices for low power. The LVBGR circuit has 2 main blocks:
Startup circuit
Startup circuit is used to ensure that all the device start working correctly in known states
during power up. The devices M7, M8 and M9 form a startup circuit. M7 and M8 form an
inverter which is a part of startup circuit as shown in figure 4. Initially when supply is off
there is no current in core circuit which makes top PMOS M4 and M5 turn on and input to
inverter M7 and M8 is logic one and inverter output is zero. The zero output of inverter which
turns on the PMOS M9 device whose output initiates the current in core circuit. Once the core
LVBGR turns ON startup will turn off and carrying very less current (12pA). The devices M9
will be in subthreshold region, M7 in triode and M8 in saturation region for the proper operation of startup. Also M14 is used to avoid startup problem for Iref generation in opamp.
Ireference Generation Circuit
Current Reference for 2stage opamp is obtained from LVBGR P-MOS current M5 and by
properly varying the aspect ratio of M15,M16 and M17 device we can obtain the required
reference current i.e. 50nA for 2stage opamp as shown in figure2 and Vbias for this current
reference circuit is taken from Startup circuit in order to overcome startup problems.
Proceedings of the 5th International Conference on Computing and Informatics, ICOCI 2015
11-12 August, 2015 Istanbul, Turkey. Universiti Utara Malaysia (http://www.uum.edu.my )
Paper No.
000
Operational amplifier
A two stage Op-amp operating in subthreshold region is chosen to meet the low supply voltage and gain requirement is as shown in figure 2 [2]. First stage of 2stage opamp has PMOS
differential pair with NMOS current mirrors and second stage has common-source amplifier.
The PMOS input pair of 2stage opamp operating in subthreshold is chosen in order to meet
the low supply voltage requirement and input common mode range. The devices M4 and M5
are input pair of 2 stage opamp, the inputs of opamp is driven by LVBGR circuit a and b
nodes as shown in figure 3. MOSFETS M2 to M6 and M1 and M8 are operate in subthreshold
region and are implemented as first and second amplifier stages. The Miller compensation
capacitor Cc provides frequency compensation required to achieve closed-loop stability of the
2stage opamp[2]. Thus entire 2stage opamp is designed to operate in subthreshold region i.e.
Vgs < Vth, where reference current carries current of 0.05nA which is generated from
LVBGR circuit as explained above and the entire opamp consumes current of 0.45 nA. Load
capacitance of opamp is taken from adding all capacitance associated with M4 and M5 devices of LVBGR circuit figure3. The approximated gain of 2stage opamp is given as
𝐴𝑉 = 𝐴𝑉1 𝐴𝑉2 = 𝑔𝑚5 (𝑟4,5 ||𝑟6,7 ). 𝑔𝑚8 (𝑟1 ||𝑟8 )
[1]
OPERATING PRINCIPLE
The CTAT voltage is obtained from gate to source voltage of MOSFET which is operating in
subthreshold region this given as [3]
W
𝑉𝑔𝑠 = 𝑉𝑡ℎ + 𝑛VT (lnC − ln ( ) + ( γ − 2)lnT)
[2]
L
Where and n represents MOS constants which are related to the process and C represents
Subthreshold MOSFET current. The first-order derivative of equation (1) is a negative value
[4] i.e. gate to source voltage of MOSFET which is operating in subthreshold region has
negative temperature coefficient. PTAT voltage is obtained by taking the difference between
the gate to source voltage of two MOSFETs which will be operating subthreshold with same
current flowing through them but with different aspect ratios
𝑊
(𝐿)
∆𝑉𝑔𝑠 = 𝑉𝑔𝑠1 − 𝑉𝑔𝑠2 = 𝑛𝑉𝑇 + ln 𝑊 2
[3]
(𝐿)
1
if (W/L)2>(W/L)1 then ΔVgs has positive temperature coefficient so with device sizes M2
four times of M1 we get PTAT voltage and from M3 device Vgs3 we get CTAT voltage. Transistors M4 and M5 has the same size to make sure that M1 and M2 have the same drain current. Since input impedance of 2stage opamp in subthreshold is very large, the current flowing through M2 equals to the current flowing through R1 and it is just the Vgs difference of
M1 andM2 divided by R1:
𝑊
∆𝑉𝑔𝑠 𝑛𝑉𝑇 ( 𝐿 )2
𝐼2 =
=
ln
𝑅1
𝑅1 (𝑊)
[4]
𝐿 1
M6 mirrors I2.The output voltage reference of LVBGR can written as:
𝑊
𝑛𝑉𝑇 𝑅2 ( 𝐿 )2
𝑉𝑜𝑢𝑡 = 𝑉𝑔𝑠3 + 𝐼3 𝑅2 = 𝑉𝑔𝑠3 +
ln 𝑊
[5]
𝑅1
(𝐿)
1
Proceedings of the 5th International Conference on Computing and Informatics, ICOCI 2015
11-12 August, 2015 Istanbul, Turkey. Universiti Utara Malaysia (http://www.uum.edu.my )
Figure3. stage opamp operating subthreshold
Paper No.
000
Figure 4. Proposed LVBGR
Hence the output voltage of LVBGR circuit is obtained by adding the gate to source voltage
of M3 device which has negative temperature coefficient and the voltage drop across R2 i.e.
the trimming resistors which gives positive temperature coefficient and the effects of positive
temperature coefficient and negative coefficient cancels by adding in order to get stable output voltage reference which is less sensitive to supply and temperature. Since the output voltage is taken across both resistor and MOSFET it is less prone to resistor mismatches. The
Proposed LVBGR is as shown in figure 4.
Trimming circuit
The trimming circuit is as shown in figure 4. which used to reduce the temperature coefficient
of output reference voltage of LBGR circuit for different supply and process corners. A 4 bit
series trimming circuit has resistors [10], whose values are chosen by calculating fine and
coarse variations of resistors at different supply and process corners. The fine resistor value
will be used for minute variations and coarse resistor value will be selected for large variation
of resistors for different supply variations and process corners. RMIN0, RMIN1 and RMIN2
are minimum resistor values obtained at SS, TT and FF corners in order to get required
LVBGR output voltage. Coarse resistors are selected by using the following equations
Rcoarse0 = RMIN1 -RMIN0 (6) and Rcoarse1 = RMIN2 -RMIN1 (7)
From the figure RMIN0=RMIN,Rcoarse0=R21,Rcoarse1=R22, R23 andR24 are fine resistors. These resistors are chosen by NMOS switches by their turn on and turn off which is
driven by digital circuit [10].
SIMULATION AND RESULTS
Simulations have been carried out using Mentor Graphics Pyxis tool with EldoSpice simulator in 130nm CMOS technology with supply of 1.2V with 10 % variations. The operational
amplifier used in the proposed LVBGR is 2 stage opamp operating in subthreshold, which
gives gain of 89.6db and phase margin of 74 º as shown in figure 5. Figure 6 Shows startup
behavior of LVBGR output with supply variation. The time required for LVBGR to produce a
stable output is 50µs (27 º C) and settles at 0.385V and the simulation is carried out using
transient analysis
Proceedings of the 5th International Conference on Computing and Informatics, ICOCI 2015
11-12 August, 2015 Istanbul, Turkey. Universiti Utara Malaysia (http://www.uum.edu.my )
Figure5. Gain and Phase of opamp
Paper No.
000
Figure 6. Start-up behavior of the BGR
Figure 7 shows the Vref variation with respect to temperature without trimming circuit and
figure 8 shows the Vref variation with respect to temperature with trimming circuit for all the
process and supply variation. The output of LVBGR with trimming circuit for supply voltage
of 1.2V for TT,SS and FF process corners has variation of output voltage of 230µV with
trimming circuit and without trimming circuit it was 132mV. With trimming circuit in
LVBGR the temperature coefficient (TC) for all the process corner and supply variation is
827ppm/ ºC. Hence the output voltage variation of LVBGR is reduced with the help of trimming circuit. Table1the performance metric of different architectures of low voltage bandgap
reference are shown in table 1 and table 2 shows the comparison of 2satge opamp vales with
practical using Pyxis tool and theoretical values using Maxima tool which are nearly same.
Figure. 7. Vref without trimming
Figure 8. Vref with trimming cicrcuit
CONCLUSION
A bandgap reference with low supply voltage is presented by using the characteristics of subthreshold MOSFET. It can work under supply voltage of 1.2V with 10% variation which
gives temperature coefficient of 240ppm/ °C. Compared with traditional current-mode BGR
for low voltage application, the proposed LVBGR circuit is less sensitive to resistor mismatch. Output variation is reduced from 132mV to 230µV with the help of trimming circuit.
Simulations are done using Mentor Graphics Pyxis tool with EldoSpice simulator in 130nm
CMOS technology and the entire circuit of LVBGR consumes 9nA of current and total power
Proceedings of the 5th International Conference on Computing and Informatics, ICOCI 2015
11-12 August, 2015 Istanbul, Turkey. Universiti Utara Malaysia (http://www.uum.edu.my )
Paper No.
000
consumption of 0.9W and this LVBGR circuit is used for low dropout reference (LDO) application which will be having a supply of 3.3V and must produce an output voltage of 1.8V.
Parameters
[5]
[6]
[7]
[8]
[9]
Proposed
Design
CMOS
0.35
0.18
0.18
0.45
0.13
0.13
Tech.(µm)
VDD (V)
0.87
1
0.9 to
2.5 V
0.8
0.6
1.2
VREF(V)
0.611
0.630
0.222
0.310
0.429
0.38
VREF
Variation
-
-
2
mV/V
Temp.
range(ºC)
-10
to 70
-20
to 70
20 to
120
TC(ppm//ºC)
<20
93.33
PSRR (db)
-
-
-
-
-
230µV/V
0 to
100°C
20 to
80
14.62
25.6
261
-
-70
-
TABLE I Comparison of LVBGR circuits
0 to 100
Parameters
Theoritical
Practical
Gain(dB)
90.73
89.7
UGB(KHz)
368.93
332
Pole1(Hz)
10.73
11.5
Pole2(MHz)
2.59
1.18
Zero1
8.8
10
TABLE II Comparison of 2stage opamp
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