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ECE 546
Lecture - 19
Equalization
Spring 2014
Jose E. Schutt-Aine
Electrical & Computer Engineering
University of Illinois
[email protected]
ECE 546 – Jose Schutt-Aine
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High-Speed Bus and Networks
 Memory Bus (Single-ended, Parallel)  Cable (Differential, Serial)
• DDR (4.266 Gbps)
• USB (4.266 Gbps)
• LPDDR4 (4.266 Gbps)
• HDMI (4.266 Gbps)
• GDDR (7 Gps)
• Firewire: Cat 5, Cat 5e, Cat 6
• XDR (differential, 4.8 Gbps)
 Storage (Differential, Serial)
• Wide IO2, HBM
• eMMC, UFS (6 Gbps)
• SAS, STATA (6 Gbps)
 Front Side Bus (Differential, Parallel)
• FiberChannel (10 – 20 Gbps)
• QuickPath Interconnect (6.4 Gbps)
• HyperTransport (6.4 Gbps)
 Computer IO (Differential, Parallel)
• PCIe (8 Gbps)
• InfiniBand (10 Gbps)
 Ethernet (Differential, Serial)
• XAUI (10 Gbps)
• XFI (10 Gbps)
• CEI-6GLR
• SONNET (10 Gbps)
• 10GBase-x, 100GBase (25 Gbps)
ECE 546 – Jose Schutt-Aine
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Why SERDES?
•
Traditional parallel communication not suitable
for inter-IC data transport in high-speed links.
–
•
Serial links are most cost-effective.
–
–
•
High design overhead due to cross-talk, data-skew.
Parallel links = extra pins  Higher packaging costs.
Speed v/s cost tradeoff with serial links.
Solution = SERDES!!!
–
–
Parallel communication still used in internal buses of
ICs thus a need for SerDes.
Mitigate cost while maintaining high-speeds with a
fast serial-parallel data conversion.
ECE 546 – Jose Schutt-Aine
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What is a SERDES?
•
SERDES = SERializer – DESerializer
–
–
–
–
Used to transmit high speed IO-data over a serial
link in I/O interfaces at speeds upwards of 2.5Gbps.
SerDes TX: transmit parallel data to receiver
overhigh speed serial-link.
SerDes RX: receive data from serial-link and deliver
parallel data to next-stage.
Advantage: Fast signaling, robust, high signal
integrity.
ECE 546 – Jose Schutt-Aine
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Serializer/Deserializer Blocks
•
Serializer:
•
Deserializer
ECE 546 – Jose Schutt-Aine
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Clock Types
• Synchronized System
 Global clock is used to update and determine bits
• Asynchronized System
 Only data is sent
 Clock is embedded in data
 Clock recovery unit (CRU) recovers clock at receiver
ECE 546 – Jose Schutt-Aine
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CDR Circuit Overview
• Monitor data signal transitions and select optimal
sampling phase for the data at midpoint between
edges.
• Extracts clock information from incoming data stream
and uses this regenerated clock to resample the data
waveform and recover the data.
• Non-linear circuit and key block to limit jitter, noise
within the SERDES circuit.
ECE 546 – Jose Schutt-Aine
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PLL Overview
Basic PLL Block Diagram:
• Closed-loop feedback system that synchronizes the
output CLK phase with that of the reference CLK.
• Tracks phase changes w/i the specified BW.
• Idea is that the PD (Phase Detector) will compare the
reference CLK phase with that generated by the VCO.
– Goal: Stabilize Δ𝜙𝑒𝑆𝑆 → 0 such that VCO output CLK and
reference CLK are locked at same frequency and phase.
– Tracks low-frequencies but rejects high-frequencies.
ECE 546 – Jose Schutt-Aine
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Why need PLLs?
• Reduces jitter.
• Reduces clock-skew in high-speed digital ckts.
• Instrumental in frequency synthesizers.
• Essential building block of CDRs.
ECE 546 – Jose Schutt-Aine
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Channel Equalization
ECE 546 – Jose Schutt-Aine
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Design Challenges for High-Speed Links
• Modern computer systems require Tb/s aggregate
off-chip signaling throughput
– Interconnect resources are limited
• Parallel buses with fast edge
rates must be used
– Package size and pin count cannot
keep up with speed
– Stringent power and BER
requirements to be met
– Channel attenuation increases
with the data rate
– High-performance signaling
requires high-cost channels
– Crosstalk-induced jitter
Available number and required speed of I/Os
(ITRS roadmap)
A typical controller-memory interface
ECE 546 – Jose Schutt-Aine
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Signal Integrity Impairments In High-Speed Buses
– SI issues limit system performance to
well below channel Shannon capacity
– Inter-Symbol Interference (ISI) is an
issue for long backplane buses
Insertion loss of a single DDR channel
– For short, low-cost parallel links,
dominant noise source is crosstalk
•
Far-end crosstalk (FEXT) induces
timing jitter (CIJ), impacts timing budget
FEXT increases with routing density
– Other SI impairments:
•
•
•
Simultaneous-switching (SSO) noise
Thermal noise
Jitter from PLL/DLL
ECE 546 – Jose Schutt-Aine
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Channel Impairments
• Modern computer systems require Tb/s aggregate
off-chip signaling throughput
– Interconnect resources are limited
• Parallel buses with fast edge
rates must be used
– Stringent power and BER
requirements to be met
– High-performance signaling
requires high-cost channels
Available number and required speed of I/Os
(ITRS roadmap)
• Difficult to design and costly
to manufacture
– One of main limiting factors:
crosstalk-induced jitter
A typical controller-memory interface
ECE 546 – Jose Schutt-Aine
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Equalization
Off-chip bandwidth scales at a much lower rate
than on-chip bandwidth. Primary objective is to
have low bit error rate (BER). Typical BER is 10-12.
ECE 546 – Jose Schutt-Aine
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Equalization
Frequency shaping filters that flatten the channel
response up to a certain frequency. Objective is to
improve BER and increase eye opening.
ECE 546 – Jose Schutt-Aine
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Pre-Emphasis and Equalization
• Pre-emphasis boosts the high-frequency contents of
the signal at the transmitter befre the signal is sent
through the channel.
• A two-tap finite impulse response (FIR) filter is an
example of pre-emphasis implementation.
• Pre-emphasis has high power requirements,
aggravates crosstalk and increase EMI.
• Pre-emphasis cannot improve SNR
• Data converters are required to implement preemphasis
ECE 546 – Jose Schutt-Aine
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Receiver Equalization
• The loss in the channel is suppressed by boosting
the high-frequency content of the signal.
• Often results in larger noise margins.
• Receivers can be implemented in discrete-time or
continuous time.
• Implementations include digital FIR equalizer,
analog FIR equalizer, continuous time equalizer.
ECE 546 – Jose Schutt-Aine
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Equalization Techniques
ECE 546 – Jose Schutt-Aine
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Continuous Time Passive Equalizer
1
z 
R1C1
P 
1
R2
DC gain 
R1  R2
R1 R2
 C1  C2 
R1  R2
R2
1  R1C1s
H (s) 
R1  R2 1  R1 R2 C  C s
 1 2
R1  R2
ECE 546 – Jose Schutt-Aine
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Channel-Equalization
Typical Channel Response w/o Equalization:
•
Equalization at TX and RX needed to counter the
effects of channel, properly decode signals.
•
TX: FFE (Feed-Forward Equalizer)
•
RX: DFE (Decision-Feedback Equalizer)
D. R. Stauffer et al., “High Speed Serdes Devices and Applications”, Springer 2008
ECE 546 – Jose Schutt-Aine
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FFE Circuit Architecture
Typical Channel Response at Receiver with FFE at TX:
Sample 3-tap FFE Architecture:
D. R. Stauffer et al., “High Speed Serdes Devices and Applications”, Springer 2008
ECE 546 – Jose Schutt-Aine
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FFE taps selected to
generate a filter with
the inverse transferfunction as that of
channel.
•
Trade-off b/w signal
amplitude at receiver
and jitter.
21
DFE Circuit Architecture
Typical Channel Response at Receiver with DFE at RX:
Sample 5-tap DFE Architecture:
•
•
D. R. Stauffer et al., “High Speed Serdes Devices and Applications”, Springer 2008
ECE 546 – Jose Schutt-Aine
DFE is needed in links
with a high-baud rate to
min. signal ampl. at
high freq. caused by
channel jitter.
Filter weights selected
dynamically
in
a
feedback loop to max.
eye opening.
22
FFE vs. DFE
• FFE
• DFE
•
Can mitigate the pre-cursor
channel response in low-BW
channels.
• Cannot equalize ISI arising
from pre-cursor channel
response.
•
Can compensate ISI arising
from transient TL loss over
wide time-spans.
• Can only compensate ISI
from a fixed time-span.
FFE + DFE
• Guarantees max. performance from the SerDes.
• Advantage:
–
DFE permits use of low-frequency de-emphasis at TX resulting in
a larger received signal envelope, smaller signal/crosstalk ratio.
–
System capable of employing continuous adaptive equalization of
its feedback taps to optimize performance.
ECE 546 – Jose Schutt-Aine
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Crosstalk – Uniform Channel
Channel consists of uniform transmission lines
Crosstalk can be described by multi-conductor TL theory
ECE 546 – Jose Schutt-Aine
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Crosstalk – Nonuniform Channel
Channel consists of connectors and traces
Cascade of S parameters
ECE 546 – Jose Schutt-Aine
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Crosstalk Mitigtion in Parallel Buses
V1s 
V 
2s
Vsn   
  
 
V ps 
V1n 
V 
2n
Vln   
  
 
V pn 
V1 f 
V 
2f
Vlf   
  
 
V pf 
ECE 546 – Jose Schutt-Aine
V1d 
V 
2d
Vdf   
  
 
V pd 
26
Crosstalk Mitigtion in Parallel Buses
Vmn = EVln
where Vln is the line voltage vector and Vmn is the modal voltage
vector at the near end. E is the voltage eigenvector matrix
associated with the multiconductor system. In general, E will be
complex and a function of frequency. The modal voltage vector
at the far end, Vmf will be given by:
Vmf = Xm Vmn
where Xm is the complex propagation matrix function given by
Vmf = Xm EVln
ECE 546 – Jose Schutt-Aine
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Crosstalk Mitigtion in Parallel Buses
in which ai +jbi is the complex propagation constant, associated
with the ith mode and l is the length of the lines. In terms of nearend signals this reads
Vmf = Xm EVln
The far-end line voltage vector, Vlf can be recovered using:
Vlf = E-1Vmf = E-1 Xm EVln
ECE 546 – Jose Schutt-Aine
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Crosstalk Mitigtion in Parallel Buses
Now, assume that the information signals are encoded with the
encoder T such that each of signals is mapped to one of the
two orthogonal modes, as follows:
Vln = T-1Vsn
At the far end the decoded voltage vector would be given by:
Vdf = QTVlf
where Q is an equalization matrix representing any equalizer
box that might be implemented at the output of the channel.
Using (5), we get
ECE 546 – Jose Schutt-Aine
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Crosstalk Mitigtion in Parallel Buses
Vdf = QTE-1 Xm ET-1Vsn
If we choose T=E we obtain
Vdf = QXm Vsn
e a1l  jb1l
V1d 

V 
 2d   Q 

  

 

V pd 
e a 2l  jb2l

 V1s 
 
 V2 s 
  


a p l  j b p l 
V
e
  ps 
ECE 546 – Jose Schutt-Aine
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Crosstalk Mitigtion in Parallel Buses
If in addition, we implement an equalizer with property
e a1l

a 2l
e
Q



this gives
 jb l
V1d  e 1
V  
 2d   
   
  
V pd  
e





a pl
e 

 j b 2l

  j vl
m1
e

 V1s 
  
 V2 s   
   

 
 j b pl 
e
 V ps  


ECE 546 – Jose Schutt-Aine
j
e
l
vm 2


 V 
  1s 
 V2 s 
  
 
l  V ps 
j
v 
e mp 
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Crosstalk Mitigtion in Parallel Buses
  j vl

m1
e
 j b1l

 V 
 V1s 
V1d  e
1s



l
 
V  
V 
 j b 2l
j
V
e
v
  2s 
  2s   
e m2
 2d   
  
   
   



 

  


 j b pl
l  V ps 
e
 V ps  
V pd  
j
vmp 

e


in which we used the relation bi = /vmi. This shows that if the proper
encoder, decoder and equalizer can be implemented, all signals can be
perfectly reconstructed, with no crosstalk, no attenuation and no
dispersion.
In the special case where the lines are lossless, ai = 0, Q= I (the
identity matrix) and no equalization is needed. Also E is real and does
not depend on frequency.
ECE 546 – Jose Schutt-Aine
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Mutual Inductance and Capacitance
 Crosstalk is the coupling of energy from one line to another via:
Mutual capacitance (electric field)
Mutual inductance (magnetic field)
– The circuit elements that represents this transfer of energy are the
following familiar equations:
VLm
dI
 Lm
dt
I Cm
dV
 Cm
dt
 The mutual inductance will induce current on the victim line opposite of
the driving current (Lenz’s Law)
 The mutual capacitance will pass current through the mutual capacitance
that flows in both directions on the victim line
 Near-end crosstalk is always positive
Currents from Lm and Cm always add and flow into the node
 For PCBs, far-end crosstalk is usually negative
Current due to Lm larger than current due to Cm
ECE 546 – Jose Schutt-Aine
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Crosstalk in Non-Homogenous Media
• Propagation modes have different velocities
– Time of flight depends on parameters
per unit length (self- and mutual L and C)
• Example: two-line single-ended signaling
• In microstrip PCB, typically:
– Lm/Ls>Cm/Cs → Odd mode is faster
• NRZ signal on aggressor line
induces both modes
– → Noise pulse on the victim line
– FEXT; translates into timing jitter
ECE 546 – Jose Schutt-Aine
Far-end voltages on the
quiet victim line
Courtesy of [1]
34
Crosstalk in Non-Homogenous Media
• Propagation modes have different velocities
– Time of flight depends on parameters
per unit length (self- and mutual L and C)
– FEXT noise pulses translate into timing jitter
• Previous proposed methods:
– Treat coupling as undesired, try removing its effects
– Harder to implement as coupling gets tighter
Example: two-line signaling
• Modal signaling takes advantage of coupling
–
–
–
–
Enables increased routing density
Special cases explored in previous work
Lossless, homogenous media
Uniform parallel lines
• This work explores the general case
– Lossy metal and dielectric (FR-4)
– Non-homogenous media (microstrip)
– Cascaded segments, vias/connectors
ECE 546 – Jose Schutt-Aine
Far-end voltages on the
quiet victim line
Courtesy of [1]
35
Crosstalk-Induced Noise
Different propagation modes have different propagation delays
and impedances:
TDeven  Leven Ceven  ( L11  L12 )(C11  C12 )
TDodd  Lodd Codd  ( L11  L12 )(C11  C12 )
Z even
Leven
L11  L12


Ceven
C11  C12
Z odd
Lodd
L11  L12


Codd
C11  C12
Weak coupling approximations:
kC=Cm/Cs«1, kL=Lm/Ls«1
• Model of inductive coupling coeff:
– where s is the pitch spacing between wire i and wire j,b a and b
 as
k

e
ij P/G plane
are constants depending on the wire width and
distance
ECE 546 – Jose Schutt-Aine
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Crosstalk-Induced Jitter (CIJ)
• Timing jitter is more dominant in chip-to-chip links than voltage
margin reduction
• Most of FEXT coupled energy introduced at transitions
– Affects zero crossing, causing jitter
– CIJ: independent of signal swing, insensitive to transition slope
• N-line bus: N distinct modes with different velocities
Courtesy of [5]
ECE 546 – Jose Schutt-Aine
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Crosstalk Sources, Timing Budget
• Crosstalk impacts both timing and voltage margins
• Limits routing density, especially for single-ended links
• Crosstalk sources:
– Coupling at vias, connectors, terminations
– Coupling in package (wirebonds, escape traces)
– Coupling in PCB traces (bus or adjacent layers for wide bus)
• Dominant in low-cost microstrip buses (e.g. DDR3)
A typical DDR timing budget: Rx jitter (orange), routing skew (green), Tx jitter (purple);
the remaining portion needs to cover all the timing uncertainties due to interconnects (blue) [4]
ECE 546 – Jose Schutt-Aine
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Crosstalk Mitigation Techniques
• Signal Coding
– Forbidden transition codes, Incremental, Differential or Pseudo-differential
signaling
• CIJ Compensation
– Detect mode combination, retime the signals
• FEXT Cancelation
– Estimate FEXT, inject the opposite signal to cancel
• Passive Equalization
– Reduce mode velocity mismatch
• None of the above are in practical use for off-chip links
– Hard to generalize to buses, power-hungry, too costly or complex to
implement for realistic channels
ECE 546 – Jose Schutt-Aine
39
Crosstalk Mitigation Approach
– Extend the applicability of crosstalk mitigation using modal signaling to
realistic tightly coupled low-cost interconnects.
– Examine the properties of building blocks of a modal signaling system;
propose practically realizable low-complexity models.
– Introduce a noise-aware system perspective of modal signaling; provide
design tradeoffs for a given level of performance.
– Establish a practical design flow of the modal transceiver system.
• The overall goal: enable crosstalk-free high-speed signaling on
dense, low-cost chip-to-chip interconnects
ECE 546 – Jose Schutt-Aine
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Mode-Aware Signaling for
Optimal FEXT Mitigation
• Common for all previous proposed methods:
– Treat coupling as undesired, try to remove its effects
– Harder to implement as coupling gets tighter (more crosstalk
to cancel)
• An alternative approach: Modal signaling
– Takes advantage of tight coupling using channel
diagonalization
 Enables increased routing density
– Special cases explored in previous works
– This work aims to solve the general case
ECE 546 – Jose Schutt-Aine
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Modal Signaling System – Ideal Lines
𝐕𝐦𝐟 = 𝐗𝐦𝐕𝐦𝐧
𝐕𝐦𝐟 = 𝐗𝐦𝐄𝐕𝐥𝐧
𝐕𝐥𝐧
1
b1
b2
Encoder
[T] ...
...
𝐕𝐝𝐟
𝐕𝐥𝐟
b'1
...
2
Decoder
b'2
[T-1] ...
...
N
...
Channel
bN
Transmitter
Decoded data
𝐕𝐦𝐧 = 𝐄𝐕𝐥𝐧
Source data
𝐕𝐬𝐧
b'N
Fully Matched
Termination Network
Receiver
𝐕𝐥𝐟 = 𝐄 −𝟏 𝐕𝐦𝐟 = 𝐄 −𝟏 𝐗 𝐦 𝐄𝐕𝐥𝐧
E: Eigenvector matrix
𝐕𝐝𝐟 = 𝐓𝐄 −𝟏 𝐗 𝐦 𝐄𝐓 −𝟏 𝐕𝐬𝐧
Xm: Propagation matrix (diagonal)
If we choose T=E-1 all signals are perfectly reconstructed
ECE 546 – Jose Schutt-Aine
42
Multiconductor Theory
•
•
•
Line bundle can be described by matrices per unit length
Z =R +jL, Y =G +jC
Telegrapher’s equations in frequency domain reveal coupling
d 2V
 (ZY)V
2
dz
d 2I
 (YZ)I
2
dz
•
Goal: introduce modal variables, diagonalizing the line equations
•
Issue: For lines with discontinuities, Z and Y change over length
•
Only interested in voltages/currents at ends of the channel
•
Start by describing the channel by its ABCD-parameters (one choice):
vS   A B  vR 
i   C D  i 
 R 
S  
ECE 546 – Jose Schutt-Aine
43
Modal Signaling System
•
For unidirectional signaling in forward direction:
– Map signals onto propagation modes at Tx; retrieve at Rx
– We can use T=WFv or T=WFi waveshapes for signaling
– Terminate the lines with Yterm=YC,F to eliminate reflections and mode conversion
– Optimal signaling from crosstalk mitigation standpoint
1
b1
b2
Encoder
[T] ...
...
bN
Transmitter
...
2
b'1
Decoder
b'2
[T-1] ...
...
N
...
Channel
Decoded data
Block diagram of the proposed direct implementation:
Source data
•
b'N
Fully Matched
Termination Network
Receiver
• Encoder, decoder – linear combinations of signals (channel eigenvectors)
• Matching network – needed to avoid reflections and mode conversion
ECE 546 – Jose Schutt-Aine
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Need for Termination Network
• In case of reflections at the far-end, signals would represent the superposition
of the incoming waves and the reflected ones;
• Modal redistribution - translates into crosstalk between modal channels;
• Therefore into crosstalk between decodes signal as well.
Frequency domain modal propagation model in matrix form (after Kuznetsov/Schutt-Aine
1992).
ECE 546 – Jose Schutt-Aine
45
Modal Signaling Concept:
Decoupling of Modal Channels
GMIMO (f)
x(t)
•
•
•
GSISO (f)
H(f)
E(f)
M(f)
H m(f)
n(t)
M -1(f)
+
Y MIMO (f)
D(f)
Y SISO (f)
x'(t)
– Block diagram of Tx – channel – Rx
– Hm(f) – diagonal modal propagation matrix: Hm(f)=diag(e-a(f)l-jb(f)l)
In frequency domain: X’= D (M-1 Hm M) E X
If we choose Tx encoder E=M-1 , Rx decoder D=M:
– After decoding: X’= M (M-1 Hm M) M-1 X = Hm X
Hm diagonal: crosstalk is completely eliminated
– Need to implement a termination network for channel H(f)
– Need to take into account noise present in the system
ECE 546 – Jose Schutt-Aine
46
Generalized Modal Decomposition
•
Traditional modal decomposition diagonalizes ZY=(R+jL)(G+jC) matrix
–
•
Issues: For lines with multiple segments, Z and Y change over length; Discontinuites
For signaling, only interested in Tx/Rx voltages/currents:
–
Use eigenvalue decomposition to diagonalize overall channel (S- or ABCD-parameters):
vS   A B  vR  WFv WBv  F
 i   C D   i   W

W
  R   Fi
Bi  
S 
•
vS , iS , vR , iR
1
 WFv WBv  vR 
B  WFi WBi   iR 
Submatrices describe forward- and backward-propagating mode waves
–
Fundamental modes are linearly independent in all cases of interest
•
Characteristic admittances:
•
All the submatrices complex, frequency dependent (for a lossy channel)
ECE 546 – Jose Schutt-Aine
47
•
•
Four Tightly Coupled Lines
Analyze waveshape properties of modal decomposition of channel parameter matrix (S,
ABCD, …)
Extract encoder/decoder/termination values at each frequency
All lines in sync
A: Uniform PCB traces
tan 2 ,  2r2
SOLDERMASK
h2
t
h1
t
TRACE
W
tan 1 ,  r1
S
SUBSTRATE
REFERENCE PLANE
B: Cascaded traces
with discontinuities
Arbitrary phase switching
Case B, 4 Gb/s NRZ tr=67ps, uncoded
ECE 546 – Jose Schutt-Aine
48
Propagation Constants of Modes
800
A: Uniform PCB traces
800
B: Cascaded traces
with discontinuities
700
700
600
600
500
X=10GHz
0=20GHz
400
400
300
300
Mode 1
Mode 2
Mode 3
Mode 4
200
Mode 1
Mode 2
Mode 3
Mode 4
200
100
0
0
b
b
500
100
1
2
3
4
a
5
6
7
0
0
8
Encoder/decoder/terminations can be
approximated by constant, real values
•
P. Milošević, J. Schutt-Ainé, and W. Beyene,
“Crosstalk mitigation of high-speed interconnects
with discontinuities using modal signaling," Conf. on
Electrical Performance of Electronic Packaging and
Systems, 2010
•
•
1
2
3
4
a
5
6
7
8
9
Propagation constants exhibit resonances resonant eigenvectors
Interaction of modes between cascaded
segments
Some modes more resonant than others
due to coupling mechanisms
ECE 546 – Jose Schutt-Aine
49
Performance Comparison of the
Termination Networks
•
Statistical eye diagrams
of 4 Gb/s NRZ, tr=67ps,
all modes switching
–
•
Only 2 out of 4 channels
shown
Mode 3
Mode 1
Mode 4
Mode 2
Note: channel for which
uncoded eye was closed
Resistive Terminations
•
•
•
Vertical eye opening
increase of 39%
Reduction in peak-topeak jitter of 27%
“Ground mode” #4
suffers from ISI of
internal reflections
Mode 3
Mode 4
Low-Order Modeled
ECE 546 – Jose Schutt-Aine
50
Physical Realization (1)
DSP-based
Encoding
DSP encoder directly calculates final transition values
–
– DAC/line drivers need to generate proper transition waveforms
– Most suited to Tx with DSP core (and SerDes) already in place
N
Uncoded
bits
b1
b2
1:S
Deserializer
N
Digital
Encoder
[T]
NxM
M
1
Instance #1
NxM
S:1
Serializer
M
#2
...
...
...
2
...
...
NxM
...
M
N
#S
bN
Multimode
Receiver
2
...
N
...
DAC/driver 1
N
Channel
Transition Time Select
Mux
...
...
Transmitter
Ibias,1
Ibias,2
Fully Matched
Resistive Termination
Network
Ibias,2N
ECE 546 – Jose Schutt-Aine
51
Physical Realization (2) Analog Frontend
• Channel: 4-line 4-inch pkg-PCB-pkg bus
• 3 bitstreams x 4 Gb/s = 12 Gb/s
• Forwarded clock uses ground mode
– Half rate (2Gb/s) to alleviate
limited bandwidth
– This allows simple resistive terminations
P. Milošević and J. Schutt-Ainé, “Design of a
12Gb/s Transceiver for High-Density Links with
Discontinuities using Modal Signaling” Conf. on
Electrical Performance of Electronic Packaging and
Systems, 2011
Rx
Tx
ECE 546 – Jose Schutt-Aine
52
Modal Signaling – Circuit-level Results
• Process used: IBM 90 nm low-power digital RF, 1.2 V supply
• Encoder/Driver (w/o pre-drivers): 11.0 mW (0.92 mW/Gb/s), 6500m2
• Decoder overhead (w/o slicers): 14.5 mW (1.20 mW/Gb/s), 4300m2
2ns
200mV
Unit pulse responses of signals over equivalent
modal channels
Normalized eye diagrams of decoded modal signals
ECE 546 – Jose Schutt-Aine
53
Performance Improvements
and Comparison
• Max Jp-p reduced to 15.6% of UI
• 2.5x increase in aggregate bandwidth
– Compared to the conventional NRZ signaling on similar channel
• Other mitigation techniques fail due to tight coupling
–
–
–
–
Tx FEXT cancelation: peak-power limit closes vertical eye
Rx FEXT cancelation: FEXT pulses hard to mimic, subtract
Passive velocity matching: issues with cascaded segments
CIJ retiming implementation: too complicated for N>2
ECE 546 – Jose Schutt-Aine
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Synthesis Flow
• Procedure for the adaptive
optimal crosstalk cancellation
method
On-chip
measurement
Interconnect
Characteristics
• Starts from realistic system
measurements (or models)
mode 1
1
0
-1
0
0.5
1
1.5
2
0.01
0
-0.01
0
0.5
1
1.5
10
• End result – tuned encoder,
decoder and termination
network for optimal signaling
performance
0.5
1
1.5
2
0.01
0
-0.01
0
0.5
1
1.5
10
0
-1
0
x 10
mode 3
x 10
1
0.5
1
1.5
2
0.02
0
-0.02
0
0.5
1
1.5
10
-1
0
0.5
1
Frequency
1.5
2
10
x 10
2
10
x 10
0
-0.5
2
10
x 10
mode 4
• Decomposition – performed by
the system or offline
x 10
Modal
Decomposition
mode 2
0
-1
0
2
10
x 10
1
0.02
0
-0.02
0
0.5
1
Frequency
1.5
2
10
x 10
Determine
encoder &
decoder
Extraction of
optimal term.
r
Generate
ki
Low-order
 s p
i 1
ECE 546 – Jose Schutt-Aine
Tune
network
i
55
Encoder Layout
Milosevic, P., Schutt-Ainé, J.E., "Transceiver Design for High-Density Links With Discontinuities
Using Modal Signaling", IEEE Trans. Comp. Packaging. Manuf. Tech., vol. 3, pp. 10-20, January
2013.
ECE 546 – Jose Schutt-Aine
56
Decoder Layout
Milosevic, P., Schutt-Ainé, J.E., "Transceiver Design for High-Density Links With
Discontinuities Using Modal Signaling", IEEE Trans. Comp. Packaging. Manuf. Tech., vol.
3, pp. 10-20, January 2013.
ECE 546 – Jose Schutt-Aine
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Serial Link
- Passive channel consists of linear elements (TL, package)
- Analog channel includes TX driver and RX termination network
- End-to-end channel includes everything
ECE 546 – Jose Schutt-Aine
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High-Speed Serial Channels
High speed Serial channels are pushing the current
limits of simulation. Models/Simulator need to handle
current challenges
– Need to accurately handle very high data rates
– Simulate large number of bits to achieve low BER
– Non-linear blocks with time variant Systems
– TX/RX equalization and vendor specific device settings
– Coding schemes
– All types of jitter: (random, deterministic, etc.)
– Crosstalk, loss, dispersion, attenuation, etc…
– Clock Data Recovery circuits
– TX and RX may come from different vendors
ECE 546 – Jose Schutt-Aine
59
Serial Channel Characterization
• Millions of bits of behavior are needed to adequately characterize serial
links long simulation times
• SERDES transmitters / receivers can be modeled as a combination of analog
& algorithmic elements
• Serial channels can be characterized using S Parameter data and/or other
passive interconnect models
ECE 546 – Jose Schutt-Aine
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Simulation Methods
Analysis Method
Advantages
Drawbacks
IBIS
Fast
Not accurate
Device Level
Accurate
Nonlinear
Very slow
IP liability
Fast convolution
Very fast
Handles EQ
Include bit patterns
Not Silicon Specific
Assumes LTI
Statistical
Very Fast
Handles EQ
Not silicon specific
No bit patterns
Assumes LTI
IBIS-AMI
Fast
Handles Vendor EQ
Includes Bit Patterns
Not limited to LTI
Implementations vary
ECE 546 – Jose Schutt-Aine
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Industry Standard: IBIS
•
•
•
•
•
•
•
Provided as binary code
Fast, efficient execution
Protects vendor IP
Extensible modeling capability
Allows models to be developed in multiple languages
Standardized execution interface
Standardized control (.AMI) file
IBIS homepage: http://www.eigroup.org/ibis/
ECE 546 – Jose Schutt-Aine
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AMI
• AMI stands for Algorithmic Modeling Interface
faster signal processing algorithms
 intellectual property protection
used in convolution transient engines
designed to be used with fixed time step data
introduced in IBIS 5.0 specs
in these specs the library is specified inside
the IBIS wrapper
IBIS stands for “I/O Buffer Information Specification”; high-level buffer
specification for circuit modeling
http://eda.org/pub/ibis/ver5.0/ver5_0.txt
ECE 546 – Jose Schutt-Aine
63
AMI Challenges
• AMI models are compiled DLLs and text files
– No graphical representation
• Package model standard not finalized
– User needs to manually add IC/package parasitics to
channel model
• Each IC vendor has different parameter set
– No standards set
– Each vendor must document their models
• No standard way to sweep parameters
– Need to create multiple .AMI files
– EDA tools need to parse arbitrary .AMI parameters
ECE 546 – Jose Schutt-Aine
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