Download Abstract *The aim of this paper is to study the

Capacitance parameters evolution of Silicon MOSFET Devices exposed to
Electrical and Thermal Stress
Chafic Salame1 and Michel Aillerie2
1
2
Faculty of Sciences II, Lebanese University, Jdeidet El Mten, Lebanon
LMOPS-SUPELEC, Universite de Lorraine, 2 rue Eduard Belin, 57070 Metz cedex, France
Abstract —The aim of this paper is to study the behavior of the gate-source capacitance of MOSFET devices
under extreme temperature and high electric field conditions.
C-V curves are measured as a function of temperature and high electric field stress. A theoretical approach is given
and an experimental procedure is set up. Several sets of measurements are performed at different temperatures and
for different periods of stress.
The degradation after stress causes the shift of the C-V curves. When positive defects dominate, the curve shifts to
lower voltages and when negative defects dominate, the curve shifts to higher voltages. The degradation is not
sensed at very high temperature because defects migrate away from the interface and their effect is thereby reduced.
Since the gate-source capacitance is very essential in the microelectronics industry, the information presented in this
paper is of major importance. These measurements show how the capacitance of MOSFET devices behaves in
extreme conditions. The variations allow engineers to predict the degradation mode of their devices.
Keywords—MOSFET, capacitance, high field stress, charged defects.
I. INTRODUCTION
The operation of field effect transistors is mainly ruled by the behavior of their integrated MOS
capacitance. C-V characteristic curves are very suitable to provide information about several
MOS features such as the flat band voltage, the threshold voltage, oxide thickness, and trap
densities [1]. Interface quality, oxide thickness [2], and trap densities are key factors ruling the
performance of MOSFET devices, in particular the gate-source capacitance. The biggest threats
that MOS structures have to face are operations under high temperatures [3] such as in hybrid
vehicles or in the aerospace industry, and operations in hostile environments where hot carrier
generation alters their long term reliability by inducing charged defects within the oxide layer, or
at the oxide semiconductor interface [4].
In this paper, the gate-source C-V curves of a MOSFET device are studied as a function of
temperature and high field stress. Theoretical predictions are presented, then experimental
verification is presented to show the dependence of the C-V curve with charged defects when the
device is stressed at different temperatures.
EXPERIMENTAL SET-UP
C-V curves are measured on an IRL3215 n-channel commercial MOSFET device. This type of
devices is manufactured in a standard commercial process and is widely used in the industry
mainly because of its low cost TO220 plastic package. The IRL3215 have a breakdown voltage
of 150 V and an on-resistance of 0.16 Ω. We know that the oxide thickness range of this device
is greater than 30 nm, which rules out the possibility of direct tunneling of carriers through the
oxide layer even when high fields are applied on the gate contact. For each set of measurements,
the temperature is fixed and the oxide is stressed by a high field, resulting from the application of
a high voltage on the gate contact. Drain and source are grounded during the stressing phase.
Each time the stress is stopped, a gate-source low frequency C-V curve is measured. This
procedure is repeated as a function of temperature. Each time a complete set of measurements is
performed at a different temperature going from 0 0C up to 200 0C. During the stress and the
measuring phases, the temperature is always fixed at the desired temperature. An HP4192A
impedance analyzer is used and the frequency is set to 400 Hz, the gate voltage goes from -8V to
+8V by a step of 0.2V. As the use of commercial devices implies small differences even between
components having the same part number, many samples were tested and the repetitiveness of
the results was good.
RESULTS AND DISCUSSION
The gate-source capacitance is in fact a combination of the oxide capacity C0, and the
semiconductor capacity Cs. The total capacity is given by:
When a negative voltage is applied on the gate contact of an n-channel MOSFET device, a high
accumulation of holes occurs on the p-type substrate and Cs becomes very large, consequently
the total capacity is reduced to C0. As the gate voltage is increased, holes accumulation weakens
and a depletion layer starts to form. Cs is then given by:
Where εS is the semiconductor permittivity, and W is the depletion layer width.
W increases along with the gate voltage so Cgs decreases until we reach inversion where the
semiconductor surface starts to accumulate electrons instead of holes, then further increasing of
the gate voltage does note enlarge W but make better inversion instead [5]. At high inversion Cs
is too large and Cgs is once again equal to C0. In order to have the inversion phenomena, the gate
voltage should first reach enough positive value to induce a certain charge per unit area Qs and to
create the necessary surface potential φS. The threshold voltage is then given by:
Which is an idealistic case. The real case, particularly in MOS devices, is different because of
the presence of charged defects. If we replace all positive defects by an equivalent charge Qpos
and all negative charges by an equivalent charge Qneg, The resultant real threshold voltage will
be expressed by:
Where φ mS is the metal semiconductor work function potential difference.
Equation (4) predicts the behavior of the threshold voltage along with defects density. An
accumulation of positive defects should shift Vth towards lower voltages, and negative defects
should shift Vth towards higher voltages.
We begin by investigating the behavior of Cgs when the temperature is increased from 0 0C to
200 0C without stress.
Figure 1 shows that the capacity in high accumulation and in high inversion is unchangeable
with temperature, which means that the oxide electrical capacity C0 is stable within the studied
range of temperature. Only CS is varying mainly because of the reduction of W at elevated
temperature. In fact W is a function of the intrinsic carrier concentration ni that rises with
temperature leading to the decrease of W as predicted by equation (5):
Na is the acceptor concentration. Consequently, Cgs increases with temperature because of the
additional charges generated by thermal effects but no shifts are observed.
Fig. 1 Gate-source capacitance as a function of temperature.
When the device is stressed at a certain temperature, the main observed effect is the shift of the
Cgs curve towards larger or lower voltages. For example, the curves shown in figure 2 were
measured at 0 0C after stressing the oxide at the same temperature. The larger shift is obtained
after 10 minutes of stress and then the curve slowly restores its initial position especially for the
right side of the dip that gives the threshold voltage. The left side of the dip, which indicates the
flat band voltage, is not changed a lot after 10 minutes of stress. These changes, in particular Vth
modification, indicate a large accumulation of positive charges in the oxide near the interface.
According to equation (4) Vth is decreased by a positive charge, which is consistent with the
experimental results of figure 2 where the oxide accumulates a large amount of positive defects
in the early period of stress. Then Vth starts to increase again because of the creation of interface
states that are generally negatively charged, thus shielding a part of the oxide charges. But even
for the largest period of stress the concentration of interface does not equal the density of oxide
charges. In fact when the oxide is facing a high electric field during the stress period, electrons
are therefore driven from the substrate and forced to travel through the oxide layer by FowlerNordheim tunnelling. The passage of energetic electrons in the oxide creates defects by breaking
bonds, and by extracting electrons from the oxide molecules through impact ionization [6] which
will consequently leave the oxide with a net positive charge. More extended periods of stress
induce negatively charged interfacial defects that will be located at the Si/SiO2 interface region
and will compensate a part of the oxide positive charge.
Fig. 2 Gate-source capacitance as a function of stress at 0 0C.
Figure 3 shows the experimental results obtained at room temperature. In addition to the
threshold voltage shift, the flat band voltage is also decreasing with stress mainly because of
interface states creation. At 50 0C, figure 4 shows that not only the threshold voltage is shifting
towards lower values but also the bottom of the dip is increasing and the minimal capacitance
becomes bigger. The latter phenomenon is due to the increase of the semiconductor capacitance
CS, thus revealing a change of the material properties as predicted by equation (2). Assuming that
the width of the depletion layer W does not decrease with stress, the only reason that explains the
increase of CS is a change of εS because of the degradation of the semiconductor surface largely
caused by interface states.
Fig. 3 Gate-source capacitance as a function of stress at 25 0C.
Fig. 4 Gate-source capacitance as a function of stress at 50 0C.
Figure 5 shows that at 100 0C the CS increase is larger and the surface degradation is more
severe. The curves are distorted and do not reveal any further changes with extended periods of
stress. The biggest degradation occurs after only the first few minutes of stress and then the
progression becomes slower.
Fig. 5 Gate-source capacitance as a function of stress at 1000C.
When we proceed to the 150 0C temperature, figure 6 shows that the same distortion exists as in
the case of 100 0C, but the difference is that at 150 0C the minimal capacitance tends to slowly
restore its original position as the stress period is extended. We believe that this behaviour is not
related to the stress itself or to the increase of the number of defects; it is more linked to the
temperature that is high enough to consider a reorganization of the silicon lattice and a migration
of defects far from the interface region. This temperature effect is more pronounced at 200 0C
where the figure 7 shows that after several periods of stress the changes are very slight.
Even the curve shift due to positive charges is insignificant because the oxide defects are gaining
extra mobility by thermal effect and are drawn away from the interface.
Interface states are probably rearranged at high temperature so the variation of minimal CS is
minor.
We should note that if defects are delocalized by high temperature, this does not mean that they
do not exist anymore but their position is far from the interface and their effect on the C-V curve
is not sensed. Increasing the temperature over 200 0C is not recommended for this type of
devices and does not bring any new information, especially that the plastic package is unstable at
very high temperature.
Fig 6 Gate-source capacitance as a function of stress at 150 0C
Fig 7 Gate-source capacitance as a function of stress at 200 0C.
IV. CONCLUSION
Gate-source C-V curves, were studied as a function of temperature and high field stress. High
temperature leads to a better accumulation of charges, thus increasing the semiconductor
capacity. As predicted by theoretical studies, the C-V curve shifts towards lower voltages when
positive defects are created with small periods of stress, and shifts towards higher voltages when
negatively charged defects are created with extended stress. These shifts express the variation of
the threshold voltage and the flat band voltage with the presence of charged defects. However,
curve shifting is not the only sign of degradation because we have also found that at high
temperature the silicon properties could be changed by excessive degradation of its surface. At
very high temperature, defects are migrating away from the interface by thermal effects, mainly
because of higher mobility, so apparently we do not observe many signs of degradation.
Nevertheless defects always exist; only their effect on the C-V curve is not sensed due to their
location away from the interface.
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