Download Source Follower - CS

Source Follower
General Description
Vdd
Vin
Vout
I=5uA
Vss
Figure 1N-MOS configuration of fource follower
Applications
Achieving output voltage which follow the input signal with a constant offset. The output
achieved is from a transistor – not the original signal. Therefore, it can withstand higher
loads than the original signal.
Analysis
The following are the equations for channel current in saturation (for a MOSFET):
2

I Sd  VSG  VT
2
VSG  VSD  VGD  Vout  Vin
Therefore:
 2i

Vout  Vin  
 | VT |
 


Equation 1

The expression in brackets is actually the offset from input to output voltage of the source
follower. The current i, which is the current from the current source, is the only variable
that can be used to control the offset.
Applying equation 1 to our model we get the following:
The offset of the output is 0.85V(as shown on the graph).
The right hand side of equation 1 yields the following:
The current from the current source = 190uA, β=Kp*W/L = 2.635440E-05*305
 2  190  10 6

So the term in the bracket equals to 

0
.
63025
  0.85 and equation 1 is
8  10 3


satisfied.
Linear Region


Upper limit: Vin, HIGH determines Vout, HIGH . If too high, it can harm the saturation
of out current source transistor.
Lower limit: Vin, LOW determines Vout, LOW . If the latter is too low, then the source
following transistor will not be in saturation.
The linear region can be manipulated by changing  of this transistor, and by that
changing the offset voltage (in brackets of Equation 1).
Current Source
There is a trade of between two factors that are effected by the size of the current from
the current source:
On one hand, we wish the current source to supply enough current to achieve high slewrate, and therefore we wish it has high  .
On the other hand, higher current increases the offset of the source-followed transistor,
and therefore increases Vout . This increase shortens the saturation margin of the currentsource VSD  VSG  VT , at which point the current is no longer constant, and the device
becomes non-linear.
Pad I/O With ESD
Applications

The pad protects the chip from potentially harmful input voltages (too high or to low).
Analysis
The symbol scheme of the pad is
Dpdiff
BONDING
SIGNAL
SIGNAL
PAD
Dndiff
Vb denotes the built in voltage of the diodes, and is the voltage needed to make the diode
forward biased.
When the signal input is of a voltage higher than 5+Vb, the upper diode become forward
biased becomes a donnductor. The excess charge is discharged through it and does not
effect the the chip itself, which will see only 5V.
A too low input will be discharged through the lower diode, in a similar manner.
PadInOut
OutPad

The out pad takes a signal from the internal circuit, and outputs it to the
“world” through a buffer.
Parameter
Freq
Test Condition
Min
0
Max
30
Unit
Mhz
VOH
Input : ramp
Vdd 5v
Input : ramp
Vdd 5v
2.6
5
V
0
2.4
V
VOL
Switching characteristics:
Comments
High 80% of
original with 10pF
load
For lower Vdd, min
is (Vdd/2+0.1)
For lower Vdd,max
is (Vdd/2-0.1)

Parameter
tHL
tLH
The time it takes the output buffer to change from one state to the other state.
Setup Time (ns)
0.8
0.7
InPad


The pad takes a signal from the “world”, and inputs it into the circuit. It
provides both a buffer (so that the signal’s strength will not depend on its
source), and an ESD unit to protect the circuit from static electric charges.
DataIn is the inputed data, DataInB is the inverse of the input data..
Parameter
Freq
Test Condition
Min
0
Max
100 (both
inputs)
300 (only
dataIn)
Unit
Mhz
Comments
High 80% of
original
VOH
Input : ramp
Vdd 5v
Input : ramp
Vdd 5v
2.6
5
V
0
2.4
V
For lower Vdd, min
is (Vdd/2+0.1)
For lower Vdd,max
is (Vdd/2-0.1)
VOL
switching Characteristics for 200 Mhz square pulse with 0.1 ns rising time

The time it takes the input buffer to change from one state to the other.
Parameter
tLH
tHL
Output Node
DataIn
DataInB
DataIn
DataInB
Setup Time (ns)
0.7
1
0.8
0.45
Comments
Bibliography
1. The Art of Electronic, second edition, Horowitz & Hill, pg. 133
2. CMOS Analog Circuit Design, Allen & Holberg. Pg. 221