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ECE 5745 Complex Digital ASIC Design
Topic 2: CMOS Devices
Christopher Batten
School of Electrical and Computer Engineering
Cornell University
http://www.csl.cornell.edu/courses/ece5950
Simple Transistor RC Model
Simple Wire RC Model
MOSFET Fabrication
Part 1: ASIC Design Overview
P P
M M
Topic 4
Full-Custom
Design
Methodology
Topic 6
Closing
the
Gap
Topic 1
Hardware
Description
Languages
Topic 5
Automated
Design
Methodologies
Topic 8
Testing and Verification
Topic 3
CMOS Circuits
Topic 2
CMOS Devices
ECE 5745
T02: CMOS Devices
Topic 7
Clocking, Power Distribution,
Packaging, and I/O
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Simple Transistor RC Model
Simple Wire RC Model
MOSFET Fabrication
Agenda
Simple Transistor RC Model
Simple Wire RC Model
CMOS Fabrication
ECE 5745
T02: CMOS Devices
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• Simple Transistor RC Model •
Simple Wire RC Model
MOSFET Fabrication
Fundamental Building Block: MOSFET Transistor
IBM Power 7
1.2 Billion
Transistors
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• Simple Transistor RC Model •
Simple Wire RC Model
MOSFET Fabrication
“Metal”-Oxide-Semiconductor Structure
Polysilicon Gate
Silicon Dioxide Insulator
p-Type Silicon Body
(doped to create mobile majority carriers,
positively charged holes)
Accumulation: Battery puts negative charge on gate,
attracts positively-charged majority carriers in p-type silicon body
Adapted from [Weste’11]
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T02: CMOS Devices
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• Simple Transistor RC Model •
Simple Wire RC Model
MOSFET Fabrication
“Metal”-Oxide-Semiconductor Structure
Polysilicon Gate
Silicon Dioxide Insulator
p-Type Silicon Body
(doped to create mobile majority carriers,
positively charged holes)
Depletion Region
Depletion: Battery puts positive charge on gate,
pushes positively-charged carriers away from surface, uncovers some
negatively-charged dopant atoms in substrate
Adapted from [Weste’11]
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T02: CMOS Devices
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• Simple Transistor RC Model •
Simple Wire RC Model
MOSFET Fabrication
“Metal”-Oxide-Semiconductor Structure
Polysilicon Gate
Silicon Dioxide Insulator
p-Type Silicon Body
(doped to create mobile majority carriers,
positively charged holes)
Depletion Region
Inversion Region
Inversion: Battery puts more positive charge on gate, instead of pushing holes
even further away, draws free electrons to surface. Where did electrons come
from? No electron donors in p-type silicon; electron/hole pairs always being
generated by thermal excitation – electrons caught by efield in depletion region
Adapted from [Weste’11]
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T02: CMOS Devices
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• Simple Transistor RC Model •
Simple Wire RC Model
MOSFET Fabrication
NMOS Transistor
Cutoff: Vgs = 0V, Vds can be 0V or Vdd
No Channel, Ids = 0
Linear: Vgs = Vdd, Vds = 0V
Channel Formed, Ids increases with Vds
0 < Vds < Vgs - Vt
Vds > Vgs - Vt
Linear: Vgs = Vdd, Vds = Vdd
Channel Formed, Ids increases with Vds
Saturation: Channel Pinched Off,
Ids independent of Vds
Adapted from [Weste’11]
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• Simple Transistor RC Model •
Simple Wire RC Model
MOSFET Fabrication
Simple NMOS Circuit
Vds
d
Vgs
0 < VVds
ds <> V
Vgs
gs -- Vt
Vt
s
Cutoff:
Channel,
Ids = 0Off,
Saturation:
Linear:No
Channel
Pinched
Formed
IIds
increases with
of V
Vds
ds independent
ds
Vt
Vgs =Vdd
Id
ECE 5745
log
Id
Id
Vds
Vgs
Vds =Vdd
Vgs
V
Vds
Vgs
T02: CMOS Devices
time
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• Simple Transistor RC Model •
Simple Wire RC Model
MOSFET Fabrication
Key Qualitative Characteristics of MOSFET Transistors
I Vt sets when transistor turns
Reff
on, impacts leakage current
Cd
I Id / µ ⇥ (W /L)
Key qualitative
characteristics
of
I
µ
>
µ
=)
RN ,eff < RP ,eff
n
p
Cg
MOSFET transistorsCd I Cg / (W ⇥ L)
I Cd / W
Width
I " W = # Reff = V" Id = "
out
Cd , Cg
Vin
Cg
I " L = " Reff C=d # Id = " Cg
Reff
Length
T02: CMOS
Devices
ECE 5745
• Threshold
voltage sets when transistor
turns
on – also impacts leakage
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Simple Transistor RC Model
• Simple Wire RC Model •
MOSFET Fabrication
Agenda
Simple Transistor RC Model
Simple Wire RC Model
CMOS Fabrication
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T02: CMOS Devices
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Simple Transistor RC Model
• Simple Wire RC Model •
Wire
Resistance
Wire Resistance
Height
Length
Width
resistance
bulk aluminum
bulk copper
bulk silver
MOSFET Fabrication
length resistivity
height width
2.8x10-8
1.7x10-8
1.6x10-8
Thickness fixed in given manufacturing process
Resistances quoted as /square
TSMC 0.18 m 6 Aluminum metal layers
M1-5 0.08 /square (0.5 m x 1mm wire = 160
M6
0.03 /square (0.5 m x 1mm wire = 60
Rsq = resistivity / height
ECE 5745
6.371 – Fall 2002
-m
-m
-m
)
)
resistance = Rsq ⇥ ( length / width )
Adapted from [Terman’02]
T02: CMOS Devices
10/2/02
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L09 – Wires
Simple Transistor RC Model
• Simple Wire RC Model •
MOSFET Fabrication
Wire Capacitance
Capacitance
Wire
H2
2
W2
12
H1
1
D1
D12
W1 S1
DD1
Capacitance depends on geometry of surrounding wires and
relative permittivity, r,of dielectric
– silicon dioxide, SiO2
– silicon flouride, SiOF
– SiLKTM polymer,
ECE 5745
r = 3.9
r = 3.1
r = 2.6
Adapted from [Terman’02]
Can have different materials between wires and between
layers, and also different
materials
on higher layers
T02: CMOS
Devices
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Distributed RC wire model gives accurate
results
but
is computationally
expensive
Key
Qualitative
Characteristics of Wires
Simple Transistor RC Model
Rdriver
R1
• Simple Wire RC Model •
MOSFET Fabrication
R2
RN
Cload a
Lumped model can provide
C1
C2
CN
quick reasonable approximation
Because
both wire
Use
Penfield-Rubenstein
equation to find delay
resistance and wire
capacitance increase with
Delay
length, wire delay
grows
quadratically with length
Rdriver
N
j i
i
j 1
Rw
Rj
C
Cload
i
Cw/2
Cw/2
How does the delay scale with longer wires?
Cw
– Wire delay increases quadratically
Delay R driver
R driver
2
– Edge rate also degrades quadratically
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T02: CMOS Devices
Rw
Cw
2
C lo
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6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 31
Simple Transistor RC Model
Simple Wire RC Model
• MOSFET Fabrication •
Agenda
Simple Transistor RC Model
Simple Wire RC Model
CMOS Fabrication
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T02: CMOS Devices
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Simple Transistor RC Model
Simple Wire RC Model
• MOSFET Fabrication •
Mask Set for NMOS Transistor (circa 1986)
Mask set for an n-Fet (circa 1986)
Vg = 0V
Vd = 1V
I ≈ nA
n+
dielectric
Vs = 0V
n+
p-
Top-down view:
Masks
#1: n+ diffusion
#2: poly (gate)
#3: diff contact
#4: metal
Layers to do
p-Fet not shown.
Modern
processes have 6
to 10 metal
layers (or more)
(in 1986: 2).
38
Lecture 02, Introduction 1
ECE 5745
CS250, UC Berkeley Fall ‘11
Adapted from [Asanovic’11]
T02: CMOS Devices
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Simple Transistor RC Model
Simple Wire RC Model
• MOSFET Fabrication •
Design Rules for Masks (circa 1986)
“Design rules” for masks, 1986 ...
Poly
overhang.
So that if
masks are
misaligned,
channel
doesn’t
short out.
Minimum gate length.
So that the source and
drain depletion regions
do not meet!
#1: n+ diffusion
#2: poly (gate)
length
#3: diff contact
#4: metal
CS250,
UC Berkeley
Fall ‘11[Asanovic’11]
Adapted
from
Lecture 02, Introduction 1
ECE 5745
Metal rules:
Contact
separation from
channel, one
fixed contact
size, overlap rules
with metal, etc ...
T02: CMOS Devices
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Simple Transistor RC Model
Simple Wire RC Model
• MOSFET Fabrication •
Start With an Un-Doped Wafer
Start with an un-doped wafer ...
UV hardens exposed resist. A wafer
wash leaves only hard resist.
Steps
oxide
#1: dope wafer p#2: grow gate
oxide
#3: deposit undoped
polysilicon
p-
#4: spin on
photoresist
#5: place positive
poly mask and
expose with UV.
Lecture 02, Introduction 1
ECE 5745
CS250, UC Berkeley Fall ‘11
Adapted from [Asanovic’11]
T02: CMOS Devices
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Simple Transistor RC Model
Simple Wire RC Model
• MOSFET Fabrication •
Wet Etch to Remove Unmasked Regions
Wet etch to remove unmasked ...
HF acid etches through poly and oxide,
but not hardened resist.
oxide
p-
oxide
After etch and
resist removal
pLecture 02, Introduction 1
ECE 5745
CS250, UC Berkeley Fall ‘11
Adapted from [Asanovic’11]
T02: CMOS Devices
17 / 33
Simple Transistor RC Model
Simple Wire RC Model
• MOSFET Fabrication •
Use Diffusion Mask to Implant N-Type
Use diffusion mask to implant n-type
accelerated donor atoms
n+
oxide
n+
p-
Notice how donor
atoms are blocked
by gate and do not
enter channel.
Thus, the channel
is “self-aligned”,
precise mask
alignment is not
needed!
Lecture 02, Introduction 1
ECE 5745
CS250, UC Berkeley Fall ‘11
Adapted from [Asanovic’11]
T02: CMOS Devices
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Simple Transistor RC Model
Simple Wire RC Model
• MOSFET Fabrication •
Metallization Completes Device
Metallization completes device
n+
n+
n+
oxide
n+
p-
oxide
p-
oxide
n+
Mask and etch
to make contact
holes
n+
Put a layer of
metal on chip.
Be sure to fill in
the holes!
pLecture 02, Introduction 1
ECE 5745
Grow a thick
oxide on top
of the wafer.
CS250, UC Berkeley Fall ‘11
Adapted from [Asanovic’11]
T02: CMOS Devices
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Simple Transistor RC Model
Simple Wire RC Model
• MOSFET Fabrication •
Final NMOS Transistor
Final product ...
Vd
Vs
n+
oxide
n+
p-
Top-down view:
“The planar
process”
Jean Hoerni,
Fairchild
Semiconductor
1958
46
Lecture 02, Introduction 1
ECE 5745
CS250, UC Berkeley Fall ‘11
Adapted from [Asanovic’11]
T02: CMOS Devices
20 / 33
Simple Transistor RC Model
Simple Wire RC Model
• MOSFET Fabrication •
PMOS Transistor is Dual of NMOS Transistor
p-Fet: Change polarity of everything
Vwell = Vs = 1V
I ≈ μA
p+
Vg = 0V
dielectric
n-well
p-
Vs
Vd = 0V
p+
New “n-well” mask
Vg
Isd
Vd
“Mobility” of
holes is slower
than electrons.
p-Fets drive less
current than nFets, all else being
equal
Lecture 02, Introduction 1
Adapted from [Asanovic’11]
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Simple Transistor RC Model
Simple Wire RC Model
• MOSFET Fabrication •
Single- and Triple-Well Processes
Adapted from [Weste’11]
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Simple Transistor RC Model
Simple Wire RC Model
• MOSFET Fabrication •
Local Interconnect
IBM 6-Transistor SRAM Cell
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T02: CMOS Devices
Adapted from [Weste’11]
23 / 33
Simple Transistor RC Model
Simple Wire RC Model
• MOSFET Fabrication •
Intel Metal Stacks: 90nm and 45nm
Adapted from [Weste’11]
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Simple Transistor RC Model
Simple Wire RC Model
• MOSFET Fabrication •
Intel Metal Stacks: 45nm with M9 and I/O Bump
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Adapted from [Weste’11]
Simple Transistor RC Model
Simple Wire RC Model
• MOSFET Fabrication •
Intel Metal Layer Dimensions in 45nm
ECE 5745
Layer
t (nm)
w (nm)
s (nm)
pitch (nm)
M9
7µm
17.5µm
13µm
30.5µm
M8
720
400
410
810
M7
504
280
280
560
M6
324
180
180
360
M5
252
140
140
280
M4
216
120
120
240
M3
144
80
80
160
M2
144
80
80
160
M1
144
80
80
160
T02: CMOS Devices
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Adapted from [Weste’11]
Simple Transistor RC Model
Simple Wire RC Model
• MOSFET Fabrication •
IBM Metal Stacks
IBM 11-layer Copper Metal Stack
IBM 6-layer Copper Metal Stack
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T02: CMOS Devices
Adapted from [Weste’11]
27 / 33
Simple Transistor RC Model
Simple Wire RC Model
• MOSFET Fabrication •
Bulk vs. Silicon-on-Insulator Processing
I Eliminates parasitic capacitance between source/drain and the body
! lower energy, higher performance
I Lower subthreshold leakage, but threshold voltage varies over time
us ISIO
Processing
10–15%
increase in total manufacturing cost due to substrate cost
tance -> lower energy, higher-performance
T02: CMOS Devices
ECE 5745
n hard” application (space craft) - saphhire
Adapted from [Asanovic’11,Weste’11]
28 / 33
‣
cost.
Simple Transistor RC Model
Simple Wire RC Model
Lithography
Lecture 02, Introduction 1
• MOSFET Fabrication •
CS250, UC Berkeley Fall ‘11
49
‣
desired (drawn)
I Resolution of patterns far exceeds wavelength
Current state-of-the-art
modified mask
‣
photolithography
tools
of light used for exposure which
is usually
use deep ultraviolet (DUV)
193 nm generated with an light
argon
laser
withfluoride
wavelengths
of
I Sophisticated tricks used
exposure
248 and 193 nm, which
allow
minimum
feature µm
to
pattern
10–100
sizes down to 50 nm.
features including immersion lithography,
optical proximity correction, double patterning
Lecture 02, Introduction 1
ECE 5745
Optical proximity correction
(OPC) is an enhancement
technique commonly used to
compensate for image errors
due to diffraction or process
effects.
SEM of Mask
Lithography
T02: CMOS Devices
50
CS250, UC Berkeley Fall ‘11
29 / 33
Adapted from [Asanovic’11,Weste’11]
Simple Transistor RC Model
Simple Wire RC Model
• MOSFET Fabrication •
Processing Enhancements
I High-K Dieletrics and Metal Gates –
Replacing silicon dioxide gate dielectric
with a high-K material allows increased
vertical electric field without increasing
gate leakage
I Strained Silicon – Layer of silicon in
which silicon atoms are stretched
beyond their normal interatomic distance
leading to better mobility
I Gate Engineering – Multiple transistor
designs with different threshold voltages
to allow optimization of delay or power
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T02: CMOS Devices
Adapted from [Asanovic’11,Weste’11]
30 / 33
Simple Transistor RC Model
Simple Wire RC Model
• MOSFET Fabrication •
FinFET Transistors
I Small footprint, but good control of the gate
due to using the vertical dimension
I Intel is using FinFETs
in 22 nm process
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Adapted from [Weste’11]
Simple Transistor RC Model
Simple Wire RC Model
MOSFET Fabrication
Take-Away Points
I Although a basic understanding of devices and fabrication is important
for understanding technology constraints, mostly in this course we will
focus on first-order RC models of CMOS logic, state, and interconnect
I In the next topic of this part of the course, we will briefly introduce
CMOS circuits using these devices
. Combinational Logic: static CMOS, pass-transistor, tri-state buffers
. Sequential State: latches, flip-flops
I In the next part of the course, we will explore the details of how to
quantitatively evaluate the cycle time, area, and energy of these digital
circuits
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Simple Transistor RC Model
Simple Wire RC Model
MOSFET Fabrication
Acknowledgments
I [Weste’11] N. Weste and D. Harris, “CMOS VLSI Design: A Circuits
and Systems Perspective,” 4th ed, Addison Wesley, 2011.
I [Terman’02] C. Terman and K. Asanović, “CMOS Technology,” and
“Wires, ” MIT 6.371 Introduction to VLSI Systems, Lectures, 2002.
I [Asanovic’11] K. Asanović, J. Wawrzynek, and J. Lazzaro,
“Introduction,” UC Berkeley CS 250 VLSI Systems Design, Lecture,
2011.
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