Download Si2 Power Reduction Stimulus - Si2: Home Page

Si2 Power Reduction
Stimulus™
Version 1.0
06 November 2008
Published by
Silicon Integration Initiative, Inc. (Si2TM)
9111 Jollyville Road, Suite 250
Austin TX 78759
Copyright © 2008 by Si2, Inc.
All Rights Reserved.
Si2 trademark rules apply
The requested document describing the Si2 Power Reduction Stimulus and all materials and information therein, are provided as is and
without warranty of any kind. The authors, editor, publisher, and contributors specifically disclaim warranties of any kind whether express or
implied, with regard to any material contained herein, including, without limitation, any warranties of title, non-infringement, merchantability,
or fitness for a particular purpose or arising from course of dealing or usage in trade are made or shall apply.
In no event shall the authors, editors, publisher, or contributors, be responsible or liable for any loss of profit or damages, direct or indirect,
including but not limited to, special, incidental, punitive, indirect, or consequential damages of any nature arising from or relating to the
specification or any materials or information therein, even if advised of the possibility of such loss or damages.
The following description outlines an approach adopted by much of the industry regarding Low Power Design Techniques. This information
is provided only as a description of the current state of the art, and does not constitute a recommendation or contribution on the part of Si2
or any Si2 initiative or Member regarding implementation approaches. This information is not a standard or a specification that has been
approved or adopted by Si2 or by any Si2 initiative or Member, including without limitation Si2's Low Power Coalition (the "LPC"), and has
not been subjected to a "Call for Patents" by the LPC. All information in this description is provided "AS IS" without warranty or
representation of any kind including without limitation any warranty or representation of merchantability, fitness for particular purpose or noninfringement. No information in this description shall obligate Si2 or any Si2 Member to grant licenses under any patent rights controlled by
Si2 or such Member with respect to any implementation or other use of this information.
Notice: Attention is called to the possibility that implementation of these guidelines may require use of subject matter covered by patent
rights under which a license may be required. Si2 shall not be responsible for identifying patents or patent applications for which a license
may be required to implement Si2 guidelines or for conducting inquiries into the legal validity or scope of those patents that are brought to its
attention. By publication of this document, Si2 takes no position with respect to the existence or validity of any patent rights. A list of any
member submitted certificates and exclusions are also available from Si2.
Si2 makes no representation as to the reasonableness or nondiscriminatory nature of the terms and conditions of the license agreements
offered by any such holder(s). Further information may be obtained from Si2 upon request.
Copyright: This document is subject to protection under Copyright Laws: Copyright (c) 2008 Si2, Inc. All Rights Reserved Worldwide. Any
unauthorized use, reproduction, modification, or distribution of this document is strictly prohibited. Si2 will make a royalty-free copyright
license available upon request.
Trademarks: Where manufacturer or vendor designations claimed as trademarks are used herein, and the publisher or authors were aware
of the trademark claim, such designations have been printed in initial caps or all caps.
Restricted rights: Use, duplication, or disclosure by the Government is subject to restrictions as set forth in FAR52.227-14 and
DFAR252.227-7013 et seq. or its successor.
Rev 0.6
Power Reduction Techniques (PRT) Document
1 Objective
Objective of this XLS is to identify and list all low power techniques used in minimizing
power consumption in silicon and systems. The list is intended to drive the flow and
format requirements and reach convergence.
2 PreSilicon Decision Stage
Three decision stages are identified for Presilicon design ESL is the architectural and
high level design stage. Design indicates the micro architecture and RTL definitions.
Implementation indicates the RTL2 silicon conversion process.
3 PostSilicon Decision Stage
The mark in this column indicates if the techniques has impact and a requirement for
usage model in post silicon stage. This is created to indicate if the silicon designers
need to make post silicon users aware of the techniques and appropriately provide a
use model.
4 Technique Classifications
All low power techniques are classified in five categories. Clock techniques are related
to optimal usage of clock. Activity control related techniques are different hooks to
monitor and control activities. Voltage Techniques are related to control of operating
voltage and power gatings in the silicon and systems. Circuits and process are related
to manufacturing processes and special circuit usage in silicon. Firmware techniques
are related to software and hardware integrations in system design.
5 Power Impact
The power impact colum indicates the major impact of the techniques. In some cases,
both active and leakage are impacted.
Various Techniques in Power Aware Flow
Power Reduction Technique
ESL
Clock Gating
Dynamic Frequency Scaling (DFS)
X
X
GALS, 1/2 clock, no clock designs
X
Retiming
Dynamic Voltage and Frequency Scaling (DVFS)
Precomputation
X
Pre Silicon Decision Stage
Design
Implementation
Clock Control Oriented
X
X
Analysis
X
X
4,5
4
X
X
4
X
X
4
X
X
Major Power Impact
Dynamic
Leakage
X
HW Activity Control Techniques
X
X
X
4,8
X
4
Description
Shut off clocks when not used/predicted to be used in logic.
This refers to approaches that dynamically change the speed at
different layers of an embedded system, e.g., as compile-time
tool or as operating system extension. These approaches predict
application run-time
Clock tree power optimizations with Globally Asynchronous but
Locally Synchronous designs.
Place ff in circuit nodes with high switching activity and high load
cap, which results in glitches not being propagated and reduction
in total switching activity.
Voltage and frequency dynamically varied based on application
behavior.
Selective precomputation of output logic values of a circuit one
cycle before they are required and then use the precomputed
values to reduce internal switching activity of the logic in the
succesive clock cycle.
State encoding in fsms to reduce logic activity in the input and
output combinatorial blocks.
Techniques to minimize power consumed by systems having
wide and large busses. Covers a variety of techniques for
example, one hot encoding, Bus-invert encoding, etc.
Operand isolation is a technique to minimize the power overhead
incurred by redundant operations by selectively blocking the
propagation of switching activity through the circuit
Logic synthesis based on activities and logic state
Removal of intermediate inverters requires logic duplication for
generating both the negative and positive signal phases for
domino logic
Reduce power by buffer resizing
Reduce TDP by balance load, example clock cycle stealing
Memory slice and partition tradeoff based on per slice VS single
SRAM power. Also, latch array VS SRAM, etc
State encoding
X
X
4
Bus Encoding
X
X
4
Operand isolation
X
X
X
4
Dynamic and static synthesis power optimization
Phase Assignment
X
X
X
X
X
X
4
4
X
X
X
X
X
X
X
X
X
X
3,4,6,9,10,11
X
3,4, 6,7,9,10,11
X
On-die power gate and off chip voltage regulation
3,4,6,7,9,10,11 Multiple supply is always alive but can change the voltage levels
based on a power mode.
Power aware buffering and gate sizing
Work load Balancing
SRAM partitioning
Dynamic voltage scaling
X
X
Voltage Control Oriented Techniques
X
X
Power shut off
X
X
X
Multi supplies
X
X
X
State dependent Leakage reduction
Vt Optimization
Device stacking
Variable threshold biasing
Device channel bias
Long channel standard cell optimization
Process and Circuit Oriented Techniques
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
4
2,4
4, 8
8
8
8
8
8
8
Closed or open loop voltage scaling based on frequency and/or
silicon performance
Leakage power reduction based on cell input logic states
Process Vt optimization to meet power performance needs.
Devices are stacked on top of each other to reduce leakage.
Using bias to control threshold voltages
bias channel length based on timing
Similar to mixVt but with separate long channel libraries
Test Power Reduction
Power Aware ATPG & optimization
Power aware test insertion
X
X
X
X
X
6,13,14
6,13,14
ATPG optimizes test time vs power consumption.
Power aware scan chain stitching to reduce dynamic power hot
spots
Profile dynamic and standby power to guide load balancing and
power domain partitioning
Identify power usage due to speculative branching and fetch,
while generating fetch unit usage profile. Also includes power
aware compilation to distribute tasks in parallel SIMD.
Hardware VS firmware partition
Firmware power
Device operation power profile optimization
X
X
X
1,2,3,4
Compiler power optimization
X
X
X
2,3,4
Algorlithm mapping
X
X
X
2,3,4
Power Aware Activities and Stimulus
Power activities are simulation data used to facilitate power analysis, optimization, and related analyses. The activities are a result of a simulation; the activity data (in whichever form) is post-processed to accomplish the desired operation. The activity data can be represented in several forms - power vectors, switching activities, or switching events - the appropriate form depending upon the desired type of power analysis or optimization. The
table below indicates the most appropriate form for operations during each of the three design phases.
S.No
Design
Phases
Design Task
1
Power delivery specification
2
Thermo design power (TDP)
*System environment specification
*Packaging requirement
*Worst case junction temperature
3
Recommended Activity Form
ESL
SE
Design
SE
Implementation
ESL
SA
Design
SA
Stimulus purpose and requirements
Activity or stimulus needed for peak power requirements for power regulation. Note that SA does not contain
sufficient information to specify power supply transisent response requirements, hence instantaneous power must
be calculated for multiple cycles.
Stimulus combined with all thermo resistant components of the chip, heat sink, and operating environment to
provide targeted junction temperature. A sufficient number of cycles must be simulated so as to exceed the thermal
time constant of the system. If we consider dynamic thermal load balancing then multiple SA files would be needed.
SA
Energy analysis (battery life)
Implementation
ESL
SE or SA
Design
SE or SA
Stimulus required for long term energy analysis, joules = power * time. In order to evaluate energy efficiency of a
system, multiple time sliced SA files representing real operation are needed. For time dependent energy analysis
SE is used, and for time averaged energy analysis SA is used.
SE or SA
4
Implementation
ESL
Design
Dynamic power analysis
Implementation
ESL
5
Design
Fine grain clock gating optimization
6
Implementation
ESL
Design
Chip level power plan
7
Implementation
ESL
Design
Power gate optimization
8
Implementation
ESL
Design
Leakage power analysis and optimization
Implementation
ESL
9
Static IR analysis
(time averaged voltage drop analysis)
Dynamic voltage drop analysis
SE or SA
SA
SA
SA
Stimulus required for performance, leakage, and area impact analysis for power gate budget and simulation. A
sufficient number of cycles with power management control enable may be simulated so as represent actual chip
functional operation to insure on-die power gate’s robustness meets chip performance in worst case operating
conditions and leakage power requirement in the standby mode.
SA
Stimulus provides power mode and power state dependent activities for leakage power analysis and optimization.
Additional weighted activity information can be used for cell level state dependent leakage optimization.
SA
SA
(instantaneous voltage drop analysis)
Implementation
ESL
Design
Power Grid EM analysis (DC average, RMS, and/or peak)
Implementation
ESL
Design
12
Signal net EM analysis
SE
(peak & RMS)
SE
13
14
Implementation
ESL
Design
Device burn in
Implementation
ESL
Design
ATE test power
Implementation
Power Definitions
Dynamic Power = cell internal and wire switching power
Leakage Power = Sub-threshold and gate leakage
Total Power = Dynamic Power + Leakage Power
Stimulus and Acitivity Definitions
SE (Switching Events) = a non-aggregated collection of all switching events covering at least one or more cycles, an example of which is VCD (ie, the simulation output)
SA (average Switching Activities) = an aggrated count of switching events over a period of time, an example of which is SAIF. Note that SA can be derived from SE.
SS (Selected Switching events) = a non-aggregated collection of all switching events covering no more than one cycle, an example of which is VCD (ie, the simulation output). Note that SS is a subset of SE and can be derived from SE.
Stimulus required for estimation of IR drop use for initial chip level power plan. A sufficient number of cycles may be
simulated so as represent actual chip functional operation to insure on-die power plan’s robustness in worst case
operating conditions..
SA
SS
11
Activities or stimulus enables analysis and optimization for dynamic power in each of the three design phases. The
activities and stimulus enable simulation of data flow, power management policies, clock gate efficiency, voltagefrequency scaling, data path switch activities, etc. For dynamic power profile generation (time dependent) we would
use SE and for the time averaged version we would use SA
Set of functional stimulus to provide designers and synthesis tools in efficient clock gate implementation and
optimization. Stimulus needs to provide both clock gate efficiency and power saving from clock gates
SA
Design
Implementation
ESL
Design
10
SE or SA
SE or SA
Power grid voltage drop analysis using time averaged, or time invariant (effective dc), currents for the V = I*R
calculations. I is determined from the time averaged power consumption values for each instance connected to the
grid by integrating the current consumed by each instance over the simulated time period. This type of voltage drop
analysis is used as a rough check of the power grid’s integrity.
Power grid voltage drop analysis using instantaneous, or time varying, currents for the V(t) = I(t)*R + C*(dv/dt)*R +
L*di/dt calculations. I is determined from the time varying power consumption values for each instance connected
to the grid by computing a current consumption waveform for each instance over the simulated time period. DVD is
used as a detailed check of the power grid’s integrity and to verify time dependent issues such as decoupling
capacitor effectiveness package resonance and voltage drop induced delay effects
Power rail electromigration (EM) analysis requires time-dependent average and peak current stress at high
temperatures to determine a product’s long term life time reliability. To calculate the uni-directional current density
through the power rail, average and worst case average switching activities will be needed. Multiple SE files may
needed to be evaluated so as to find the maximum amongst those multiple SS files. For DC avaerge, multiple SE
DC average for a signal net is zero. Maximum RMS current based on signal switching and clock net activities
based on aggregated operations are needed to calculate temperature rise due to Joule heating effect. Multiple SE
files may need to be evaluated so as to find the maximum amongst those multiple SE files.
Full trace of device inputs and outputs needed from which to generate dynamic and static Burn-in tests for AC-EM,
DC-EM, NBTI, HC, etc
SE
SE
Full trace of device inputs and outputs needed from which to generate ATE test program. Static power SA to
provides die level leakage current screening. Stimulus provides power analysis to avoid excess junction
temperature during ATE testing.