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DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING EEL 6323: Advanced VLSI Design 20-Bit CMOS SRAM DESIGN REPORT (0.25-µm Process) Design Team Surendra Boppana Sailash Mani Shashank Nallani Rajesh Pydipati BMNP20A 20-Bit SRAM Design Project Contents NO TITLE Page 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. INTRODUCTION DESCRIPTION CHIP ORGANIZATION BLOCK DIAGRAM DESIGN CHIP COST CALCULATION COMPARISON WITH CUSTOMER SPECIFICATIONS CONCLUSION REFERENCES GRADING DECLARATION APPENDIX I: SCHEMATIC OF BASIC COMPONENTS II: LAYOUTS OF BASIC COMPONENTS III: MISCELLANEOUS 3 3 3 5 5 8 9 9 9 10 10 © 2004 Boppana Mani Nallani Pydipati, Inc. 2 February 2004 BMNP20A 20-Bit SRAM Design Project Introduction The need for faster, low power static-type memory devices for use as main storage has been realized by CMOS technology. CMOS circuits have inherent advantages of low power and large noise margin. Therefore, there has been a great demand for memories possessing not only lower power and high density, but also high speed comparable to the NMOS and bipolar ECL memories. The goal of our project is to design a 5 by 4 bit SRAM, which uses the 0.25-micron CMOS process. In order to meet the customer’s requirements we have designed the memory to be as fast, small, and economical as possible. We used Cadence design tool to draw the schematic and symbols of all the sub cells. Transistor sizing were also estimated at the same time using hand calculation and simulation as well. This helped us achieve an optimal transistor sizing, and propagation delay. Description The goal of this project is to design a SRAM which needs to store 20-bits of information, the customer required that memory address and data drivers can drive a 2-pF load with propagation delay of 0.5-ns and each line of data bus (output) has an associated capacitance of 2.7-pF, the maximum access time is 13-ns for supplying a valid address to the input of the address driver and to retrieve the data. Chip Organization Design and organizational concepts are crucial in improving chip performance and increasing circuit margins. This could be proved in the chip operation, the overall timing approach, and the small number of clocks used. The IC is a CMOS static random-access memory organized as 5 by 4 bits. Design Features Storage of 20 bits of information (5 by 4 bit) 13-ns maximum access time (either for read or write) Single supply of 3 volts Low static power dissipation Four outputs (denoted as D0, D1, D2, and D3) Commercial operating temperature range: 0C-50C ESD Protection Memory capacity upgradeable to 40 bits with a word length of 8 bits by connecting two chips in parallel © 2004 Boppana Mani Nallani Pydipati, Inc. 3 February 2004 BMNP20A 20-Bit SRAM Design Project Pin Configurations A0 A1 A2 D0 D1 BMNP20A CE D2 CLK D3 GND R/W’ Vdd Pin Descriptions Pin Name A0 A1 A2 D0 D1 D2 D3 Vdd GND CE R/W’ CLK © 2004 Boppana Mani Nallani Pydipati, Inc. Pin Function Address Line Address Line Address Line Data Line Data Line Data Line Data Line Power Supply Ground Chip Enable / Chip Select Read Enable / Write Enable Clock 4 February 2004 BMNP20A 20-Bit SRAM Design Project Block Diagram R O W A0 RS 0 D . E . C . O D RS 4 E R A1 A2 MEMORY ARRAY 5X4 bit R/W’ WRITE DRIVER READ DRIVER CONTROL LOGIC CE DATA BUFFER Design The SRAM chip has seven basic components. They are the basic memory cell, the row decoder, the sense amplifier, input circuitry, bit line conditioner, buffers and pads. The design considerations of each of these components and the means by which they were satisfied are discussed in the following sections. SRAM Memory Cells The memory cell is a 6–transistor circuit which is a flip flop comprising two cross-coupled inverters and two access transistors, the access transistors turn on when the word line is selected (high) and its voltage rises to Vdd, and they connect the flip flop to the bit lines. Sizing of the transistors in the memory cells is very important especially for speed and chip cost. We set the aspect ratio (Width/Length) to be 580/300 and 870/350 for the SRAM cell’s internal PMOS and NMOS transistors respectively and 580/350 for the NMOS R/W enable transistors in the cell to ensure that: © 2004 Boppana Mani Nallani Pydipati, Inc. 5 February 2004 BMNP20A 20-Bit SRAM Design Project Bit lines switch rail to rail successfully Read operation does not destroy the stored information in the cell Modification of the stored information during the data-write phase be allowed Circuit is immune from noise in certain range This sizing is satisfactory as simulations show that the bit lines pre-charge to the power supply (Vdd). 3X5 Row-Decoder The 20-bit SRAM chip requires a 3 to 8 decoder of which only 5 lines will be employed for the row select lines in the array. The input terminals of the row decoder are A0, A1 and A2 to which the address lines of the processor are interfaced. The output lines are connected to the row select lines of the memory array. The logic of the row decoder is implemented using NOR Gates. The schematic of the row decoder is attached in the appendix. Truth Table of the Row Decoder Input Output A0 A1 A2 RS0 RS1 RS2 RS3 RS4 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 0 0 1 © 2004 Boppana Mani Nallani Pydipati, Inc. 6 February 2004 BMNP20A 20-Bit SRAM Design Project Sense Amplifier The sense amplifier is important in the total performance of the SRAM chip since the sense delay time directly affects the access time. Sense amplifier is used to sense the small changes in voltage that results when a particular cell is switched onto the bit line. One stage differential pair of sense amplifier is utilized here. The sense amplifier circuit is controlled by a clock signal, which is synchronized with the pre-charging and wordline signals. Read-Write and Enable Circuitry R/W’ and CE signals control the read and write circuitry. The write operation is processed when the R/W’ is low and CE is high, while the read operation is realized when the R/W’ and CE are both high. Bit Line Conditioning Bit line conditioning circuit is used to pre-charge the bit lines with high voltage level. A p-channel transistor is used to pre-charge the bit and bit~ lines. This will dramatically improve the access time of the SRAM cell. Also it reduces the power dissipation because the bit lines do not change with the supply voltage. Output Buffer A two-stage buffer is introduced in each line on the data bus (output) that is meant to drive a 2-pF capacitive load to reduce the access time within the customer requirements. Bond Pads The input/output pads and the drivers associated with them are provided by the foundry for the CMOS process. Four bi-directional pads are used for the data pins (D0-D3) and the remaining eight are input pads, of which one is for Vdd and one for GND. Temperature dependence of 20-bit SRAM The whole circuit is simulated in the temperature range of 0-50C. The results are shown in the appendices. It turns out that the propagation delay increases with temperature. © 2004 Boppana Mani Nallani Pydipati, Inc. 7 February 2004 BMNP20A 20-Bit SRAM Design Project Chip Cost Calculation The total cost is 41 cents per chip. However, if we want to make a 45% profit, the total price will be 60 cents. The calculation is shown as follows: Area calculation SRAM width= 870 µm SRAM height = 870 µm Chip area = 0.7569 mm2 Cost calculation Wafer area: /4 x 152.4 x 152.4 mm2 (As 6 inch = 152.4 mm) Wafer cost: $1400 Package cost: 2.5 cents/pin Test cost: 5 cents/IC Profit: 45% D0: 1.5 /cm2 Achip: 0.7569 mm2 No.of Die/wafer A wafer A chip π/4 152.4 2 24100 0.7569 1 e AD0 2 1 e 0.0075691.5 2 Y( ) ( ) 98.87% AD 0 0.007569 1.5 Cost/IC $1400 5.88 cent s 24100 0.9887 The total cost /chip = IC cost + package cost + test cost = 5.88+12*2.5+5=40.88 cents The total price /chip=40.88(1+0.45) = 59.3 cents (45% profit included) Cost of the chip = $0.60 © 2004 Boppana Mani Nallani Pydipati, Inc. 8 February 2004 BMNP20A 20-Bit SRAM Design Project Comparison of design results with customer’s specifications Memory Capacity: The customer needs to store 20 bits of information and our chip provides the required memory capacity. Memory capacity can be extended to 40 bits with a word length of 8 bits by connecting two chips in parallel. Read Time: The maximum read time we get in our design is approximately 1-ns which is well below the customer’s specification. Write Time: The maximum write time we get in our design is approximately 1-ns which is well below the customer’s specification. Load Capability: Our design is capable of driving a 2pF load which matches the customer’s specification. Power Supply: Power supply requirement of 3V may be supplied by two D cell batteries. Temperature Range: Our design has been successfully tested over a temperature range of 0C to 50C to satisfy the customer’s requirements. Size and Cost: We have designed our chip to be extremely small and cost effective without compromising any of the customer’s requirements. Power Consumption: Since our design employs CMOS logic, the static power consumption is considerably reduced. The chip enable logic used also aids in reducing the power by disabling the sense amplifier circuit when the chip enable line goes high. Conclusion The 0.25-micron technology CMOS design of the 20-bit Static Random Access Memory was successfully completed to satisfy all of the customer’s specifications. Read time and Write time of the SRAM chip is 1-ns and 1-ns which are far below the customer’s specification. The memory capacity can be expanded to store 40 bits of information by connecting two chips in parallel. References 1. 2. 3. 4. Jan M. Rabaey et al., Digital Integrated Circuits: A Design Perspective, 2nd Edition, Prentice Hall, 2003 IEEE Journal of Solid-State Circuits, Vol.SC-19, No.5 October 1984 IEEE Journal of Solid-State Circuits, Vol.SC-20, No.5 October 1985 Lecture notes of Dr. William R. Eisenstadt, Associate Professor, Dept of ECE, University of Florida © 2004 Boppana Mani Nallani Pydipati, Inc. 9 February 2004 BMNP20A 20-Bit SRAM Design Project Grading Declaration Name Work Contribution Surendra Boppana 1/4 Sailash Mani 1/4 Shashank Nallani 1/4 Rajesh Pydipati 1/4 Appendix I. Schematics of Basic Components A1: Schematic of SRAM chip A2: Schematic of Row Decoder A3: Schematic of Read Circuit A4: Schematic of Write Circuit A5: Schematic of Data Buffer (First Stage) A6: Schematic of Data Buffer (Second Stage) A7: Schematic of Differential Amplifier II. Layouts of Basic Components B1: Layout of SRAM chip with I/O Pads B2: Layout of SRAM chip B3: Layout of Row Decoder B4: Layout of Read Circuit B5: Layout of Write Circuit B6: Layout of Data Buffer (First Stage) B7: Layout of Data Buffer (Second Stage) B8: Layout of Differential Amplifier III. Miscellaneous C1: Output of the LVS match C2: Simulated Read & Write time of the SRAM at room temperature © 2004 Boppana Mani Nallani Pydipati, Inc. 10 February 2004