Download Static Random Access Memories (SRAM) Key

EE371 Spring 1999
Static Random Access Memories
(SRAM)
Birdy Amrutur
[email protected]
EE371 Spring 1999
Key features of SRAMs
Holds data statically:
As long as power is supplied to the chip, the data
remains.
Data randomly accessible:
ReadData = Memory[ Address ]
Memory[ Address ] = WriteData
EE371 Spring 1999
SRAMs Used as:
Embedded memory, e.g.:
First and second level caches in processors
Data buffers in various DSP chips
Standalone SRAMs:
Caches in computer systems
Main memory in low power applications
Typical sizes:
Embedded: upto 1Mbit
Standalone: upto 16Mbit
EE371 Spring 1999
The system level view of SRAMs
tAC
Asynchronous interface
tAA
Ai
Aj
address
data in
M [ 0 .. 2n ]
data out
address
r/w
r/w
M [ Ai ]
Used for stand alone SRAM chips
data out
data in
Synchronous interface
tsu
tcyc
clk
Ai
address
Aj
address
data in
r/w
M [ 0 .. 2n ]
data out
r/w
clk
M [ Ai ]
Used for embedded and standalone SRAMs
data out
data in
EE371 Spring 1999
SRAM Architecture
2m
Row decoder
word line
bitline
2n
m
Address input
n
Column Mux
Column decoder
Sense en
Write en
Read enable
Sense amplifier
Read-write control
Write driver
Data in
Data out
EE371 Spring 1999
CMOS SRAM cell
Vdd
b
b
wp
wp
wa
wa
wn
wordline
a) Static cell
b) 6T CMOS cell
c) 4T poly-R cell
d) 6T poly-PMOS cell
wn
EE371 Spring 1999
Reading a cell
b
b
0
wl
1
a
a
Cb
τ
b,b
∆v
a
Icell
a
wl
∆v =
Icell * τ
Cb
Sense Amplifier
D
EE371 Spring 1999
Writing a cell
b
b
wl
0
1
a
Cb
a
Icell
write
a
a
wl
D=0
b
D=1
b
EE371 Spring 1999
Bitline precharge and load
Pre
Pre
Pre
Important to
equalize bitline
voltage before
reads
cell
wl
b
cell
wl
cell
wl
b
b,b
Pre
Pre
wl
wl
vdd
vdd -vtn
b,b
Pre
b,b
∆v
wl
∆v
Precharged to Vdd .
Precharge shut off during reads
and writes
Bitline voltage clamped during reads. Precharge to an Nmos threshold
below supply
Use with latch style sense amps
Use with current sense amps
Useful with current mirror
sense amps
(Cant operate with low supply)
EE371 Spring 1999
Sense amplifiers
Need to amplify input bitline swing of ~100mV to full digital levels.
b
b
b
b
Sense clock
Sense enable
Current mirror amplifier
Latch type amplifier
EE371 Spring 1999
Decoders
1
16
1
16
Logically an n-input AND function.
word driver
Enables the “Random Access” portion
of RAMs.
CL
Row decoder in the critical path of the
SRAM access.
Could contribute upto 40% of the delay
and power
256
Large decoders implemented
hierarchically.
A0A1A2A3
4 to 16 predecoder
A0
A1
A3
An 8 to 256 decoder
EE371 Spring 1999
Sram Partitioning
Divided word line Architecture
block
select
global
bitlines
local
word line
word line
address
local senseamp
IO lines
global sense
amp
dout
Use higher level metal for global word lines
din
EE371 Spring 1999
Bitline partitioning
512
Wordline drivers
Wordline drivers
256
256
sense amps
Single Level Mux
Global
Bitlines
Two Level Mux
Use higher level metal for global bitlines
EE371 Spring 1999
Partioning summary
Partioning involves a trade off between area, power and speed
For high speed designs, use short blocks(e.g 64 rows x 128 columns )
Keep local bitline heights small
For low power designs use tall narrow blocks (e.g 256 rows x 64 columns)
Keep the number of columns same as the access width to minimize wasted power
EE371 Spring 1999
CMOS SRAM cell design-1
Vdd
b
b
wp
wp
a
a
wa
Problem: Find wa, wd, wp such that
1) minimize cell area
2) obtain good read and write cell margins
3) good soft error immunity
4) good cell read current
wa
wd
wd
in that order
wl
Conflicting goals!
a
Vdd
Vdd
Static Noise Margin
wp
wa
a
a
wd
Vdd
a
EE371 Spring 1999
CMOS SRAM cell design-2
Read Stability
Vdd
b
Usually Cbit is very big compared to internal
node capacitances
b
wp
wp
wa
Cell will flip if the “0” node bounces high
enough to cause the “1” node to discharge
wa
a
(=0)
(1=) a
wd
Cbit
wd
Simulate for worst case scenario with threshold
and size mismatches in the cell which aids in
flipping
To obtain good stability :
β = wd * ( Vdd - Vtn ) 2 = wd
wa * ( Vdd - Vtn ) 2
wa
wl
> 2.5
Vdd
Vdd
Vdd
wp
wa*1.1
wp
a
a
Vdd
+
wd
δ Vt
wl
wa
+ δ Vt
wd*1.1
b,b
a
a
Dynamic read noise margin
EE371 Spring 1999
CMOS SRAM cell design-3
Write Stability
Vdd
Vdd
wp
Cell is written by discharging the “1”
node low. This causes the “0” node to
charge up.
wp
wa*0.9
wa
a
( = 0)
wd*1.1
-
Need to ensure that
(1=) a
+
δ Vt
wa * µn*(Vdd-Vtn)2 > wp*µp*(Vdd-Vtp)2
+
δ Vt
wd
Hence use minimum sized pMOS
load devices.
Gnd
Vdd
wl
b
b
a
a
Dynamic write noise margin
EE371 Spring 1999
CMOS SRAM cell design-4
Soft Error Immunity
Vdd
b
α−particle can create electron-hole pairs in
the channel of a “off” transistor.
b
a
This causes the “off” transistor to leak away
some of the stored charge.
a
(=0)
(1=)
Two solutions to the problem:
Cbit
Increase stored charge ( > 20fC ) - use larger
transistors (more capacitance), bigger voltages
Use system level solution like redundancy
bits for error detection and correction
α - particle (He2+)
a
b
wp
b
a
Cell Layout
metal 2
metal 1
poly
wn
diffusion
Simple layout in MOSIS design rule. Cell area
is 66.5 µm2 (1064λ2) in 0.5µm CMOS
Advanced processes with tighter rules + clever
non-manhattan (non-right angle) layouts
reduce cell area significantly
(typically ~650λ2)
contact
wl
wa
Poly-R and poly-PMOS cells have 2-3 times
smaller area as the load devices can be laid
out on top of the nMOS transistors