Download CMOS Circuit Design

CMOS Circuit Design
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6.1 Introduction
CMOS circuits are used in many applications from gate arrays to control logic.
They have the advantage over NMOS circuits in that they do not require active
pull-up loads. For a CMOS inverter stage only one of the transistors conduct at a
time. In the low output state the pull-down transistor conducts and the pull-up
transistor is off. When the output is high the pull-up transistor conducts and the
pull-down transistor is off. Pure CMOS circuits conduct very little current and,
at low digital frequencies, consume small amounts of power. Most of the power
dissipation is due to a changing logic state because both the pull-up and pulldown transistors are conducting. Thus, CMOS circuits dissipate an increasing
power for increasing digital signal frequency.
6.2 CMOS processing
The three main types of CMOS processes are:
• n-well CMOS which uses a p-type substrate. As with NMOS technology, the
NMOS transistors are formed by diffusing n-type material into the substrate.
For the PMOS transistors, a well of n-type is diffused in the substrate and the
p-type diffusion then defines the drain and source of the PMOS transistors.
This type is compatible with NMOS technology as it uses a p-type substrate.
• p-well CMOS which uses an n-type substrate. PMOS transistors are formed
by diffusing p-type material into the substrate. For NMOS transistors a well
of n-type is diffusion followed by a p-type diffusion within the well. This
technology is not as popular as n-well CMOS as it incompatible with NMOS
fabrication.
• Twin tub CMOS which uses both n-type and p-type wells in a lightly doped
substrate.
Figure 6.1 shows an n-well CMOS inverter layout. The substrate is p-type and
the diffusion for the pull-down transistor is n-type (NMOS). To create a PMOS
transistor a tub of n-type is diffused into the substrate. Next, p-type diffusion is
inserted to create the drain and source of the transistor. The source of the pull-up
transistor is joined to the drain of the pull-down by metal (as diffusion or
polysilicon creates another transistor).
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VDD
p-diffusion
n-diffusion
A
Polysilicon
Z
Metal
GND
Substrate
Silicon dioxide
A
GND
VDD
Z
n-type well
p-type substrate
Figure 6.1
n-well CMOS inverter.
6.3 CMOS inverter
Figure 6.2 shows the stick diagram of a CMOS inverter gate. In this case, the
input to the gate is polysilicon and the output connects to metal. The polysilicon
crossing the p-type diffusion creates the PMOS pull-up transistor and polysilicon
crossing the n-type diffusion creates the NMOS transistor. A dotted line shows
the demarcation for the end of the p-well. Any diffusion in the p-well is p-type
diffusion and below it is n-type. The current diffusion type is also described as
the active diffusion and the connection between metal and the diffusion layer is
named an active contact.
VDD
p-diffusion (YELLOW)
PMOS
n-diffusion (GREEN)
Polysilicon (RED)
Z
Active contact between metal
and active diffusion (BLACK)
Connection to substrate (BLACK)
A
NMOS
Demarcation line shows
the end of the p-well (BROWN)
VSS
Figure 6.2
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CMOS inverter.
Metal 1 (BLUE)
As with NMOS, the stick diagram displays polysilicon as red, n-diffusion as
green and the first metal layer as blue. For CMOS the p-diffusion layer is drawn
in yellow and the demarcation region is shown in brown. Notice that there is a
contact between the supply rails to the active diffusion (cross symbol) on each
transistor. This is because the pull-up PMOS transistor requires the substrate to
connect to VDD and the pull-down NMOS transistor requires the substrate to be
connected to VSS.
Figure 6.3 shows a possible layout of this circuit. Notice that the minimum
transistor size has been used (that is, 2λ×2λ) and that the lengths and widths of
the transistors do not have to be scaled as they were in NMOS design. This is
because only one of the transistors is on in either logic state. Note that the connection between the substrate and the supply rails has not been included in Figure 6.2. This will be covered in the next chapter which will discuss practical
CMOS cells.
2λ
VDD
A
Z
p-well
VSS
Figure 6.3
CMOS inverter.
6.4 CMOS NAND gate
A CMOS NAND gate requires two series pull-down NMOS transistors connected to ground and two parallel pull-up PMOS transistors connected to the
supply voltage. Figure 6.4 gives a stick diagram. Only when there are two low
inputs will the output go low (that is 00, 01, 10 gives a 1 and 11 gives a 0
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output). Again, metal connects to the output and polysilicon as the input. If output metal layer from one gate connects to the next gate then the layer must be
changed to polysilicon by inserting a contact between the metal and polysilicon
layers. Figure 6.5 shows a possible layout of the circuit.
VDD
B
Z
A
VSS
Figure 6.4
2-input CMOS NAND stick diagram.
VDD
2λ
B
Z
A
VSS
Figure 6.5
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2-input CMOS NAND gate layout.
6.5 CMOS NOR gate
The CMOS NAND gate requires two parallel pull-down NMOS transistors and
two series pull-up PMOS transistors. Figure 6.6 gives the stick diagram. Only
when there are two lows on the inputs will the output go high (that is 00 gives a
1, and 01, 10 and 11 give a 0 output). Again, metal connects to the output and
polysilicon to the input. Figure 6.7 shows a possible layout of the circuit.
VDD
A
Z
B
VSS
Figure 6.6
2-input CMOS NOR stick diagram.
2λ
VDD
B
Z
A
VSS
Figure 6.7
Layout of a 2-input CMOS NOR gate layout.
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6.6 Electrical characteristics
The performance of CMOS circuits is not as dependent on the length to width
ratio as only the pull-up or pull-down transistors conduct at a time. As was seen
in the previous chapter the unit resistance of n-diffusion is approximately 10 kΩ
per square for 5 µm technology and 20 kΩ per square for 1.2 µm technology. The
p-type diffusion has a higher unit resistance and is approximately 25 kΩ per
square (for 5 µm) and 40 kΩ per square (for 1.2 µm). Thus for an inverter, using
5 µm technology, with transistor ratios of 1:1 (2λ×2λ) the pull-up PMOS
transistor will have a resistance of 25 kΩ and the pull-down resistance will be
10 kΩ. These resistances can be used to determine the maximum drive current in
the low and high state, and also the power dissipation.
6.7 Exercises
6.1
Explain why the ratios of the pull-up and pull-down transistors with a
CMOS inverter do not effect the output voltage levels. Contrast this
with an NMOS inverter.
6.2
Explain what effect the L:W ratios of the CMOS inverter pull-up and
pull-down transistors will have on circuit speed.
6.3
Determine the approximate cell sizes (in nλ×mλ) for the gates in
Figure 6.3, Figure 6.5 and Figure 6.7.
6.4
Redesign the cells in Figure 6.3, Figure 6.5 and Figure 6.7 so that
each of the cell size areas are minimized.
6.5
Using the approximations developed in Section 6.6 determine the
short-circuit current of the following gates, for 5 µm technology with
a supply of +15 V and 0 V:
(a)
(b)
(c)
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inverter;
2-input NAND gate;
2-input NOR gate.