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Design Review #2 Low Leakage LUT Yang Fu and Kejia Li 1. Additional References [1] Anderson, J.H.; Najm, F.N.; , "Low-Power Programmable FPGA Routing Circuitry," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.17, no.8, pp.1048-1060, Aug. 2009 The authors studied various power reduction techniques including power gating and sleep transistors for routing switches in FPGA. Different combinations of power reduction techniques have been evaluated. [2] Park, J. C.; Mooney III, V. J.; , "Sleepy Stack Leakage Reduction," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.14, no.11, pp.1250-1263, Nov. 2006 This paper introduces a leakage reduction method based on stack effect and sleep transistors. The combining circuit can work in either high power or low leakage mode. [3] Meijer, M.; de Gyvez, J.P.; Kup, B.; van Uden, B.; Bastiaansen, P.; Lammers, M.; Vertregt, M.; , "A forward body bias generator for digital CMOS circuits with supply voltage scaling," Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on , vol., no., pp.2482-2485, May 30 2010-June 2 2010 This paper discusses the design and characterization of a FBB generator. It can adapt to scaling supply voltages. This may serve as an good reference for our FBB design in the future. [4] Garcia, J.C.; Montiel-Nelson, J.A.; Nooshabadi, S.; , "Adaptive Low/High Voltage Swing CMOS Driver for On-Chip Interconnects," Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on , vol., no., pp.881-884, 27-30 May 2007 This paper reviews the reduced voltage swing design techniques and proposed a new reduced voltage swing driver. We would like employ similar principle in our circuit design to reduce power consumption. 2. Schematics We plan to apply power gating, forward body biasing and stacking effect to out LUT to achieve low power operation. Right now we have built and simulated the forward body biasing and power gating circuit. The circuit has four major components including the input driver, multiplexor, FBB well driver and output driver. The details of each component are shown below. Figure 1 Test Bench of LUT Figure 1 shows the test bench of our LUT. Figure 2 Input Driver Figure 3 Multiplexor The pass transistors in the multiplexor are NMOS_VTG. The increased threshold voltage could reduce leakage current. We can use FBB to enhance the speed performance. Figure 4 FBB Well Driver Figure 5 Output Driver 3. System Operation The system can operate in high performance, low power and sleep modes. The four inputs should come from registers or SRAM in real FPGA. We set the inputs to “0110” (an XNOR gate) for this test. (We will explore the impact of different inputs on system performance later) The supply voltage is 1.1V. Right now we have to reconnect some wires to change operation mode. We are going to make a mode selection circuit in the next step. a) High performance mode 1 In this mode, all the headers are fully on in drivers and multiplexor. And the FBB well driver provides about 650 mV FBB to the pass transistors in the multiplexor. Figure 6 Input/Output Voltage Waveform Figure 7 Instant Power Consumption of each component inst_pwr: total power consumption mux_pwr: multiplexor power consumption out_driver_pwr: output driver power consumption in_driver_pwr: input driver power consumption Power consumption Total power Leakage power 18.8 uW 0.42 uW Delay Sel_0 Falling Sel_0 Rising Sel_1 Falling Sel_1 Rising 68.3 ps 82.3 ps 59.7 ps 77.0 ps Figure 8 Foward Body Bias b) High performance mode #2 In this mode, all the headers are fully on in drivers and multiplexor. But the FBB generator is turned off. Figure 9 Input/Output Voltage Waveform Figure 10 Power consumption of each component Power consumption Total power Leakage power 18.9 uW 0.33 uW Delay Sel_0 Falling Sel_0 Rising Sel_1 Falling Sel_1 Rising 74.6 ps 97.2 ps 66.6 ps 91.9 ps Comparing with FBB on, we can see that FBB reduces delay by 15% ~ 20% while increases leakage by 26%. c) Low power mode In this mode, all the PMOS in the headers are turned off and the power is supplied by NMOS in the header. The output voltage swing is reduced. It is useful if the circuit is followed by other reduced swing circuits. Here we have the FBB on to reduce the delay. Figure 11 Input/Output Voltage Waveform Figure 12 Power consumption Figure 13 Virtual VDD in each component during low power mode Power consumption Total power Leakage power 13.5 uW 2.4 uW Delay Sel_0 Falling Sel_0 Rising Sel_1 Falling Sel_1 Rising 102.4 ps 162.8 ps 90.1 ps 153 ps In the low power mode, the total power consumption is reduced by 27%. The delay increases by 58%. But the leakage power also increases. So this low power mode should be used in circuits that have high activity factor. d) Sleep mode In this mode, all the headers are turned off. The leakage could be reduced. Figure 14 Power consumption in sleep mode The leakage power in sleep mode is about 40 nW. We are going to use stacking effect to suppress the leakage in drivers in multiplexors. 4. Progress We have designed the baseline LUT circuit, FBB generator (Well driver) and basic header circuit for power gating. Multi-threshold transistors have been used in the design. Delay and power consumption measurement has been tested. We have also identified possible leakage sources and trade-offs of various techniques in the design process. 5. Remaining Tasks The remaining tasks can be grouped into two categories, (1) Design a) Design mode selection circuit to control high performance / low power / sleep mode. b) Use stacking effect to reduce leakage in drivers (inverters). We are going to use method similar to the one described in [2]. c) Look into the possibility of using reduced voltage swing technique to optimize our LUT. (2) Characterization a) Study the impact of different input vectors on the choice of leakage reduction scheme. b) Calculate the power consumption overhead incurred during mode changing. Try to find the best mode changing decision. c) Increase the complexity of the LUT (more SRAM bits/selection signals) to study the impact of scaling on our circuit’s performance. 6. Challenges and Questions The biggest challenge for us is that we are not quite familiar with the design methodology of VLSI circuit. We have encountered many problems when we tried to repeat the simple examples in textbooks or papers. What we need is the “feeling” for CMOS circuit design. Just like what is the appropriate value for body biasing or which parameter is the most sensitive one that requires special attention. Tweaking the transistor size is really tricky. It takes us a lot of time to figure it out. Software is another problem. Sometimes after prolonged simulation runs, the simulator stops to update the results. We have to restart the whole virtuoso session to proceed.