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List of Experiments
1. PN Junction Diode
2. Transistor Characteristics
3. FET Characteristics
4. RC Coupled Amp.
5. RC Phase Shift Oscillator
6. Positive clipper
7. UJT
8. Clamper
9. Hartley Oscillator
10. Colpitt’s Oscillator
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Experiment No.1
PN Junction Diode
Object:
To plot the characteristics curve of PN junction diode in Forward & Reverse bias.
Apparatus Required:
S.No. Apparatus
Specification
Required No.
1.
Bread Board
6*2 inch
01
2.
Voltmeter
0-10 volt D.C.
01
3.
Ammeter
0-100 mA.
01
4.
DC power supply
0-10 Volt
01
5.
Connection Wire
single wire
08-10
CIRCUIT DIAGRAM:-
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REVERSE BIAS & FORWARD BIAS:
The Basic Diode Symbol and Static V-I Characteristics.
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THEORY:- This is a two terminal device consisting of a P-N junction formed either in Ge or Si
crystal. A P-N junction is illustrated in fig. shows P-type and N-type semiconductor pieces
before they are joined.
P-type material has a high concentration of holes and N-type material has a high concentration of
free electrons and hence there is a tendency of holes to diffuse over to N side and electrons to Pside. The process is known as diffusion.
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VOLT-AMPERE CHARACTERISTICS OF P-N JUNCTION
Fig.shows the circuit arrangement for drawing the volt-ampere characteristics of a P-N junction
diode.when no external voltage is applied the circuit current is zero. The characteristics are
studied under the following two heads:
(i) Forward bias
(ii) Reverse bias
(i)Forward bias:- For the forward bias of a P-N junction, P-type is connected to the
positive terminal while the N-type is connected to the negative terminal of a battery.The
potential at P-N junction can be varied with the help of potential divider. At some forward
voltage (0.3 V for Ge and 0.7V for Si) the potential barrier is altogether eliminated and
current starts flowing. This voltage is known as threshold voltage(Vth) or cut in voltage or
knee voltage .It is practically same as barrier voltage VB. For V<Vth, the current flow is
negligible. As the forward applied voltage increases beyond threshold voltage, the forward
current rises exponentially.
(ii)Reverse bias: - For the reverse bias of p-n junction, P-type is connected to the negative
terminal while N-type is connected to the positive terminal of a battery.
Under normal reverse voltage, a very little reverse current flows through a P-N junction. But
when the reverse voltage is increased, a point is reached when the junction break down with
sudden rise in reverse current. The critical value of the voltage is known as break down
(VBR). The break down voltage is defined as the reverse voltage at which P-N junction
breakdown with sudden rise in reverse current.
Observation table:
Forward BiasS.No.
Forward voltage Vf (volt)
Forward Current If( mA)
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Reverse BiasS.No
Forward voltage Vf (volt)
Forward Current If( μA)
Result:
The V-I characteristics of junction diode in forward and reverse bias condition has been be
plotted on the graph
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Experiment No.2
Transistor Characteristics
Object:
To study and plot the Transistor input and output characteristics in the following configurations:
(a)
Common Emitter Mode
(b)
Common Base Mode
(c)
Common Collect Mode
Features:
The board consists of the following built-in parts:
1.
Two 0-10V D.C at 200mA, continuously variable power supplies for Baes Emitter and Collector
Emitter functions.
2.
Two D.C Ammeters, 65mm rectangular dial with switch selectable ranges of 200µA & 10mA.
3.
Two D.C Voltmeters, 65mm rectangle dial with switch selectable ranges of 1V and 10V.
4.
Two Silicon (NPN &PNP) transistors and two Germanium (NPN &PNP) transistors.
5.
Adequate no. of other electronic components.
Theory:
The construction of a transistor is best understood by two diode analogy where two diode are
connected back to back as shown in fig.1 (A) and fig.2 (A). A PNP transistor analogous to two diodes with
their cathodes (N-Type ) connected together to form its base terminal see fig.1(a).An NPN transistor is
analogous to two diodes with their anodes (P-type) connected together to form its base terminal, see
fig.2(A) The remaining two terminals are collector and emitter. Fig.1 (B) and fig.2 (B) show the
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diagrammatic form of PNP and NPN transistor. The circuit symbols of PNP and NPN transistor are shows
respectively in fig.1(c) and fig.2(c).
Circuit Configurations:
A transistor has three terminals hence when it is connected in a circuit one of its terminals in
common to input and output parts of the circuits. Three circuits configurations in which a transistor can
be connected are discussed below (discussion has been limited to NPN transistor):
1. Common Emitter Configuration
When a transistor is used in common emitter configuration the input is fed between its base
and emitter terminal and output is taken between the collector and emitter terminal as shown in fig.4
shows the circuit for determining the input and output characteristics of NPN transistor in common
emitter configuration. Fig 6 shows the wiring diagram for practically determining the common emitter
characteristics using this training board.
Input Characteristics:
For input characteristics, the collector voltage i.e. Vc is kept constant. The base voltage is varied
in small steps and corresponding values of base current are observed. The readings are plotted on a
graph sheet with the base voltage Vb on the X-axis and the base current Ib on the Y-axis. Fig shows the
practical curves obtained for various transistors.
From the practical curves obtained, it is observed that the curve does not start from zero base
voltage (Vb). Appreciable base current flows when the base voltages are 0.3 volts for germanium
transistor and 0.6 volts for silicon transistor. From the curve we can obtain the input resistance of the
transistor.
Input Resistance Rin = Vb/Ib, at certain Vc value
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Output Characteristics:
For obtaining the output characteristics, the base current is kept fixed at a certain value. The
collector voltage is increased in certain steps and corresponding readings of collector current are noted.
The reading can be repeated for another value of base current. The graph of Vc Vs. Ic is plotted for each
fixed value of Ib. fig shows the practical curves obtained for various transistors. From the curves it is
observed that:
1.
No collector current flows when Ib=0
2.
For a certain fixed value of base current the collector current does not vary, much with the
change of collector voltage.
The output resistance of a transistor can be obtained as:
R0 = Vc/Ic, at certain value of Ib.
Also the current gain B of the transistor can be calculated as:
B = Ic/Ib, for a certain value of Vc.
3. Common Base Configuration:
INPUT CHARACTERSTICS
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Here the input is given between base and emitter and output is taken between collector and
base as shows in fig .9 fig.10 shows circuit diagram and fig.11 shows the wiring diagram for practically
determining the characteristics in the common base configuration.
Input Characteristics:
For input characteristics in the common base configuration the collector Vc is kept constant at a
certain value. The emitter voltage Ve is varied and corresponding value of emitter current Ie are
observed. Fig.11 shows the practical curves obtained for various transistors. From these curves we
observe the following:
1.
The curves start from zero.
2.
The emitter current increases sharply at an emitter voltage which is about 0.2V for a Ge and
about 0.6V for a Si transistor can be obtained as follows:
Ri = Ve/Ie, for a certain of Vc.
Output Characteristics:
For the output characteristics of a transistor in common base configuration, the emitter current
Ie is kept constant at a certain value. The collector variations corresponding to variations of the collector
voltages are observed. Fig shows the practical curves for various transistors. From the curves, we
observe as follows:
1.
The curves start from a point 0 instead of zero.
2.
This point is about 0.2V for a Ge. Transistor and about 0.6V in case of a Si transistor.
3.
Point 0 is of polarity to the usual polarity of collector voltage.
4.
This point 0 is nearly same for all values of emitter current.
This output resistance of a transistor in common base configuration can be determined as
follows:
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R0 =Vc/Ic, for a certain of Ie.
The current gain can also be calculated as:
α = Ic/Ie, for a certain value of Vc.
CIRCUIT DIAGRAM
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3.
Common Collector Configuration:
Basic circuits are shown in fig. 12.
Input Characteristics:
For input characteristics, the emitter to collector voltage is kept constant. The base voltage is
varied in small increments and corresponding values of base current are noted. The graph is plotted
between IB and VCB from this graph, input resistance of the transistor can be determined:
Rin = VCB / IB, at certain value of VCE.
Output Characteristics:
The output characteristics show the relationship between output current IE and output voltage
VCE, at a constant value of input current IB.
Procedure:
Common Emitter:
Input Characteristics:
1.
Using suitable batch cords make connections as per shown in fig. For NPN transistor.
2.
Keep the knobs of both 0 – 10 V DC supplies to fully anticlockwise position.
3.
Switch on the power to the training board.
4.
Set the collector voltage to a certain value say 1 V.
5.
Vary the base voltage VB in 15 mV (20 mV) steps and observe the corresponding base current by
keeping the current meter in 200 A ranges.
6.
Take the observations as per table 1 and plot the readings on a graph sheet. Take VB on the Xaxis and IB on the Y-axis.
Table – 1
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S.No.
VC = .... Volt
VB
VC = .... Volt
IB
VB
IB
1.
2.
3.
4.
5.
Output Characteristics:
1.
Using suitable batch cords make connections as per shown in fig. For NPN transistor.
2.
Keep the knobs of both 0 – 10 V DC supplies to fully anticlockwise position.
3.
Switch on the power to the training board.
4.
Set the base current to a certain value say 25 A with the help of 0 – 10 V DC supply of the input
circuit.
5.
Now vary the collector voltage from 0 – 10 V in steps say 1 V and note down the corresponding
values of the collector current IC as per table 2.
6.
Repeat the collector voltage and collector current for different settings of the base current.
7.
Plot the of collector voltage along X-axis and collector current along Y-axis.
Table – 2
IB = .... A
S.No.
VC
IB = .... A
IC
VC
1.
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2.
3.
4.
5.
Result :
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Experiment No.3
Objective: To study the characteristics of FET transistor
1 Measurement of Idss.
Theory:
Although arguably the first transistor invented the field-effect transistor did not become
Established as an important semiconductor device until experience with the BJT had
Established a broadened understanding of semiconductor phenomena and technology. In
This note distinctions between the Junction Field-Effect Transistor (JFET) and the Bipolar Junction
Transistor are examined. Static terminal characteristics of two representative JFETs are examined using
a Spice computer analysis of a sophisticated device model.
Although the JFET is a different device from the BJT nevertheless various aspects of
Device use is similar in general concept if not in precise detail. The following paragraph is a modest
paraphrase of that introducing the note on BJT Biasing. In general all electronic devices are nonlinear,
and operating characteristics can change significantly over the range of parameters under which the
device operates. The junction field-effect transistor, for example, has a ‘normal’ amplifier operating
drain voltage range bounded by the VCR range for low voltages and drain-gate junction breakdown for
high voltages. It also is bounded by excessive drain current on the one hand and cutoff on the other
hand. In order to function properly the transistor must be biased properly, i.e., the steady-state
operating voltages and currents must suit the purpose involved. Our primary concern here however is
not to determine what an appropriate operating point is; that
Determination depends on a particular context of use and even more so involves a degree of judgment.
Rather we consider how to go about establishing and maintaining a given
Operating point. Where a specific context is needed for an illustration we assume usually
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That the transistor is to provide linear voltage amplification for a symmetrical signal, i.e., a signal with
equal positive and negative excursions about a steady-state value.
Junction Field Effect Transistor
The Junction Field-Effect Transistor (JFET) is a device providing a controlled transport of majority carriers
through a semiconductor. The figure illustrates the essential nature of the JFET topology; actual
geometry varies depending on the intended application and fabrication techniques. The JFET is at its
heart a nonlinear resistor fabricated from a doped semi-conductor material. To be specific we refer to
an ‘N-channel’ device, meaning the conducting material is an N-type semiconductor. Operation of the
complementary P-channel device operation is similar and can be inferred directly from the N-channel
discussion. In the figure the lightly shaded region is the conducting channel. The darker regions at the
ends of the channel are relatively heavily doped terminations for the channel to assure good
connections to externally accessible terminals.
By convention the terminal designations are defined so that carriers (electrons for the N-channel device)
flow from the source and to the drain. For the N-channel device, therefore, a voltage is assumed to be
applied so that the drain is positive relative to the source. The resistance of the channel is a function of
its geometry and the electron transport parameters of the doped semiconductor. The device as
described thus far is more or less a (temperature-sensitive) resistor. Suppose now that the channel
geometry is changed, e.g., by gouging out the white area shown on the left side of the channel. This is a
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change of channel geometry, in particular a smaller channel cross-section , which increases the channel
resistance, and therefore for a given drain-source voltage less current will flow after the gouging. Even
less current flows with further gouging. We have then a variable resistance; although a mechanically
'gouged' the resistor would have a short service life. On the other hand the channel cross-section can be
effectively varied without physically removing material.
That is, charge carriers can be effectively removed from part of the cross-section electrically reducing
the channel cross-section and so reducing its conductivity, without actual removal of bulk material. To
effectively remove carriers from a region we simply need to ‘shove’ them out of that region, and the
way to shove a charged carrier is with an electric force. The JFET makes use of the fact that a very strong
electric field exists across a PN junction, and that field effectively removes carriers from the junction
region. The ‘gate’ electrode shown in the figure is formed as a PN junction, with the channel forming
one side of the junction. The gate side of the junction is relatively heavily doped so that the junction
depletion region extends largely into the channel.
The width of the depletion region increases with increasing reverse-bias, extending further into the
channel and further increasing the channel resistance. For small values of drain-source voltage the JFET
characteristic is linear, as illustrated by the sketch. Increasing the magnitude of the (reverse-biased) gate
source voltage increases the depletion width and increases the channel resistance. The drain
characteristics correspond to a variable resistor, with a voltage-controlled resistance. The conventional
JFET icon for an N-channel device also is shown in the figure, and is identified as to type by the gate
terminal PN junction arrow. Note that following common convention the drain current is positive (in the
direction of the current polarity arrow shown) for an electron carrier flow from source to drain.
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The P-channel device icon would have the gate arrow reversed, and the voltage polarities also would be
reversed so that normally the hole carriers flow from source to drain, and the gate junction is reversebiased. The reason for the emphasis on small values of drain-source voltage in the discussion above
arises from the fact that the gate junction extends a significant distance along the channel length as well
as across the channel width. Since the channel is a continuous resistor there is a voltage drop along the
length of the channel, and so the gate reverse-bias actually varies along the gate perimeter. The general
shape of the depleted region in the earlier illustration is not accidental. It is intended to reflect the
increasing junction reverse-bias voltage, and the consequent increasing depletion region width, moving
from the source towards the drain. In addition of course the reverse-bias changes as the drain-source
voltage changes, and so there is an influence of the drain-source voltage on the resistance of the
channel. In this respect make careful note of the fact that the junction voltage is not the same as the
gate-source voltage; it is the channel and not the source terminal that forms one side of the junction. As
already noted because of the voltage variation along the channel the width of the depletion region
varies along the channel, being larger at the drain end of the channel. And moreover the depletion
region width changes as the drain-source voltage changes. Indeed, as the drain-source voltage increases
(for an N channel device) the reverse bias across the junction increases and the channel carries less
current for a given voltage than it would otherwise. The drain characteristics viewed over larger range of
drain-source voltage than before appear (roughly) as shown to the right.
As the drain-source voltage increases further a condition known colloquially as ‘pinch-off’ occurs; this is
the condition wherein (theoretically) the depletion region extends entirely across the channel. This
occurs initially at the drain end of the channel since that is where the depletion width always is widest.
When pinch-off occurs there is a junction depletion region between the drain and the source end of the
channel. Further increases in drain source voltage are taken up primarily by depletion-width changes in
this junction region, with only second-order effects on overall channel conduction thereafter.
Modulation' effect is considered further later. The channel current is (to first-order) fixed by the
conditions when pinch-off occurs; all carriers forming the source-end current are swept across pinch-off
junction region by the strong electric field. This is (roughly) similar to the carrier injection through the
base of a BJT, although the mechanism of carrier injection is different. A still more extended range of
variation of the drain characteristics is sketched to the right. The voltage controlled (VCR) region, i.e.,
operation before pinch-off, is conventionally called (mostly) just that, i.e., VCR region.
The ‘constant’ current (pinch-off) region to the right is ‘saturation’ (probably all the remarks respecting a
conflict with BJT terminology already have been said, repeatedly).
To summarize: the JFET carrier-transport channel conductivity is modified by the electric field associated
with the depletion region of a reverse-biased junction which extends into the channel. The nature of the
control process is such that the ability of the channel to carry current is greatest when the control
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junction has zero bias (or slightly positive, but well below the diode 'knee') and decreases with
increasing reverse bias. A JFET thus inherently is a device that is 'full on 'with no control exerted, and is
turned off with increasing reverse bias. This is 'depletion-mode' operation, so-called after the nature of
the physical process through which control is exerted. The details of the physics underlying the terminal
behavior are complex. However it is the terminal behavior and not a quantitative physical explanation
for that behavior that is the principal concern here. An exact form of a theoretical expression for a drain
characteristic depends on details of both geometry and doping. However various theoretical
expressions, despite major differences in mathematical appearance, actually produce very similar
numerical characteristics. Thus we describe a commonly used ‘working’ expression, a quadratic firstorder approximation for a drain characteristic in the VCR region of operation, which has the advantage
of relative simplicity and adequacy for initial design purposes. This working expression is the quadratic
equation:
VP is the ‘pinch-off’ voltage, i.e., the gate-to-drain voltage at which the channel first becomes pinched.
'Pinch-off' is defined as the point where maximum drain current (for a given gate voltage) occurs; the
current is assumed to remain substantially unaffected by the drain voltage thereafter. Differentiate the
expression to determine that the drain-source voltage at which pinch-off occurs is VDS = -VP + VGS; note
(for a N-channel device) that -VP is positive, that VGS is negative, that 0 VGS VP, and because of all
this that VDS 0 at pinch-off! As the expression indicates the drain current ID is zero for VDS = 0
whatever the gate bias. This is notably different from the BJT, where there is a small (mill volts)
collector-emitter voltage for zero collector current, and zero offset can be an advantage in applications
where the JFET is used as an analog switch.The maximum current for a given gate bias occurs at VDS
=VGS -VP, i.e., at pinch-off, and is given by the first-order expression
This latter quadratic expression is the locus of the pinch-off points on the common source (ID vs. VDS,
with VGS as a parameter) characteristics. The theoretical equations are described graphically in the
figure following. The drain current follows the quadratic expression up to its apex (i.e., over the VCR
range), at which point pinch-off occurs and the drain current then remains roughly constant into the
saturation range.
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The quadratic pinch-off characteristic, i.e., the locus of the drain current at pinch-off for different gatesource voltages also is drawn on the figure.
Straightforward calculation shows that the extension of the tangent at the origin to the pinch-off current
level intersects that current where VDS equals half the pinch-off voltage, i.e., (VP+VGS)/2. The actual
current at this voltage is 3/4 the pinch-off current. The tangent line from the origin and the saturation
current provide convenient asymptotes with which to sketch a characteristic fairly accurately; note
again that the actual current is 3/4 that at the intersection of the asymptotes.
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Table 1
Drain Current Id ( in mA)
S.no. Vds (in V)
Vgs =0V
Vgs= -1 V
Vgs= -2V
Vgs= -3 V
1
2
3
4
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5
6
Table 2
Drain Current Id ( in mA)
S.no. Vgs (in V)
Vds = 20 V
Vds = 16 V
Vds = 12 v
Vds = 8V
1
2
3
4
5
6
Result:
1 .The drain characteristics of the FET are plotted on the graph.
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Experiment No. -4
Object :
Study RC coupled amplifier and plot the frequency response.
Apparatus Required:
S.No. Name of Instruments/Kit
Specifications
Quantity
1.
RC Coupled Amplifier Trainer kit
ETB-45
01
2.
Cathode Ray Oscilloscope
30 MHz
01
3.
Function Generator
30 MHz
01
4.
BNC Cable
75 Ω
03
5.
Patch Chords
Banana Pin
05
Theory:
(a)
Frequency Response: The voltage gain of amplifier base varies with frequency the curve
between voltage gain and signal frequency of an amplifier is known as frequency response.
The gain of the amplifier increases from 0 till it became maximum at Fr called resonance
frequency is the frequency increases beyond fr the gain decreased.
(b)
Bandwidth : The range of the frequency over with the gain is equal to or greater than 70.7%
of the maximum gain is known as bandwidth from the figure it is clear that f1 – f2 is
bandwidth f1 is the lower cutoff frequency and f2 is the higher cutoff frequency. The
frequency f1 and f2 is also called 3DB frequency or half power frequency.
R – C Coupled Amplifier:
It is the most popular type of coupling dives use for the voltage amplification in figure it is seems
that a coupling capacitor Cc is used to connect the output of the first stage to the input of the second
stage. Resistance R1, R2 and RE used for the biasing and stability.
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When an AC signal i9s apply to the bias of the first transistor it amplify across the load RC this
amplified signal is faid to the bias of the second stage through CC in this way we get the overall signal
increase at the output of the second stage.
Frequency Response of RC Coupled Amplifier:
(i)
At the lower frequency (<50 Hz) the reactance of CC is very high hence very small part of the
signal will pass from one stage to another stage.
(ii)
At high frequency (>20 kHz) the reactance of CC is very small and it behave the short circuit
thus because of the loading effect reduce the voltage gain.
(iii)
At mid frequency (50 to 20 KHz) the voltage gain of amplifier is constant the effect of the CC
in this frequency range is such as to mention uniforms voltage gain.
Procedure :
(1)
Take the frequency response of the individual stage.
(2)
Measure the output of the first stage at point A.
(3)
Measure the output of the second stage at point B.
(4)
Draw the frequency response of the R – C coupled amplifier.
Observation Table :
S.No.
Fin (Hz)
Vin (Volts)
Vout (Volts)
Gain (dB) = 20 log10 (Vout/Vin)
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EXPERIMENT NO.- 5
Object: To study the phase shift audio oscillator.
Apparatus Required:
S.No. Name of Instruments/Kit
Specifications
Quantity
6.
RC Phase Shift Oscillator kit
ETB-24
01
7.
Cathode Ray Oscilloscope
30 MHz
01
8.
BNC Cable
75 Ω
01
9.
Patch Chords
Banana Pin
06
Theory:
Figure 1
The phase shift oscillator exemplifies all the oscillator principles discussed so far.fig shows a common
emitter transistor amplifier stage. This stage introduces a 180* phase shift to the signal applied to its
input.
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Thus the RC phase shift network as shown in fig must provide additional 180* phase shift to
make an oscillator.
Let us study the phase shift provided by a CR circuit of fig. consider a current I to flow through both R
and C. than using I as the reference vector, V0 is in phase with I while Vc the voltage across the capacitor
is 90* behind I, but Vi is the sum of Vc and V0 hence Vo is θ degrees ahead of Vi and represents a phase
shift of θ degree as shown in fig
Procedure:
1. Trace the circuit according to practical circuit diagram shown on the panel.
2. Observe the waveform by CRO.
Observation Table:
Calculated Value
S.No.
Value of Capacitor
(pf)
f 
1
2 6CR
Observed Frequency by
CRO
(Hz)
(Hz)
1.
1000 pf
2.
3300 pf
3.
6800 pf
RESULT:
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Experiment No.6
Object:
To study PN diode positive clipper circuit.
Apparatus required:
Bread board, function generator, CRO, two resistances, diode, connecting wires, patch cords.
Theory:
A wave shaping circuit which controls the shape of output waveform by removing or clipping a
portion of the applied wave is known as clipping circuit. For a clipping circuit at least two componts a
diode (which acts as a closed switch when forward wise and an open circuit when reverse biased) and a
resistor are required. Some time a DC battery is also used to fix the clipping level. Clippers are used in
radar, digital and other electronics devices.
Positive clipper:
The clipper which removes the positive half cycle of the input voltage is known as positive
clipper.
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Wiring diagram for positive clipper:
Input waveform:
1. Sinusoidal waveform
2. triangular waveform
3. square waveform
Observation:
Input waveform
Output waveform
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Input waveform:
Frequency
Voltage
Working:
When the positive half cycle of the signal voltage is applied to the clipper is when A is +Ve with
respect to B, the diode D is forward biased. Hence it acts like a closed switch (or short) & conducts
heavily. Therefore the voltage drop across the diode or across the load resistor RL is zero as is obvious
from the output waveform. In the negative half cycle of the signal voltage ie. When B is +Ve with respect
to a, the diode D is reverse biased. Hence it acts like an open switch consequently the entire input
voltage appears across the diode or across the load resistance RL. Actually the circuit behaves as voltage
divider with an output of.
Output voltage = RL / R+RL * Vm = -Vm when RL»R
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In this way the +Ve cycles of the signal voltage has been removed and the circuit is called as
+Ve clipper.
Procedure:
1. Make circuit connections according to the given diagram on the breadboard.
2. Provide input from the function generator on the CRO.
3. Observe the output waveform on the CRO.
Result:
We have observed the different output waveforms of positive clipper circuit.
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Experiment No.7
UJT
Object:
To plot the characteristics of UJT (2N 2446) and to determine the intrinsic standoff ratio from
the graph.
COMPONENTS AND EQUIPMENTS REQUIRED
1. UJT
2. Resistors
3. Voltmeter
4. Ammeter
5. Rheostat
6. Power supply
CIRCUIT DIAGRAM
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THEORY
UJT is the Uni-Junction Transistor. It is a three terminal device. They are: a) emitter b)
base1 c) base2.The equalent circuit is shown with the circuit diagram. So there are two resistors.
One is a variable resistor and other is a fixed resistor. The ratio of internal resistances is referred
as intrinsic standoff ratio (η).It is defined as the ratio of the variable resistance to the total
resistance. Due to the existing pn junction, there will be a voltage drop. If we apply a voltage to
the emitter, the device will not turn on until the input voltage is less than the drop across the
diode plus the drop at the variable resistance R1.When the device is turned on holes moves from
emitter to base resulting in a current flow. Due to this sudden increase in charge concentration in
base1 region conductivity increases. This causes a drop at base1.This region in the graph is
known as negative resistance region. If we further increase the emitter voltage the device
undergoes saturation. So a UJT has 3 operating regions:
1. cut off region
2. negative resistance region
3. saturation region
PROCEDURE
1. Set up the circuit as shown in the circuit diagram
2. Give the power supply.
3. By varying the input voltage, take the values of voltage and current values
4. Plot the graph
5. Find the in intrinsic standoff ratio from graph.
OBSERVATIONS
For VBB=12 V
VE
IE
for VBB=6 V
VE
IE
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GRAPH
CALCULATIONS
VBB=12 V
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VP= Vd + ηvbb
Find the value of Vp from graph.
η = Vp – Vd/VBB
Similarly find the value of intrinsic standoff ratio for all values of VBB.
RESULT
Characteristics of UJT were plotted and intrinsic standoff ratio was found.
η = ………………..
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EXPERIMENT -08
DIODE CLAMPER
OBJECT:-
1) Study of positive clamper.
2) Study of negative clamper.
APPARATUS REQUIERD:- Trainer kit, patch cords, CRO,multimeter etc.
THEORY:Clamping is a process of introducing a D C level into an A C Signal. A clamping circuit is
a device that place either the positive or negative peak of a signal at a desired level.
Positive Clamper:When a clamper shift the original signal in vertical upward direction in such a way that
the negative peak of the signal falls on the zero level, it is known as positive clamper.
Here we assume that diode is ideal i.e., it exhibits an arbitrarily sharp break at 0 volt
and that its forward resistance is zero. The I/P signal is sinusoidal which begins at t=0.
The capacitor is uncharged at t=0. Here our aim is to find the waveform of the O/P V0.
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(A) During the negative half cycle the diode D is forward biased and conducts heavily.
At the maximum negative peak of applied signal, the condenser is charged to Vm.
The 1 plate of the capacitor being at negative potential while plate 2 at positive
potential.
(B) Slightly beyond the negative peak, the diode stop conduction through it and
behaves as an open switch.
(C) During the positive half cycle, the diode D is reverse biased and does not conduct.
The capacitor charged to Vm behave as a battery and hence the output voltage Vo
is given by.
Vo = output voltage = Vm + Vi
= Vm + Vm
= 2Vm
According to the changes iv Vi, there would be corresponding changes in output
voltage. It is obvious that Vm+Vi Simply shift the input voltage upward by Vm. The
output is thus positively clamped voltage.
Negative clamper:-
When a clamper shift the original signal in vertical downward direction, it is known as
negative clamper.
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During the positive half cycle, diode D is forward biased and conducts heavily. At the
maximum positive peak of the applied signal, the condenser is charged to Vm. The
plate 1 of the capacitor is at positive potential while plate 2 is at negative potential.
It is obvious that the voltage across the capacitor opposes the I/P Voltage Vi. So the
O/P
voltage is given by.
Vo = Output Voltage = Vi – Vm
This is equivalent to subtract a constant voltage Vm from every point on the sinewave
of Vi over the full cycle.
PROCEDURE:1.
2.
3.
4.
Make the cinnection as shown in fig.1.
Connect the square wave the input of 10KHz.
Observe the output on CRO.
Change the connections as per fig.2 and observe the output.
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Experiment No. -9
Object:-
To study the RF oscillators using L-C Hartley Oscillator.
Apparatus Required:
S.No.
10.
11.
12.
13.
Name of Instruments/Kit
Hartley Oscillator Trainer kit
Cathode Ray Oscilloscope
BNC Cable
Patch Chords
Specifications
ETB-25
30 MHz
75 Ω
Banana Pin
HEATLEY OSCILLATOR:
Figure 2
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Quantity
01
01
01
08
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Above figure gives the circuit diagram of a heartily oscillator. The study component of the
collector current is stabiles by the potential divider method and, except of the components required for
stabilization, the circuit is similar to that of a value Hartley oscillator. The frequency determining section
L, C is connected between collector (anode) and base (grid). The emitter (cathode) is effectively
connected to the tapping point on the inductor because the impedance of the power supply can be
assumed to be negligible at the frequency of oscillation.
PROCEDURE:
1. Trace the circuit according to practical circuit diagram shown on the panel.
2. Connect B to D , D to L, C to F, F to H and E to K. now the circuit is same as shown in figure
3. Switch ON the supply provided on the left hand corner on the panel. Detect the oscillation on
Absorption CRO and measure the frequency of oscillation for different position of gang condenser in
degrees.
RESULT:
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Experiment No. -10
Object : To study the RF oscillators using LC Colpitt‘s Oscillator.
Apparatus Required:
S.No.
14.
15.
16.
17.
Name of Instruments/Kit
Colpitt‘s Oscillator Trainer kit
Cathode Ray Oscilloscope
BNC Cable
Patch Chords
Specifications
ETB-25
30 MHz
75 Ω
Banana Pin
Quantity
01
01
01
08
COLPITTS OSCILLATOR:
Above figure gives the circuit diagram of a Colpitts oscillator. Also stabilized divider method. The
three connections providing positive feedback are connected to the two ends, of the coil, and to the
junction of in this circuit C1 is in parallel with the output capacitance of the transistor and C2 is in
parallel with the input capacitance. Thus the transistor capacitances have an effect on the oscillation
frequency and if the capacitances change (for example due to a change in supply voltage or ambient
temperature) there is a corresponding change in the operating stability achieved, by making C1 and C2
large compared with the transistor capacitances. The Hartley and colpitts oscillators are very similar
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circuits, with just inductance and capacitance interchanged. Therefore the circuit determinant for
colpitts is identical to the determinant described for Hartley oscillator, except that for colpitts circuit
jxc1 and jxc2 must replace jxl1 and jxl2 and jxl must replace jxc
The A.C equivalent circuit of oscillator is drown in Fig. with common emitter h parameter. An
analysis similar to that made for the Hartley circuits result in, for the oscillating frequency of the colpitts
oscillator.
PROCEDURE:
3. Trace the circuit according to practical circuit diagram shown on the panel.
4. Connect A to D, D to L, N to B,C to F,F to J,and G to H. now the circuit is same as shown in Fig
switch ON the supply provided at the left hand corner on the panel. Detect the oscillation by
absorption CRO and measure the frequency of oscillation for different position of gang
condenser.
RESULT:
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