Download Minimization of Charge Sharing ~ Problems in Dynamic BiCMOS

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Minimization of Charge Sharing ~
Problems in Dynamic BiCMOS
Logic Circuits at Low Voltage
Prof S. N. Sharon'
Prof V.K. Pandey'
Anshuman Singh'
Introduction
Abstract
This paper presents the analysis of charge sharing
problems and its minimization at low voltage in
dynamic SiGMOS logic circuits. The two methods
have been proposed to reduce charge-sharing
problems. One of the methods employs a PMOS as
pre-discharge transistor and the other uses an NMOS
as pre-discharge transistor. The Simulation results
show that the two proposed methods minimize the
charge sharing problem completely. There is no drop
in output voltage, due to the charge sharing problem.
Keywords: Dynamic SiGMOS, SiPMOS pull-down,
Noise Margin, Racing, Gharge Sharing
I
n dynamic
SiCMOS
logic
circuits
charge
sharing problems at low voltage is quite different
from
that
in dynamic
CMOS.
For dynamic
SiCMOS two methods have been proposed to
reduce charge-sharing
methods
employs
problems.
One of the
a PMOS as pre-discharge
transistor and the other uses an NMOS as predischarge transistor.
The above two methods
minimize
the charge
sharing problem completely. There is no drop in
output voltage (Vout), due to the charge sharing
problem, in both the methods [1-3,12].
FULL
'Department of Electronics Engineering
Noida Institute of Engineering
&
Technology, Gr. Noida ,UP India
SWING
This 1.5V SiCMOS dynamic
Noida Institute of Engineering &
Technology, G,: Noida, UP India
feedback
transistor
Greater Noida Institute of Technology,
Gr. Noida,UP. India
is made of the
MP4, two control
MN1, MP3, CMOS NAND gate as
and the SiPMOS pull-down structure
containing
two input PMOS devices MP1 and
MP2. The operation can be explained as follows
[4-5].
During the precharge
'Deportmens of Electronics Engineering
LOGIC
logic circuit using
pull down" structure
PMOS precharge
transistors
of Electronics Engineering
BICMOS
CIRCUIT AT 1.SV
"SiPMOS
'Department
DYNAMIC
period, 'Clk' is pulled low
and the output is pulled high to VDO' At this time,
the bipolar device is turned OFF by MN1, which
is controlled by Vfb coming from the CMOS
NAND gate. In addition, MP3 is turned OFF. After
the precharge period, during the logic evaluationlLA::!:!:::::!~
Autumn 2010
period, both MP 4 and MN1 are turned OFF and
MP3 is ON. If both inputs ('A' and 'B') are low
(OV), the bipolar device (01) will be turned ON.
As a result, the output is pulled low to the ground
level. After the output is pulled down Vfb will
switch to high. Then, MN1 is turned ON and MP3
is turned OFF. As a result, the bipolar device is
turned OFF and no current flows in MP1, MP2
and MP3.
O~1~
vp
the V p node voltage will not drop below VTF~
since MP2 needs to maintain ON. If the parasitic
capacitances
at these
two nodes
are
comparable, the base voltage Vb may rise to
above 0.7V, thereby causing the bipolar device
01 to turn ON. Therefore, the output voltage will
be pulled down accidentally. Hence we can say
1~O~
vbt---t--i
Figure 1: Dynamic BiCMOS logic at 1.5V
During operation, the bipolar device 01 is ON
only during switching.
In addition a full swing of
1.5V at the output of the BiCMOS dynamic logic
gate can be obtained.
dynamic
When cascading
logic gate circuit
1.5V
functions
the
BiPMOS
pull-down
as a non-inverting
buffer.
structure
This
is
inherent advantage of using BiPMOS pull-down
structure in 1.5V BiCMOS dynamic logic circuit
[6-7].
CHARGE SHARING PROBLEMS IN DYNAMIC
BICMOS AT 1.5 V
As shown
in Figure 1, during
that the charge-sharing
problem in the 1.5V
BiCMOS dynamic logic circuit is due to the
charge redistribution between the Vb and the Vp
node [8-10].
MINIMIZATION
the precharge
period, the output node Vout is precharged to
high by precharge transistor MP4' as the 'Clk' is
low output of NAND gate Vfb is high which turns
NMOS transistor MN1 ON and hence causes the
CHARGE
SHARING
The charge sharing problems
in dynamic
BiCMOS at 1.5V occur because of charge
redistribution between Vp and Vb' which in turn
causes the base node voltage Vb to rise.
Therefore the charge sharing problems can be
minimized if we limit the Vp to a value lower than
VDD during precharge so that even after sharing
Vb does not reach VBE or if we do not allow node
voltage Vb to reach VBE during evaluate then in
that case BJT 01 will not turn ON thereby
erroneous pull down of Vout is avoided. This
gives rise to two methods for minimizing the
charge sharing
voltage (1.5V).
During this period the two input transistors MP1
and MP2 are assumed to be OFF ('A' = 1.5 V, 'B'
problems
in BiCMOS at low
PMOS Predischarge
bipolar transistor 01 to enter the cut-OFF mode.
= 1.5V).
OF
PROBLEM
with the
BiPMOS pull-down structure, no race problems
exist since
and Vout is already precharged to high, the
output of NAND gate goes low thereby causing
the PMOS MP3 to turn ON and as MP 1 is also ON
(since 'A' =OV), the parasitic capacitance at Vp
node is charged to 1.5V.
In the next logic evaluation period, if 'A' switches
to high (MP1 turns OFF) and 'B' switches to low
(MP2 turns ON), the charge at the Vp node will
redistribute with the parasitic capacitance at the
Vb node. Due to the threshold voltage of MP2,
o
BiCMOS
During the logic evaluation period, if 'B' remains
high (MP2 stays OFF) and 'A' switches from 1.5V
to OV (MP1 turns ON); the output node voltage
Vout should stay high since the bipolar transistor
01 is OFF. During this period, as the 'Clk' is high
•
NMOS Predischarge
•
PMOS PREDISCHARGE METHOD
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Imitating the CMOS solution to the charge
sharing problems a clock driven predischarge
PMOS device MP5 has been added between the
node Vp and Gnd in 1.5V BiCMOS dynamic
logic circuit as shown in Figure 2. Charge
sharing problems were occurring when 'A' was
changing from 0-> 1 and 'B' was making a
transition from 1->0. Here during first evaluation
when A='O' and B = '1' means MP1 is ON and
MP2 is OFF. Since during evaluation Vfb is low
hence MP3 is ON and this causes Vp to rise but
during second precharge when Vfb switches to
high, PMOS predischarge transistor MP5 turns
ON and Vp starts to decrease and Vp falls up to
VTP but not below it because further decrease
causes the MP5 to turn OFF hence preventing
further lowering of node voltage V p Now during
the second evaluation phase when 'A' switches
to 1 and 'B' switches to 0 means MP 1 is OFF and
MP2 is ON. The charge is redistributed between
Vp and Vb butthevoltage at node Vb cannot rise
above VTP/2, which is clearly less than VBEON
for. Hence Q1 does not turn ON and Vout is
maintained at VDD . Thus, charge-sharing
problems can be removed.
in the logic evaluation period if both 'A' and 'B'
switch to low. This is because during pull down
Vp and Vb both need to be charged upto VDD for
causing Q1 to enter into the saturation mode and
pull down of Vout' But with PMOS predischarge
method Vp is d,ischarged to VTP hence it takes
more time for V P to charge up to and hence pull
down is slower [11-12].
NMOS PREDISCHARGE
Here in NMOS predischarge
.minimizing the charge sharing
method
for
problems in
dynamic BiCMOS logic circuit at low voltage
(1.5V) an NMOS is connected between Vb and
Gnd with its gate connected to input 'A' as shown
in Figure3.
During first precharge
and feedback
Vout is precharged
to
Voo
signal Vfb is high thereby MN, is
turned ON which removes the base charge from
Q, and causes Q, to enter into the cut-OFF mode,
during this time MP3 is OFF. During evaluation, Vfb
goes low as both inputs of NAND gate; 'Clk' and
Vou, are high. This causes MP3 to turn ON. If
'A'='O' and 'B' = '1' means if MP, is ON and MP2
is OFF, then during evaluation Vp is charged to
Voo'
MN
1 r<>Il-----'
Figure 2: Dynamic BiCMOS logic circuit with
PMOS predischarge
However, as the input chain is long, many
precharge PMOS devices are required with their
gates connected
to 'Clk'; hence the area
requirement
is also increased, which may
suppress the basic advantage of BiCMOS. In
addition to this, a voltage VTP at the internal
node Vp may slow down the pull-down process
Figure 3: Dynamic
BiCMOS logic
circuit
with
NMOS predischarge
During second precharge, Vfbgoes high thereby
causing
MN, to turn ON and removing
base
charge from Q, and this again causes Q, to enter
11'T11"r""-'
into cut-OFF mode. If during second evaluation1LA.u...;;;;u
Autumn 2010
'A' switches to '1' and 'B' switches to '0' then
MP2 turns ON and MP1 turns OFF, as 'A' is '1' this
MN2 to turn ON.
are given in the last section from Figure 4 to
Figure 6. Figure 4 shows the results when the
output voltage VOU! of BiCMOS logic circuits at 1.5
Since MP2 is ON, it causes charge at Vp to be
V is decreased, due to charge sharing. Here the
shared between Vpand Vb' but since MN2 is ON it
VOU!decreases
discharges
sharing. This shows that the charge sharing
problems are worse in dynamic BiCMOS logic at
low voltage. Figure 5 shows the results for 1.5V
dynamic
BiCMOS
logic
with
PMOS
predischarge. It can be seen from the figure that
causes NMOS predischarge
Vb and hence does not allow Vb to
rise up to 0.7 V. Hence Q1 does not turn ON and
there is no erroneous
pull down of Vou" In this
way charge sharing problems are minimized.
In NMOS predischarge
method here as Vpis at ,
so when 'A'='B'=O the pull down
compared
with that in case
predischarge
method.
Moreover
number of inputs is increased, then
single NMOS transistor is required,
is faster as
of PMOS
when a
also only a
hence area
requirement is also less compared
predischarge method [13-16].
with PMOS
v.
SIMULATION
DISCUSSIONS
RESULTS
AND
up to 0.94 V due to charge
there is no drop in output voltage VOU!due to
charge sharing. Figure 6 shows the results for
the 1.5V dynamic
BiCMOS with NMOS
predischarge. Here also there is no decrease in
VOU!due to charge sharing. Both the methods
minimize
successfully
at 1.5V.
the
charge-sharing
problem
in dynamic BiCMOS logic circuits
Charge Sharing in 1.5V BiCMOS Dynamic logic
Circuit
All the simulations have been done using Tanner
EDA tool. This consists of three main parts: S-
1.5
Edit Design Capture, T-Spice version 7.0 Circuit
simulator and W-Edit Waveform viewer. The
schematics of circuits are drawn in S-Edit
Design Capture; this generates the netlist (spice
description) of the schematic. The generated
netlist is then used by T-Spice, which simulates
the design and W-Edit shows the resulting
waveforms.
1.0
05
0.0
Some of the parameters, which have been used
here in the simulations are as follows, i3F=200 is
forward current gain of NPN bipolar junction
transistor, AE =2J1*3.75J1 is the emitter area,
VTP=-0.3V is the threshold voltage of PMOS at
Vss=OV (source to body potential being zero)
and Similarly VTN =0.3V is threshold voltage of
1.0
Qj
_"jiG 0
NMOS at Vss=O V, !ox=225Ao is the gate oxide
thickness,
L=0.2J1 is channel
length for both
NMOS and PMOS. Load capacitance CL =0.2pF
is used for all the circuits.
Voo= 1.5V has been
taken for all dynamic low voltage logic circuits.
With the given parameters the simulations have
been done in T-Spice and the results obtained
Figure 4: Transient Response of Charge Sharing
in Dynamic BiCMOS
Dynamic BiCMOS Logic
Predischarge at 1.5V
Circuit
with PMOS
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VI. CONCLUSION
I 5
I5
The output voltage ( ) decreases below
to
1.0
charge
sharing,
hence
charge
1V due
sharing
problems are worse in dynamic BiCMOS logic at
05
low voltage (1.5V). The two methods proposed
to minimize
00
o
5
10
15
20
25__ )0
l5
40
45
50
55
M
dynamic
the charge
BiCMOS
sharing
logic
problems
circuits,
in
minimizes
charge sharing problem completely. There is no
drop in output voltage (Vout) , due to the charge
sharing problem, in both the methods.
DO
-
.
----
,
I
I
II
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