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The importance of pin slew rate and backdrive current when choosing a test system.
Decisions to buy test systems are often made on comparisons of digital pattern rates or voltage
swings of various hardware modules. However when considered in isolation these quoted figures
can give the wrong impression of system performance and it is essential to look at them along-side
other key parameters.
There are many parameters shown in a data sheet for a test system and they often require a deep
technical knowledge and time to understand the implications of the figures.
This article provides a brief explanation of the effect voltage swing, pin slew rate, source impedance
and backdrive current have on the digital pattern rate driven by a test system and the interaction
between them all.
How data rate is defined
For test systems a data rate is defined as the time taken to repeat a digital pattern driven from a test
channel. It is expressed in Hertz and best explained by reference to the diagram below.
Data rate
Repeated
pattern
(logic high)
Data rate
The effect of voltage swing on digital pattern rate
A key parameter which affects voltage swing and digital pattern rate is the slew rate of a test
channel. Slew rate is the rate at which a voltage can change and is usually quoted in Volts per micro
second (V/us).
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V
Slew rate
t
A typical slew rate is 200 V/us which gives us an indication of how quickly a voltage within the test
channel range can be reached. For example, a slew rate of 200 V/us can also be described as a signal
requiring 5ns for each volt of a transition.
If we now consider a 0v to 4V TTL level voltage transition driven from a tester with a slew rate of 200
V/us then this will take approximately 4 x 5ns = 20ns to reach the required level. There is a typical
spread in slew rate of +/-20% at the full voltage swing of a test channel and therefore for a -10V to
+10v swing this would require 2 x 10 x 5 x 1.2 = 120ns for the transition or 8.3MHz data rate.
However this does not allow for propagation time or settling time of the signal which can typically
add up to 40ns to the transition time. Therefore the realistic period for the signal is 120ns + 40ns =
160ns or 6.25MHz expressed as a data rate.
So a data sheet that specifies 25MHz with a slew rate of 200V/us and a voltage swing of +/-10V
clearly does not mean that all these parameters can be achieved at the same time:
25MHz is a period of 40ns and we need to drive a signal high or low in this time, excluding any
settling time of the signal, giving a maximum theoretical voltage transition of 8V not the 20V (+/10V) stated. Realistically to achieve a stable test signal and allow for settling time the period should
be increased to around 70ns to give a maximum voltage swing of 3.5V
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Maximum Pattern rate versus drive
transition
Pattern rate (MHz)
15
10
5
0
0
5
10
15
20
Drive transition (V)
The effect of backdrive current on digital pattern rate
Backdriving is a term used to describe the process by which a tester applies a digital signal to
overcome the quiescent logic state of a network.
Back driven
Device
Device
Under
Test
Test Channel
Back drive
Logic ‘0’,
Current flow
Logic ‘1’
Logic ‘0’
Back drive
Logic ‘1’,
Current flow
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The tester is effectively backdriving a network to achieve the required test condition and this
requires the tester to drive or sink current to the network. The backdrive signal needs to be carefully
controlled to make sure the device being backdriven is not damaged by the test process i.e. that any
heating effect can be dissipated safely, including any necessary cool-down period, or that the signal
does not overshoot or undershoot the power supply voltage of the device which can cause latch-up
and destroy the device. The safe limits for backdriving a device are generally accepted to be those
defined in the Defence Standard 00-53.
Assuming the test system fully complies with the safe backdriving conditions then a test signal can
be safely applied to the circuit.
There is a non-linear relationship between the amount of current needed to back-drive a network
and the settling time needed to reach the required voltage. For lower power logic such as CMOS
there is little effect. However for the higher power devices such as F series and ABT it can take 100’s
of ns to reach the required stable voltage. Therefore the pattern rate must be reduced in order to
provide repeatable tests.
This relationship is shown in the graph below:
Maximum pattern rate versus
backdrive current
Pattern Rate (MHz)
15
10
5
0
0
100
200
300
400
500
600
700
Backdrive current (mA)
The effect of source impedance on digital pattern rate
Source impedance is the parameter used to describe the impedance on the test channel. The greater
the current required from the test channel then the higher the internal voltage drop will be across
this impedance. If the source impedance of a test channel is specified for example at 8 ohms then a
backdrive current of 500mA will cause a 4V drop internally in the pin electronics. This means that if
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the circuit under test requires a 4V logic level at 500mA the tester will not be able to drive the
correct voltage over the duration of the test.
However, if we consider a test system with a source impedance of <2 ohms then for the same
conditions as above the internal voltage drop is < 1V allowing the correct test voltages to be attained
delivering consistent and reliable results.
This is shown in the graph below:
Output voltage (V)
Output voltage vs Back-drive current
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
PinPoint Alpha
Other tester
0
200
400
600
800
Backdrive current (mA)
Summary
Data Rate, slew rate, Backdrive current and Source impedance are all important characteristics to
consider when selecting a test system. However, it is also very important to understand the
relationship and interaction between these characteristics to appreciate the effect they have in the
practical world. Diagnosys is happy to support our clients in understanding the often intricate world
of Automatic Test Equipment so that they can make the correct choice for their needs.
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