Download Average Power Balancing Control of a STATCOM based on the

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10.1109/TIA.2014.2312618,IEEETransactionsonIndustryApplications
Average Power Balancing Control of a STATCOM
based on the Cascaded H-Bridge PWM Converter
with Star Configuration
Chia-tse Lee
Bo-siang Wang
Po-tai Cheng
Sheng-wan Chen
Hirofumi Akagi
Abstract—This paper presents the average power balancing
control method for the modular multilevel cascaded converter
based on single-star bridge cells in the static synchronous compensator applications. The proposed control method accomplishes
both the reactive power compensation and the dc bus voltages
balancing control even under grid voltage sags. The low voltage
ride-through capability of the proposed method will become more
and more important as more distributed generation resources are
integrated into the grid. Laboratory test results are provided to
validate the proposed average power balancing control method.
Index Terms—Modular Multilevel Cascaded Converter, STATCOM, Low-voltage ride-through.
I. I NTRODUCTION
Static synchronous compensator (STATCOM) has been
proven for its effectiveness in voltage control in the power
system. Multilevel converters are often adopted for implementing STATCOMs because of their effective utilization of
low voltage power semiconductor devices for high voltage
applications [1], [2]. For voltage regulation in the transmission or distribution system, cascaded H-bridge converters, or
modular multilevel cascaded converters (MMCCs) - single star
bridge cell (SSBC) [3] are the most suitable among various
topologies.
The voltage balancing control of each and every dc capacitor
is a very critical issue for MMCC-SSBCs. A hierarchical
voltage balancing control is developed in [4]. Three layers
of DC bus voltages control, namely the three-phase overall
balancing, the per-phase cluster balancing and the individual
balancing, are proposed. In [5], the voltage balancing is
accomplished by selecting appropriate redundant switching
vectors. This method achieves a fast regulation of all the dc
bus voltages. However, the switching vectors increases as the
S. Chou, J. Huang and P. Barbosa are with Delta Electronics, Inc., Taiwan
(e-mail: [email protected]).
C. Lee is with the Coast Guard Administration of Taiwan (e-mail: [email protected]).
B. Wang is with ASUSTeK Computer Inc., Taiwan (e-mail:
[email protected]).
S. Chen is with Foxconn Electronics Inc., Taiwan (e-mail: [email protected]).
P. Cheng is with Center for Advanced Power Technologies, Department
of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan
(e-mail: [email protected]).
H. Akagi is with Department of Electrical and Electronic Engineering,
Tokyo Institute of Technology, Tokyo, Japan (e-mail: [email protected]).
The authors would like to thank Delta Electronics, Inc. for their financial
supports in this research.
Shih-feng Chou
Peter Barbosa
Jun-lin Huang
number of levels goes up, which restricts the flexibility to
expand the system.
However, the low voltage ride-through issue, which is
becoming more and more important as the penetration of
distributed energy resources grows higher, is not addressed
in [4], [5], [6]. Operations of MMCC-SSBC under grid fault
are presented in [7]. The error of some DC link voltages may
reach 8%-10% depending on the fault types because unbalance
grid voltages are not taken into consideration in its control.
This paper proposes a new DC link voltages control method
for the MMCC-SSBC based STATCOM. This new method
utilizes both positive- and negative-sequence voltages and currents in its DC bus balancing control to enhance its operation
in the grid fault condition. Such low-voltage ride-through
capability will be an important feature for STATCOMs as
more distributed energy resources are integrated into the grid.
The proposed method adopts the hierarchical voltage balancing
control structure for its flexibility in expanding the number of
modules in the MMCC-SSBC STATCOM.
II. S YSTEM CONFIGURATION
Fig. 1 shows the system configuration of STATCOM based
on the cascaded H-bridge PWM converter with star configuration, which is also known as Modular Multilevel Cascaded
Converter with the configuration of Single-Star Bridge Cells
(MMCC-SSBC). A MMCC-SSBC is connected to the grid
through the AC output filter. In order to realize the feedback control, the converter’s output voltages (v sm , where
m = a, b, c), phase currents (i m , where m = a, b, c), and
dc bus voltages (v dcmn , where m = a, b, c and n = 1, 2, 3)
are processed by the signal conditioning and the analog-todigital (A/D) circuits. The PWM reference commands are
then induced by the proposed closed-loop controller, and
they are modulated with the phase-shifted PWM technique
to generate the converter’s gate signals [8], [9]. TABLE I lists
the corresponding system parameters.
III. O PERATION P RINCIPLE
Fig. 2 shows the control block diagram based on the
proposed Average Power Balancing (APB) control. Because
every bridge cell performs the single phase AC modulation
with the separated dc capacitors, the dc voltages contain the
double line frequency ripples. Fig. 3 shows the calculations
for feedback averaging values. While using these signals as
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3
im
Vdc
Vqp, Vdp, Vqn, Vdn
Pos. and Neg. sequence
component extraction
3
vsm
Overall DC
P
bus voltage TB 1/3
control
*
Vdc
Qavg
Clustered
Balancing
Control
Vdc
PCBa
Pa,avg
PCBb
Pb,avg
PCBc
Pc,avg
Vdcm 3
vdcmn
3N Feedback dc voltage 3N
Vdcmn
averaging calculations
Vdcm
Individual
Balancing
Control
Iqp* Pos. iαp*
qd
va,ref
p*
vα,ref
to iβp*
Average Id
αβ vb,ref
αβ
Current
Power
to
n*
n*
v
Balance Iq Neg. iα regulator vβ,ref
abc c,ref
Equation
qd
Idn* to iβn*
αβ
N
N
N
vIBan
vIBbn
vIBcn
N van,ref
N vbn,ref
1/N
N vcn,ref
vIBan
vIBbn
vIBcn
Fig. 2. The block diagram of the proposed APB control method for MMCC-SSBC.
vdcan
N
MAF
N
Vdcan
N
Vdcbn
N
Vdccn
O
ia
Controller
Cac
15
A/D
15
The a-phase cluster
9
Phase36 Gate 36
shifted
Driver
PWM
R
vsa
sensor
9
vdcmn
R
vsb
vsc
Lac
va
vdca1 Ca1
Lac
vb
va1
vdca2 Ca2
Cell a2
va2
vdca3 Ca3
Cell a3
va3
ic
R
Fig. 1. The system configuration of the STATCOM based on MMCC-SSBC.
TABLE I
S YSTEM HARDWARE PARAMETERS
AC filter capacitor
Nominal dc voltage
DC bus capacitor
Unit capacitance constant
Switching frequency
Sampling frequency
Switching dead time
Symbol
vs
QR
N
Lac
Cac
∗
Vdc
Cmn
H
fsw
fsp
Tdt
vdccn
N
N
MAF
MAF
Σ
1/N
Σ
1/N
Vdca
Vdcb
1/3
Vdc
Vdcc
Fig. 3. The calculations for feedback dc averaging values.
Lac
M
Variables
Line-to-line rms voltage
Rated reactive power
Cascaded cell number
AC filter inductor
vdcbn
1/N
vc
The b-phase cluster
vs
ib
The c-phase cluster
60Hz
Σ
Value
220(V)
1.0(kVAR)
3
6.8(mH)
5.30(%)
3.3(µF)
80.0(V)
840(µF)
24.2(msec)
2.0(kHz)
12.0(kHz)
1.0(µsec)
feedback information, these double line frequency ripples
are suppressed by moving averaging filters (MAF) [10]. The
feedback dc voltages (V dcmn ) are then derived and used to
calculate the averaged cluster dc voltages (V dcm ) and the
averaged overall dc voltage (V dc ).
As the voltage sag appears, the grid voltage may contain
positive-, negative-, and zero-sequence components. In the
discussed system shown as in Fig. 1, the node O and node
M are separated, and node M is floating because of the converter’s star configuration. Thus the zero-sequence component
of grid voltage does not affect the converter’s operation, so
only the positive- and negative-sequence components of grid
voltage are taken into account in converter’s control. As shown
in Fig. 2, the converter’s phase voltages (v sm ) are sensed to
extract their sequence components (V qp , Vdp , Vqn , Vdn ). Several
sequence component extraction methods have been discussed
in literatures [11]. In addition, the converter does not contain
any zero-sequence current because of the separation of node
O and node M . Therefore, the converter’s phase voltage and
current (vsm and im ) can be represented by the sequence
components as equation (1), where superscript p and n indicate
the positive- and negative-sequence components respectively.
ω indicates the fundamental frequency of grid voltage. Based
on these voltage and current definitions, the voltage balancing
control is proposed and explained as follows.
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⎡ ⎤ ⎡
1
vsa
⎣ vsb ⎦ = ⎢
⎣− 21
vsc
− 21
⎡ ⎤ ⎡
1
ia
⎣ ib ⎦ = ⎢
−
⎣ 21
ic
− 21
⎤
⎡
1
0√ cos ωt − sin ωt Vqn
cos ωt sin ωt Vqp
⎥ v
⎥
⎢
−√ 23 ⎦ α = ⎣− 21 −√ 23 ⎦
+
vβ
sin ωt cos ωt
− sin ωt cos ωt Vdp
Vdn
3
1
3
−
2
2
⎤
⎤
⎡ 2
0√ 1
0√ cos ωt − sin ωt Iqn
cos ωt sin ωt Iqp
⎥ i
⎥
⎢
−√ 23 ⎦ α = ⎣− 12 −√ 23 ⎦
+
iβ
sin ωt cos ωt
− sin ωt cos ωt Idp
Idn
3
1
3
−
2
2
2
0√
⎤
(1)
A. The proposed average power balancing control
The proposed average power balancing (APB) control can
accomplish the converter’s reactive power controls and regulate the cluster dc voltages even under the grid fault conditions.
These functionalities are achieved by managing the average
active power flow at each phase and the total reactive power
flow of the whole converter. In order to manage these power
flows, several key equations are analyzed and derived as first.
As mentioned previously, the average active power flow
at each phase and the overall reactive power flow are paid
attention, so the instantaneous active power at each phase and
the instantaneous reactive power of system are calculated as
follows [12],
pa = vsa · ia
pb = vsb · ib
pc = vsc · ic
3
q = (vα · iβ − vβ · iα )
2
(2)
In equation (2), the voltage and current can be replaced by
the definitions in equation (1). In addition, the instantaneous
active power at each phase (p a , pb , and pc ) contains the
average power and the double frequency power ripple. The
double line frequency reactive power ripple also occurs in the
instantaneous reactive power (q) as long as there is negativesequence component in system.
The main objective of proposed control method is to regulate three cluster dc voltages and to inject the required reactive
power into the grid. These can be achieved by managing the
average active power flow at each phase and the total reactive
power flow of system. By paying attention to the average
power flows in equation (2), the proposed APB equation is
derived as equation (3).
As Fig. 2 shows, the APB equation given in equation (3)
calculates the current commands to produce the demanded
power flows. Base on these relationships, the overall dc bus
voltage control, the clustered dc voltage balancing control, and
the average reactive power control are implemented to generate
the commands of average power flow for APB equations.
Fig. 4 shows the overall dc bus voltage control. This controller
uses the average value of all the feedback dc voltages (V dc )
to accomplish the regulation. The overall dc voltage error
is regulated by the proportional and integral (PI) controller,
and the output value is multiplied by the overall dc voltage
∗
) to derive the command of total power flow
command (V dc
(PT B ).
Fig. 4. Overall dc bus voltage control.
Clustered Balancing Control
Vdca
PCBa
KpCB
∫
KiCB
PI
Vdcb
PI
PCBb
Vdcc
PI
PCBc
Vdc
Fig. 5. Clustered dc bus voltage control.
The clustered dc voltage control is to regulate the average
dc bus voltages of each cluster (V dcm ) at the average value of
all the feedback dc voltages (V dc ). Fig. 5 shows the control
block diagram. The clustered voltage errors are regulated by
the PI controller, and then the output values are multiplied by
their clustered average dc bus voltages (V dcm ) to derive the
command of cluster power flows (P CBm ).
Note that the multiplications in Fig. 4 and Fig. 5 keep
the unit of control parameters in PI regulator (K pT B , KiT B ,
KpCB , and KiCB ) consistent with those in the literature
[4]. This helps in analyzing these control parameters. In the
implementation of proposed controller, these multiplications
can also be removed.
As long as the commands for total power flow and cluster
power flows are generated, the final commands for average
active power flows at each phase are determined as follows,
Pm,avg =
PT B
+ PCBm
3
(4)
In equation (4), the total power flow command is divided by 3.
This represents that the overall average active power is evenly
shared by three phases. This command ( PT3B ) is added to the
clustered voltage balancing command (P CBm ) to derive the
average active power command for each phase.
In addition to the average active power command, the
reactive power command (Q avg ) can be determined by the
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⎡
⎡
⎤
Iqp∗
⎢ I p∗ ⎥
⎢ dn∗ ⎥
⎣Iq ⎦
Idn∗
=
Vqp
Vqn
+
⎢ Vqp 2Vqn 2√3V n
d
⎢
⎢ 2p − 4n + √ 4 n
⎢ Vq
Vq
3Vd
⎣ 2 − 4 − 4
3V p
− 2d
Vdp
Vdn
2√ − 2
n
p
3Vq
Vd
Vn
+ 4d
2 + √4
n
3Vq
Vdp
Vdn
2 −
4p + 4
3Vq
2
Vqn
2
Vqn
2
Vqn
Vqp
+
2
2√
Vp
3V p
− 4q + √ 4 d
Vp
3V p
− 4q − 4 d
n
3V
− 2d
Clustered balancing control
Individual balancing control
Symbol
M AF
KpT B
KiT B
KpCB
KiCB
KIB
⎤−1
Vdp ⎥
⎥
4 ⎥
Vdp ⎥
⎦
4
⎡
⎤
Pa,avg
⎢ Pb,avg ⎥
⎢
⎥
⎣ Pc,avg ⎦
Qavg
Value
33points at 4kHz
0.4(A/V)
4.0(A/V·sec)
0.4(A/V)
4.0(A/V·sec)
2.0(V/V)
ia
Inductive 1kVAR
-600VAR / 10ms
higher level controller or the power system operator. Once
the average power commands (P a,avg , Pb,avg , Pc,avg , Qavg )
are determined, the positive- and negative-sequence current
commands can be calculated by using equation (3) and the
derived positive- and negative-sequence voltage components.
These voltage sequence components are obtained by the
positive- and negative-sequence extraction techniques [11].
The STATCOM system tracks these positive- and negativesequence current commands with inner-loop current regulator
to generate the PWM references (v m,ref ) for the reactive
power control, the overall dc bus voltage control, and the
clustered voltage balancing control.
(3)
vsa vsb vsc
TABLE II
C ONTROLLER PARAMETERS
Variables
Moving averaging filter
Overall dc bus voltage control
Vdn
2
Vdn
2
Vdp
Vdn
−
2√
2
3V p
+ √4 q +
3V p
− 4q +
3Vqn
2
ib
0V
20ms
0A
20ms
ic
0VAR 20ms
Q
200V
2A
1kVAR
Capacitive 1kVAR
Triggering signal
(a) Test waveforms of phase voltage and phase current
80V 20ms
10V
vdca1, vdca2
vdcc1, vdcc2
vdcb1, vdcb2
Inductive 1kVAR
-600VAR / 10ms
0VAR 20ms
Q
1kVAR
Capacitive 1kVAR
Triggering signal
B. The individual voltage balancing control
The individual voltage balancing control is to regulate the
dc bus voltage of each bridge cells (V dcmn ) at the average
cluster dc bus voltage (V dcm ). This is achieved by exchanging
energy among the bridge cells in the same phase [4]. In
order to accomplish this operation, the relative adjustments
among all the bridge cell’s PWM references are implemented
as equation (5).
As equation (5) shows, the individual dc voltage errors
(Vdcm − Vdcmn ) is used as an index to determine the adjustment amount of PWM reference. The component of sin ωt,
sin(ωt − 120o), and sin(ωt + 120o) ensures the adjustment to
be in-phase with the phase current, thus resulting in the energy
exchange among bridge cells. In the end, the PWM references
for the MMCC-SSBC (vmn,ref ) are generated by adding the
derived adjustment of PWM references (v IBmn ) to the PWM
references derived in Section III-A (v m,ref ).
IV. T EST RESULTS
The operation of STATCOM system with the proposed APB
control method is tested in the laboratory hardware test bench.
Circuit configuration is implemented as Fig. 1, where the
cascaded bridge cell number N = 3. This MMCC-SSBC is
regulated by the proposed control method shown in Fig. 2.
TABLE II shows the controller parameters used in these tests.
(b) Test waveforms of 6 dc bus voltage
Fig. 6. Hardware test results for the transition of STATCOM operation from
rated inductive 1 kVAR injection to capacitive 1 kVAR injection.
A. Hardware test for STATCOM operation
The proposed APB control method is confirmed with a
MMCC-SSBC hardware circuit, whose cascaded number N =
3. The hardware parameters and the control parameters are
the same as listed in TABLE I and TABLE II. Fig. 6 show
the transition of STATCOM operation from rated inductive
1 kVAR injection to capacitive 1 kVAR injection. As shown in
Fig. 6(a), the phase currents (i m ) lag the phase voltages (v sm )
90 degree in the inductive operation, and become 90 degree
leading in the capacitive operation. The transition speed of
reactive power commands is 600 VAR/10 ms. Fig. 6(b) shows
that the 6 dc bus voltages among the 9 bridge cells, and the dc
voltages are regulated at the same level even in the transient.
B. Hardware test for single-phase grid fault
Fig. 7 shows the test waveforms of capacitive VAR operation as the 30% a phase grid voltage sag (Type B defined
in [13]) occurs. Fig. 7(a) shows the waveform of converter’s
phase voltage and current, and it verifies that the phase current
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vIBan =
vIBbn =
vIBcn =
KIB · (Vdca − Vdcan ) · sin ωt
if Qavg > 0, inductive VAR,
(−1) · KIB · (Vdca − Vdcan ) · sin ωt if Qavg < 0, capacitive VAR.
KIB · (Vdcb − Vdcbn ) · sin(ωt − 120o)
if Qavg > 0, inductive VAR,
o
(−1) · KIB · (Vdcb − Vdcbn ) · sin(ωt − 120 ) if Qavg < 0, capacitive VAR.
(5)
KIB · (Vdcc − Vdccn ) · sin(ωt + 120o)
if Qavg > 0, inductive VAR,
o
(−1) · KIB · (Vdcc − Vdccn ) · sin(ωt + 120 ) if Qavg < 0, capacitive VAR.
is 90 degree leading with respect to the phase voltage. The
proposed method produces some certain amount of negativesequence current to maintain all the dc voltages, so the
unbalanced converter phase currents are also investigated in
Fig. 7(a) as a result. Fig. 7(b) shows the dc bus voltage
waveforms during all the voltage sag period. The proposed
APB control method regulates all the dc voltages at 80.0 V
even as in the grid fault situation, and their detailed waveform
in the transient is given in Fig. 7(c). The inductive VAR
injection is also tested with the same voltage sag, and the
test waveforms are given in Fig. 8.
In order to compare the effectiveness of the proposed
voltage balancing control during the grid fault, the method
presented in [4] is also tested. Fig. 9 shows the test results, and
the dc bus voltages deviate from each others during fault ridethrough operation. The proposed method in [4] implements
the cluster balancing control in the viewpoint of individual
phase, and the proportional gain adopted in this controller
affects the steady-state performance a lot. Thus the cluster
power flows can not be compensated as the negative-sequence
voltages are induced during the voltage sag situation.
vsa
ia
Normal
vsb vsc
0V
10ms
100V
0A
10ms
2A
ib ic
Fault ride-through
(a) Converter side phase voltage and phase current
vdcb1, vdcb2
80V 50ms
10V
vdca1, vdca2
vdcc1, vdcc2
C. Hardware test for two-phase grid fault
Fig. 10 and Fig. 11 shows the test waveforms of two-phase
grid fault, so vsm shown in Fig. 10(a) appears as the Type
E voltage sag, which is defined in [13]. As investigated in
Fig. 10(b) and Fig. 10(c), all the dc bus voltages are still
maintained at 80.0 V during the voltage sag. In order to
accomplish this voltage balancing control, the proposed APB
method produces some certain amount of negative-sequence
current to balance the average active power flows among
clusters, thus the unbalanced converter phase current can be
observed in Fig. 10(a). Fig. 12 is given to compare the voltage
balancing results. The results shown in Fig. 12 verify that dc
bus voltages deviate from each others, while the proposed APB
method can maintain all the dc bus voltages at the commanded
value even in the voltage sag conditions.
D. Hardware test for three-phase grid fault
Fig. 13 and Fig. 14 shows the test waveforms of threephase grid fault. As investigated in Fig. 13(b) and Fig. 13(c),
all the dc bus voltages are still maintained at 80.0 V during
the voltage sag. The method proposed in [4] is also tested
for symmetrical grid fault, and the test result given in Fig. 15
shows that the voltages balancing control can be still maintained in this case.
Normal
Fault ride-through
Normal
(b) DC voltages vdc
80V 50ms
80V 10ms
20V
10V
vdcc1, vdcc2
vdca1, vdca2
vdcb1, vdcb2
Normal
Fault ride-through
(c) Zoomed waveforms of DC voltages in the transient
Fig. 7. Experimental test waveforms of rated capacitive VAR operation with
the proposed APB control method as 30% one-phase voltage drop.
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vsa vsb
vsa v v
sb
sc
0V
ia
ib
ia ib
10ms
Normal
Fault ride-through
0V
10ms
100V
0A
10ms
2A
ic
2A
Fault ride-through
(a) Converter side phase voltage and phase current
(a) Converter side phase voltage and phase current
vdcb1, vdcb2
vdcb1, vdcb2
80V 50ms
10V
80V 50ms
vdca1, vdca2
vdcc1, vdcc2
Normal
vsc
100V
ic
0A
Normal
10ms
Fault ride-through
vdca1, vdca2
vdcc1, vdcc2
Normal
Normal
Fault ride-through
Normal
(b) DC voltages vdc
(b) DC voltages vdc
Fig. 8. Experimental test waveforms of rated inductive VAR operation with
the proposed APB control method as 30% one-phase voltage drop.
80V 50ms
80V 10ms
vdcb1, vdcb2
10V
vdcc1, vdcc2
80V 50ms
20V
10V
vdca1, vdca2
vdcc1, vdcc2
vdcb1, vdcb2
10V
vdca1, vdca2
Normal
Fault ride-through
(c) Zoomed waveforms of DC voltages in the transient
Normal
Fault ride-through
Fig. 10. Experimental test waveforms of rated capacitive VAR operation with
the proposed APB control method as 30% two-phase voltage drop.
Normal
(a) Rated capacitive VAR injection
vdcc1, vdcc2
vdcb1, vdcb2
80V 50ms
vdca1, vdca2
10V
The main difference between the proposed APB control
method and the reviewed method is verified by the test
results given in Section IV-B, Section IV-C, and Section IV-D.
Although both methods can maintain the dc voltages under the
symmetrical grid voltages, their performances under asymmetrical grid voltages are different. Therefore, the proposed
APB control method has better performance for the fault ridethrough operations.
V. C ONCLUSION
Normal
Fault ride-through
Normal
(b) Rated inductive VAR injection
Fig. 9. Experimental test waveforms with the voltage balancing control
proposed in [4] as 30% one-phase voltage drop at grid side.
This paper presents an average power balancing control for
reactive power injection and all the dc bus voltage balancing
of the MMCC-SSBC in the STATCOM application. The proposed method takes both the positive- and negative-sequence
components into account, thus all the dc bus voltage balancing
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vsa vsb
vsa vsb vsc
vsc
0V
ia ib
100V
ia
ic
0A
Normal
10ms
10ms
Normal
Fault ride-through
0A
10ms
2A
Fault ride-through
vdcb1, vdcb2
80V 50ms
10V
80V 50ms
10V
vdca1, vdca2
vdcc1, vdcc2
vdca1, vdca2
vdcc1, vdcc2
Normal
Normal
Fault ride-through
Normal
(b) DC voltages vdc
(b) DC voltages vdc
Fig. 11. Experimental test waveforms of rated inductive VAR operation with
the proposed APB control method as 30% two-phase voltage drop.
80V 50ms
80V 10ms
vdcc1, vdcc2
80V 50ms
vdca1, vdca2
100V
(a) Converter side phase voltage and phase current
vdcb1, vdcb2
Fault ride-through
10ms
ic
2A
(a) Converter side phase voltage and phase current
Normal
ib
0V
20V
10V
vdcc1, vdcc2
vdca1, vdca2
vdcb1, vdcb2
10V
vdcb1, vdcb2
Normal
Fault ride-through
(c) Zoomed waveforms of DC voltages in the transient
Normal
Fault ride-through
Fig. 13. Experimental test waveforms of rated capacitive VAR operation with
the proposed APB control method as 30% three-line voltage drop.
Normal
(a) Rated capacitive VAR injection
vdcc1, vdcc2
80V 50ms
vdca1, vdca2
10V
vdcb1, vdcb2
can be achieved no matter the grid voltage is balanced or
unbalanced. The details of proposed method is presented and
explained, and the experimental test results are also given to
validate the proposed method.
R EFERENCES
Normal
Fault ride-through
Normal
(b) Rated inductive VAR injection
Fig. 12. Experimental test waveforms with the voltage balancing control
proposed in [4] as 30% two-phase voltage drop.
[1] J. S. Lai and F. Z. Peng, “Multilevel converters-a new breed of power
converters,” IEEE Transactions on Industry Applications, vol. 32, no. 3,
pp. 509–517, May./Jun. 1996.
[2] J. Rodriguez, J. S. Lai, and F. Z. Peng, “Multilevel inverters: a survey of
topologies, controls, and applications,” IEEE Transactions on Industrial
Electronics, vol. 49, no. 4, pp. 724–738, Aug. 2002.
[3] H. Akagi, “Classification, terminology, and application of the modular
multilevel cascade converter (mmcc),” IEEE Transactions on Power
Electronics, vol. 26, no. 11, pp. 3119–3130, Nov. 2011.
0093-9994(c)2013IEEE.Personaluseispermitted,butrepublication/redistributionrequiresIEEEpermission.See
http://www.ieee.org/publications_standards/publications/rights/index.htmlformoreinformation.
Thisarticlehasbeenacceptedforpublicationinafutureissueofthisjournal,buthasnotbeenfullyedited.Contentmaychangepriortofinalpublication.Citationinformation:DOI
10.1109/TIA.2014.2312618,IEEETransactionsonIndustryApplications
vsa vsb vsc
ia
Normal
ib
0V
10ms
100V
0A
10ms
2A
ic
Fault ride-through
(a) Converter side phase voltage and phase current
vdcb1, vdcb2
80V 50ms
10V
vdca1, vdca2
vdcc1, vdcc2
Normal
Fault ride-through
Normal
(b) DC voltages vdc
[4] H. Akagi, S. Inoue, and T. Yoshii, “Control and performance of a
transformerless cascade pwm statcom with star configuration,” IEEE
Transactions on Industrial Applications, vol. 43, no. 4, pp. 1041–1050,
Jun./Aug. 2007.
[5] X. She, A. Q. Huang, and G. Wang, “3-d space modulation with voltage
balancing capability for a cascaded seven-level converter in a solid-state
transformer,” IEEE Transactions on Power Electronics, vol. 26, no. 12,
pp. 3778–3789, Dec. 2011.
[6] F. Z. Peng, J. S. Lai, J. McKeever, and J. VanCoevering, “A multilevel
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[7] J. Ota, Y. Shibano, and H. Akagi, “Low-voltage-ride-through (lvrt)
capability of a phase-shifted-pwm statcom using the modular multilevel
cascade converter based on single-star bridge-cells (mmcc-ssbc),” in
Proc. IEEE Energy Conversion Congress and Exposition (ECCE), 2013,
pp. 3062–3069.
[8] Y. Liang and C. O. Nwankpa, “A new type of statcom based on
cascading voltage-source inverters with phase-shifted unipolar spwm,”
IEEE Transactions on Industry Applications, vol. 35, no. 5, pp. 1118–
1123, Sept./Oct. 1999.
[9] D. G. Holmes and T. A. Lipo, Pulse Width Modulation for Power
Converters Principles and Practice. Wiley-IEEE Press.
[10] M. Hagiwara, R. Maeda, and H. Akagi, “Negative-sequence reactivepower control by a pwm statcom based on a modular multilevel cascade
converter (mmcc-sdbc),” IEEE Transactions on Industry Applications,
vol. 48, no. 2, pp. 720–729, Mar./Apr. 2012.
[11] R. Teodorescu, M. Liserre, and P. Rodriguez, Grid Converters for
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[13] M. H. J. Bollen, Understanding Power Quality Problems : voltage sags
and interruptions. Wiley-IEEE Press.
Fig. 14. Experimental test waveforms of rated inductive VAR operation with
the proposed APB control method as 30% three-line voltage drop.
vdcb1, vdcb2
80V 50ms
10V
Chia-tse Lee was born in Tainan, Taiwan in 1985.
He received the B.S. and Ph.D. degrees in electrical
engineering from National Tsing Hua University,
Hsinchu, Taiwan, in 2007 and 2013, respectively. He
is currently a second lieutenant at the Coast Guard
Administration of Taiwan.
He received the IEEE IAS Committee Second
Prize Paper Award in 2012. His current research
interests include high power converters and power
electronic technologies for smart grid and microgrid.
vdca1, vdca2 vdcc1, vdcc2
Normal
Fault ride-through
Normal
(a) Rated capacitive VAR injection
vdcc1, vdcc2
80V 50ms
vdca1, vdca2
10V
vdcb1, vdcb2
Bo-siang Wang was born in Tainan, Taiwan in 1989.
He received the B.S. degree from National Taiwan
University of Science and Technology, Taipei, Taiwan in 2011. He received the M.S. degree in electrical engineering from National Tsing Hua University,
Hsinchu, Taiwan in 2013. Since 2013, he has been
with ASUSTeK Computer Inc., Taiwan.
Normal
Fault ride-through
Normal
(b) Rated inductive VAR injection
Fig. 15. Experimental test waveforms with the voltage balancing control
proposed in [4] as 30% three-line voltage drop.
0093-9994(c)2013IEEE.Personaluseispermitted,butrepublication/redistributionrequiresIEEEpermission.See
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Sheng-wen Chen was born in Kaohsiung, Taiwan
in 1987. He received the B.S. and M.S. degrees
in electrical engineering from National Tsing Hua
University, Hsinchu, Taiwan, in 2010 and 2012,
respectively. He is currently an engineer in the Communication & Network Solution Business Group of
Foxconn Electronics. His research interests include
cascaded multilevel converters and the control of
power converters.
Shih-feng Chou was born in Taipei, Taiwan in 1987.
He received the B.S. and M.S. degrees in electrical
engineering from National Tsing Hua University,
Hsinchu, Taiwan, in 2009 and 2011, respectively.
Since 2012, he performs R&D in power electronics
for renewable energy systems at Delta Electronics.
Jun-lin Huang received the B.S. degree in electrical
engineering from the National Taipei University of
Technology, Taipei, Taiwan in 2009. He received
the M.S. degree in electrical engineering from the
National Tsing Hua University, Hsinchu, Taiwan in
2011.
His research interests include digital control of
multilevel converters, active power filter and static
var compensator. He is working in Delta Electronics.
Hirofumi Akagi (M’87-SM’94-F’96) was born in
Okayama, Japan, in 1951. He received the Ph. D.
degree in electrical engineering from Tokyo Institute of Technology, Tokyo, Japan, in 1979. He is
currently Professor in the department of electrical
and electronic engineering at Tokyo Institute of
Technology. Prior to it, he was with Nagaoka University of Technology, Nagaoka, Japan, and Okayama
University, Okayama, Japan.
His research interests include power conversion
systems and its applications to industry, transportation, and utility. He has authored and coauthored more than 110 IEEE
Transactions papers and two invited papers published in Proceedings of the
IEEE in 2001 and 2004. The total citation index for all his papers in Google
Scholar is more than 25 000 times.
He received six IEEE Transactions Prize Paper Awards and eleven IEEE
IAS Committee Prize Paper Awards. He is the recipient of the 2001 IEEE
William E. Newell Power Electronics Award, the 2004 IEEE IAS Outstanding
Achievement Award, the 2008 IEEE Richard H. Kaufmann Award, and the
2012 IEEE PES Nari Hingorani Custom Power Award.
Dr. Akagi served as the President of the IEEE Power Electronics Society
for 2007-2008. Since January 2014, he has been serving as the IEEE Division
II Director-Elect.
Peter Babosa (SM’06) received the Ph.D. degree
in 2002 from The Virginia Polytechnic Institute
and State University (Virginia Tech). From 2001 to
2003, he served as a Technical Coordinator for the
Center for Power Electronics Systems at Virginia
Tech. In 2003 he joined ABB Corporate Research
Switzerland as a Scientist where he also led the
Power Electronics and System Applications Group
from 2005 to 2007. At ABB, he developed innovative multilevel power converter concepts for high
power applications. Since 2008 he has been with
Delta Electronics, Taiwan, developing high efficiency telecom power supplies
and heading medium voltage drives product development. Dr. Barbosa has
extensive international experience in industry and is an Associate Editor of
the IEEE Transactions on Power Electronics.
Po-Tai Cheng (S’96-M’99-SM’09) received the
B.S. degree from National Chiao Tung University,
Hsinchu, Taiwan in 1990 and Ph.D. degree from
the University of Wisconsin, Madison, WI, USA in
1999.
He is currently a Professor in the Department of
Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan. He is an associate editor for
IEEE Transactions on Power Electronics and IEEE
Transactions on Industry Applications. His research
interests include power quality issues, high power
converters, power electronics technologies for smart grid and microgrid.
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