Download Lecture 7: Power Outline Power and Energy

Outline
‰ Power and Energy
‰ Dynamic Power
‰ Static Power
Lecture 7:
Power
CMOS VLSI Design 4th Ed.
7: Power
Power and Energy
Power in Circuit Elements
‰ Power is drawn from a voltage source attached to
the VDD p
pin(s)
( ) of a chip.
p
PVDD ( t ) = I DD ( t ) VDD
‰ Instantaneous Power: P(t ) = I (t )V (t )
‰ Energy:
PR ( t ) =
T
E = ∫ P (t )dt
0
‰ Average Power:
T
Pavg =
2
VR2 ( t )
= I R2 ( t ) R
R
∞
∞
0
0
EC = ∫ I ( t )V ( t ) dt = ∫ C
E 1
=
P (t )dt
T T ∫0
dV
V ( t ) dt
dt
VC
= C ∫ V ( t )dV = 12 CVC2
0
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Charging a Capacitor
Switching Waveforms
‰ When the gate output rises
– Energy stored in capacitor is
‰ Example: VDD = 1.0 V, CL = 150 fF, f = 1 GHz
2
EC = 12 CLVDD
– But energy drawn from the supply is
∞
∞
0
0
EVDD = ∫ I ( t )VDD dt = ∫ CL
= CLVDD
dV
VDD dt
dt
VDD
∫ dV = C V
2
L DD
0
– Half the energy from VDD is dissipated in the pMOS
transistor as heat
heat, other half stored in capacitor
‰ When the gate output falls
– Energy in capacitor is dumped to GND
– Dissipated as heat in the nMOS transistor
CMOS VLSI Design 4th Ed.
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Switching Power
‰ Suppose the system clock frequency = f
‰ Let fsw = αf, where α = activity factor
– If the signal is a clock, α = 1
– If the signal switches once per cycle, α = ½
1
= ∫ iDD (t )VDD dt
T 0
T
=
VDD
iDD (t ) dt
T ∫0
VDD
[Tfsw CVDD ]
T
= CVDD 2 f sw
=
6
Activity Factor
T
Pswitching
it hi
CMOS VLSI Design 4th Ed.
7: Power
‰ Dynamic power:
Pswitching = α CVDD 2 f
VDD
iDD(t)
fsw
C
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Short Circuit Current
Power Dissipation Sources
‰ When transistors switch, both nMOS and pMOS
networks may
y be momentarilyy ON at once
‰ Leads to a blip of “short circuit” current.
‰ < 10% of dynamic power if rise/fall times are
comparable for input and output
‰ We will generally ignore this component
‰ Ptotal = Pdynamic + Pstatic
‰ Dynamic power: Pdynamic = Pswitching + Pshortcircuit
– Switching load capacitances
– Short-circuit current
‰ Static power: Pstatic = (Isub + Igate + Ijunct + Icontention)VDD
– Subthreshold leakage
– Gate leakage
– Junction leakage
– Contention current
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CMOS VLSI Design 4th Ed.
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7: Power
Dynamic Power Example
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Solution
Clogic = ( 50 ×106 ) (12λ )( 0.025μ m / λ )(1.8 fF / μ m ) = 27 nF
‰ 1 billion transistor chip
– 50M logic
g transistors
• Average width: 12 λ
• Activity factor = 0.1
– 950M memory transistors
• Average width: 4 λ
• Activity factor = 0.02
– 1.0
1 0 V 65 nm process
– C = 1 fF/μm (gate) + 0.8 fF/μm (diffusion)
‰ Estimate dynamic power consumption @ 1 GHz.
Neglect wire capacitance and short-circuit current.
7: Power
CMOS VLSI Design 4th Ed.
Cmem = ( 950 ×106 ) ( 4λ )( 0.025μ m / λ )(1.8 fF / μ m ) = 171 nF
Pdynamic = ⎡⎣0.1Clogic + 0.02Cmem ⎤⎦ (1.0 ) (1.0 GHz ) = 6.1 W
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Dynamic Power Reduction
‰ Let Pi = Prob(node i = 1)
– Pi = 1
1-P
Pi
‰ αi = Pi * Pi
‰ Completely random data has P = 0.5 and α = 0.25
‰ Data is often not completely random
– e.g. upper bits of 64-bit words representing bank
account balances are usually 0
‰ Data propagating through ANDs and ORs has lower
activity factor
– Depends on design, but typically α ≈ 0.1
2
‰ Pswitchingg = α CVDD f
‰ Try to minimize:
– Activity factor
– Capacitance
– Supply voltage
– Frequency
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Activity Factor Estimation
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Switching Probability
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Example
‰ A 4-input AND is built out of two levels of gates
‰ Estimate the activity factor at each node if the inputs
have P = 0.5
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Clock Gating
Capacitance
‰ The best way to reduce the activity is to turn off the
clock to registers
g
in unused blocks
– Saves clock activity (α = 1)
– Eliminates all switching activity in the block
– Requires determining if block will be used
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CMOS VLSI Design 4th Ed.
‰ Gate capacitance
– Fewer stages of logic
– Small gate sizes
‰ Wire capacitance
– Good floorplanning to keep communicating
blocks close to each other
– Drive long wires with inverters or buffers rather
than
h complex
l gates
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Static Power
Voltage / Frequency
‰ Run each block at the lowest possible voltage and
frequency that meets performance requirements
‰ Voltage Domains
– Provide separate supplies to different blocks
– Level converters required when crossing
from low to high VDD domains
‰ Static power is consumed even when chip is
q
quiescent.
– Leakage draws power from nominally OFF
devices
– Ratioed circuits burn power in fight between ON
transistors
‰ Dynamic Voltage Scaling
– Adjust VDD and f according to
workload
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Static Power Example
Solution
‰ Revisit power estimation for 1 billion transistor chip
‰ Estimate static power consumption
– Subthreshold leakage
100 nA/μm
• Normal Vt:
10 nA/μm
• High Vt:
• High Vt used in all memories and in 95% of
logic gates
– Gate leakage
5 nA/μm
– Junction leakage
negligible
CMOS VLSI Design 4th Ed.
7: Power
Wnormal-Vt = ( 50 ×106 ) (12λ )( 0.025μ m / λ )( 0.05 ) = 0.75 ×106 μ m
Whigh-Vt = ⎡⎣( 50 ×106 ) (12λ )( 0.95 ) + ( 950 × 106 ) ( 4λ ) ⎤⎦ ( 0.025μ m / λ ) = 109.25 ×106 μ m
I sub = ⎡⎣Wnormal-Vt ×100 nA/μ m+Whigh-Vt ×10 nA/μ m ⎤⎦ / 2 = 584 mA
(
)
I gate = ⎡ Wnormal-Vt + Whigh-Vt × 5 nA/μ m ⎤ / 2 = 275 mA
⎣
⎦
Pstatic = ( 584 mA + 275 mA )(1.0 V ) = 859 mW
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CMOS VLSI Design 4th Ed.
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Subthreshold Leakage
‰ For Vds > 50 mV
I sub ≈ I off 10
Vgs +η (Vds −VDD ) − kγ Vsb
S
‰ Ioff = leakage at Vgs = 0, Vds = VDD
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Stack Effect
Typical values in 65 nm
Ioff = 100 nA/μm @ Vt = 0.3 V
Ioff = 10 nA/μm @ Vt = 0.4 V
Ioff = 1 nA/μm @ Vt = 0.5 V
η = 0.1
kγ = 0.1
S = 100 mV/decade
‰ Series OFF transistors have less leakage
– Vx > 0, so N2 has negative
g
Vgs
−Vx +η ( (VDD −Vx ) −VDD ) − kγ Vx
η (Vx −VDD )
S
I sub = I off 10 S
= I off 10
3 1444
424444
3
14
4244
N1
N2
ηVDD
Vx =
1 + 2η + kγ
I sub = I off 10
⎛ 1+η + kγ ⎞
−ηVDD ⎜
⎟
⎜ 1+ 2η + kγ ⎟
⎝
⎠
S
≈ I off 10
−ηVDD
S
– Leakage through 2-stack reduces ~10x
– Leakage through 3-stack reduces further
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Leakage Control
Gate Leakage
‰ Leakage and delay trade off
– Aim for low leakage
g in sleep
p and low delay
y in
active mode
‰ To reduce leakage:
– Increase Vt: multiple Vt
• Use low Vt only in critical circuits
– Increase Vs: stack effect
• Input
put vector
ecto co
control
t o in s
sleep
eep
– Decrease Vb
• Reverse body bias in sleep
• Or forward body bias in active mode
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CMOS VLSI Design 4th Ed.
‰ Extremely strong function of tox and Vgs
– Negligible for older processes
– Approaches subthreshold leakage at 65 nm and
below in some processes
‰ An order of magnitude less for pMOS than nMOS
‰ Control leakage in the process using tox > 10.5 Å
– High-k gate dielectrics help
– Some processes provide multiple tox
• e.g. thicker oxide for 3.3 V I/O transistors
‰ Control leakage in circuits by limiting VDD
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Power Gating
‰ Turn OFF power to blocks when they are idle to
save leakage
– Use virtual VDD (VDDV)
– Gate outputs to prevent
invalid logic levels to next block
‰ Voltage drop across sleep transistor degrades
performance during normal operation
– Size the transistor wide enough to minimize
impact
‰ Switching wide sleep transistor costs dynamic power
– Only justified when circuit sleeps long enough
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