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energies
Article
Simultaneous On-State Voltage and Bond-Wire
Resistance Monitoring of Silicon Carbide MOSFETs
Nick Baker *, Haoze Luo and Francesco Iannuzzo
Department of Energy Technology, Aalborg University, Aalborg 9220, Denmark; [email protected] (H.L.);
[email protected] (F.I.)
* Correspondence: [email protected]
Academic Editors: Alberto Castellazzi and Andrea Irace
Received: 12 January 2017; Accepted: 3 March 2017; Published: 18 March 2017
Abstract: In fast switching power semiconductors, the use of a fourth terminal to provide the
reference potential for the gate signal—known as a kelvin-source terminal—is becoming common.
The introduction of this terminal presents opportunities for condition monitoring systems. This article
demonstrates how the voltage between the kelvin-source and power-source can be used to specifically
monitor bond-wire degradation. Meanwhile, the drain to kelvin-source voltage can be monitored
to track defects in the semiconductor die or gate driver. Through an accelerated aging test on 20 A
Silicon Carbide Metal-Oxide-Semiconductor-Field-Effect Transistors (MOSFETs), it is shown that
there are opposing trends in the evolution of the on-state resistances of both the bond-wires and the
MOSFET die. In summary, after 50,000 temperature cycles, the resistance of the bond-wires increased
by up to 2 mΩ, while the on-state resistance of the MOSFET dies decreased by approximately 1 mΩ.
The conventional failure precursor (monitoring a single forward voltage) cannot distinguish between
semiconductor die or bond-wire degradation. Therefore, the ability to monitor both these parameters
due to the presence of an auxiliary-source terminal can provide more detailed information regarding
the aging process of a device.
Keywords: Silicon Carbide MOSFET; reliability; power semiconductors
1. Introduction—The Kelvin-Source Terminal
Faster switching semiconductors mean that the parasitic elements of packaging materials impact
semiconductor performance to a greater degree. This is particularly the case when utilizing wide
bandgap semiconductors, which can switch several hundred volts and several tens of amperes in a
few nanoseconds.
As a consequence of these switching speeds, the use of a fourth terminal known as a kelvin-source
(or emitter in insulated gate bipolar transistors, IGBTs) connection to provide the reference potential
for the gate control voltage is becoming more common. This technique essentially separates the current
path of the control signal and the path of the load current from drain to the source (or collector to
emitter in IGBTs).
Figure 1 demonstrates the above principle. In the traditional three-terminal arrangement
(Figure 1a), the fast drain current transient during switching causes a voltage drop across the common
parasitic inductance of the source bond-wires. This induced voltage is in opposition to the driving
voltage, and consequently slows down the switching transient and increases energy loss [1,2]. To avoid
the common source inductance, an additional terminal known as the kelvin-source is used, as shown
in Figure 1b.
It is the objective of this article to focus on how the kelvin-source terminal can also be utilised for
condition monitoring purposes. The article performs experiments on Silicon Carbide (SiC) MOSFETs,
Energies 2017, 10, 384; doi:10.3390/en10030384
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Energies 2017, 10, 384
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MOSFETs,
however
the samecan
principle
also be
Silicon
IGBTs that
provided
that theya
however the
same principle
also becan
applied
to applied
Silicon to
IGBTs
provided
they contain
contain
a
kelvin-emitter
terminal.
kelvin-emitter terminal.
(a)
(b)
Figure
Traditional
three-terminal
power semiconductor;
(b) four-terminal
power
Figure 1.1.(a) (a)
Traditional
three-terminal
power semiconductor;
(b) four-terminal
power semiconductor
semiconductor
containing
a
kelvin-source
terminal
for
the
gate
voltage
reference.
containing a kelvin-source terminal for the gate voltage reference.
2. Background: Reliability and Condition Monitoring of Power Semiconductors
2. Background: Reliability and Condition Monitoring of Power Semiconductors
The reliability of power semiconductor devices is an important issue, since their unexpected
The reliability of power semiconductor devices is an important issue, since their unexpected
failure can lead to significant downtime of power converters. This downtime can incur significant
failure can lead to significant downtime of power converters. This downtime can incur significant
economic costs in applications such as renewable power. Additionally, the economic costs of power
economic costs in applications such as renewable power. Additionally, the economic costs of power
device failures in applications such as military, aerospace, and transport can equal the total cost of
device failures in applications such as military, aerospace, and transport can equal the total cost of the
the entire system, as such failures can cause catastrophic and unrecoverable effects [3].
entire system, as such failures can cause catastrophic and unrecoverable effects [3].
If failures can be anticipated, the operation of a system can be halted before a catastrophic
If failures can be anticipated, the operation of a system can be halted before a catastrophic
breakdown occurs, or pre-emptive maintenance scheduled that reduces the total downtime of the
breakdown occurs, or pre-emptive maintenance scheduled that reduces the total downtime of the
system. Nevertheless, the anticipation of failures in power semiconductors is difficult.
system. Nevertheless, the anticipation of failures in power semiconductors is difficult.
Power semiconductor reliability is significantly influenced by junction temperature and
Power semiconductor reliability is significantly influenced by junction temperature and
temperature cycling conditions. Failure mechanisms are generally separated into two categories:
temperature cycling conditions. Failure mechanisms are generally separated into two categories:
die-related failure mechanisms and package-related failure mechanisms. Wu et al. [4] define
die-related failure mechanisms and package-related failure mechanisms. Wu et al. [4] define die-related
die-related failure mechanisms with two further groupings: short-circuit and open-circuit failures.
failure mechanisms with two further groupings: short-circuit and open-circuit failures.
On the topic of condition monitoring and failure prediction, the most studied failure
On the topic of condition monitoring and failure prediction, the most studied failure mechanisms
mechanisms appear to be associated with the packaging materials. Here, the failures are primarily
appear to be associated with the packaging materials. Here, the failures are primarily attributed to
attributed to the differences in the coefficients of thermal expansion of the various materials of the
the differences in the coefficients of thermal expansion of the various materials of the semiconductor
semiconductor die and package construction, combined with the temperature swings they experience
die and package construction, combined with the temperature swings they experience [5]. Repeated
[5]. Repeated thermal cycling then leads to thermo-mechanical stress that results in the gradual
thermal cycling then leads to thermo-mechanical stress that results in the gradual wear-out of the
wear-out of the packaging materials. The most pertinent issues are lift-off and cracking of the
packaging materials. The most pertinent issues are lift-off and cracking of the bond-wires that connect
bond-wires that connect the semiconductor die to the terminals of the power module, and fatigue in
the semiconductor die to the terminals of the power module, and fatigue in the solder joints which
the solder joints which reduces the effective area for heat to escape via conduction from the die through
reduces the effective area for heat to escape via conduction from the die through the baseplate [6].
the baseplate [6].
The development of condition monitoring systems for power semiconductor modules has been
The development of condition monitoring systems for power semiconductor modules has been
an active research area in the past decade [6–8]. The majority of research has focused on monitoring an
an active research area in the past decade [6–8]. The majority of research has focused on monitoring
electrical parameter that indicates degradation. Examples of the most commonly monitored parameters
an electrical parameter that indicates degradation. Examples of the most commonly monitored
are: the forward voltage in IGBTs (or the on-state resistance in MOSFETs) [9–11] and the evolution of a
parameters are: the forward voltage in IGBTs (or the on-state resistance in MOSFETs) [9–11] and the
module’s thermal resistance (Rth ) [12–16]. These parameters have been studied since the 1990s.
evolution of a module’s thermal resistance (Rth) [12–16]. These parameters have been studied since
While the above indicators readily observe degradation in laboratory conditions, they are
the 1990s.
ultimately influenced by numerous failure mechanisms. As such, it is challenging to incorporate
While the above indicators readily observe degradation in laboratory conditions, they are
them into real-world condition monitoring systems, since it is difficult to ascertain with a high degree
ultimately influenced by numerous failure mechanisms. As such, it is challenging to incorporate
of certainty whether a critical level of degradation is present. This is especially the case for the
them into real-world condition monitoring systems, since it is difficult to ascertain with a high
forward voltage of an IGBT or the on-resistance of a MOSFET, which is influenced by both die- and
degree of certainty whether a critical level of degradation is present. This is especially the case for
packaging-related failure mechanisms. The reason for this is shown in Figure 2a: any measurement of
the forward voltage of an IGBT or the on-resistance of a MOSFET, which is influenced by both dieand packaging-related failure mechanisms. The reason for this is shown in Figure 2a: any
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measurement
of across
the voltage
drop across
a MOSFET
or IGBT
includes
voltage
drop of both die
the
the
voltage drop
a MOSFET
or IGBT
includes the
voltage
drop ofthe
both
the semiconductor
semiconductor
die and
the bond-wires.
Therefore,
when observing
an increase
on-state
and
the bond-wires.
Therefore,
when observing
an increase
in the on-state
resistanceinofthe
a MOSFET
resistance
of a MOSFET
(e.g.,possible
as in Figure
2b), it what
is notthe
possible
determine
what the
cause is
(e.g.,
as in Figure
2b), it is not
to determine
cause istowithout
performing
additional
without performing
after-failure
analysis.additional after-failure analysis.
Evolution of Ron in SiC MOSFET
Relative Change in Ron (%)
160
140
120
100
80
60
40
0
250,000
500,000
750,000
1,000,000
Temperature Cycles
(a)
(b)
Figure 2.
2. (a)
(a) Measurement
Measurement of
of the
the voltage
voltage drop
drop across
across aa MOSFET;
MOSFET; (b)
(b) Evolution
Evolution of
of on-state
on-state resistance
resistance
Figure
(R
on) of a Silicon Carbide (SiC) MOSFET in TO-247 packaging during an accelerated aging test [17].
(Ron ) of a Silicon Carbide (SiC) MOSFET in TO-247 packaging during an accelerated aging test [17].
In fact, the forward voltage can be affected by several conditions: junction temperature, gate
In fact, the forward voltage can be affected by several conditions: junction temperature, gate
oxide integrity, bond-wire fatigue, surface metallization reconstruction, or a faulty gate driver. This
oxide integrity, bond-wire fatigue, surface metallization reconstruction, or a faulty gate driver. This is
is perhaps why there are a variety of aging trends reported in the literature when examining the
perhaps why there are a variety of aging trends reported in the literature when examining the forward
forward voltage of a device. For example, increases in the forward voltage in IGBTs of 5%, 7%, and
voltage of a device. For example, increases in the forward voltage in IGBTs of 5%, 7%, and 20% have
20% have been reported before module failure occurs [7,9,11,15]. At the same time, decreases of up
been reported before module failure occurs [7,9,11,15]. At the same time, decreases of up to 25% were
to 25% were present in other studies [7,16,18]. Data for MOSFETs are harder to compare since the
present in other studies [7,16,18]. Data for MOSFETs are harder to compare since the majority of
majority of reliability studies seem to be performed on IGBTs. However, increases in the region of
reliability studies seem to be performed on IGBTs. However, increases in the region of 40% to 60% can
40% to 60% can generally be seen in previous literature [17,19,20].
generally be seen in previous literature [17,19,20].
Although the forward voltage of a device is influenced by numerous degradation conditions, it is
Although the forward voltage of a device is influenced by numerous degradation conditions, it is
still an attractive parameter to monitor, since it is relatively easy to extract during power
still an attractive parameter to monitor, since it is relatively easy to extract during power semiconductor
semiconductor operation [21].
operation [21].
The pressing question, therefore, is: at which point does the monitored parameter reliably
The pressing question, therefore, is: at which point does the monitored parameter reliably
signify the end-of-life condition of the device, so that operation can be halted and a catastrophic
signify the end-of-life condition of the device, so that operation can be halted and a catastrophic
failure prevented?
failure prevented?
One tactic to simplify the process of determining when the forward voltage displays a critical
One tactic to simplify the process of determining when the forward voltage displays a critical
level of degradation would be to reduce the number of degradation conditions it is dependent on.
level of degradation would be to reduce the number of degradation conditions it is dependent on.
This is difficult in a traditional three-terminal device. However, for devices with an auxiliary-source
This is difficult in a traditional three-terminal device. However, for devices with an auxiliary-source
connection, this article will demonstrate a simple measurement circuit with which degradation in
connection, this article will demonstrate a simple measurement circuit with which degradation in the
the semiconductor and bond-wires can be monitored separately.
semiconductor and bond-wires can be monitored separately.
A review of past literature does not yield many results of past publications that have studied
A review of past literature does not yield many results of past publications that have studied
the use of the auxiliary-source (or emitter) connection for condition monitoring purposes. However,
the use of the auxiliary-source (or emitter) connection for condition monitoring purposes. However,
one study was performed by Farokhzad et al. in 1996 [22,23]. This study was performed on IGBTs,
one study was performed by Farokhzad et al. in 1996 [22,23]. This study was performed on IGBTs,
and an additional current source was used to inject a sensing current (independent of the load
and an additional current source was used to inject a sensing current (independent of the load current)
current) between the power-emitter and auxiliary-emitter. The key difference in this article is that the
between the power-emitter and auxiliary-emitter. The key difference in this article is that the resistance
resistance between the power-source and auxiliary-source is evaluated while the device is in the
between the power-source and auxiliary-source is evaluated while the device is in the on-state, and no
on-state, and no additional current source is used.
additional current source is used.
3. Results
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3. Results
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3.1. On-State Voltage Monitoring with Kelvin-Source Connection
3.1. On-State Voltage Monitoring with Kelvin-Source Connection
The principle of the on-state measurements in this article are shown in Figure 3. The kelvin-source
Theis principle
of the
on-state
measurements
in this article
are shownThe
in Figure
3. The
connection
used as the
ground
reference
for two voltage
measurements.
first measurement
kelvin-source connection is used as the ground reference for two voltage measurements. The first
is of the drain to kelvin-source voltage (VDS ). Here, the measurement circuitry from [17] is used,
measurement is of the drain to kelvin-source voltage (VDS). Here, the measurement circuitry from [17] is
which uses a blocking diode to protect the measurement amplifier circuit against high voltages when
used, which uses a blocking diode to protect the measurement amplifier circuit against high voltages
the MOSFET/IGBT
is in the
off-state.
TheThe
second
the
kelvin-source
to source
when the MOSFET/IGBT
is in
the off-state.
secondmeasurement—of
measurement—of the
kelvin-source
to source
voltage
(VSS )—uses
only
an an
LT1167
instrumentation
the high
voltage
(VSS)—uses
only
LT1167
instrumentationamplifier,
amplifier,since
sincethis
thisdoes
does not
not experience
experience the
voltage
the drain
terminal.
The outputs
the two
are connected
to a 14-bit
highofvoltage
of the
drain terminal.
The of
outputs
of amplifiers
the two amplifiers
are connected
to atwo-channel
14-bit
two-channel Analogue-to-Digital
Converter
(ADC):
anpresented
AD7367. The
presented measurement
circuit
Analogue-to-Digital
Converter (ADC):
an AD7367.
The
measurement
circuit can be
used for
can
be
used
for
both
high
and
low
side
switches.
both high and low side switches.
VDS Measurement Circuit [17]
(a)
(b)
Figure 3. (a) Schematic for online VSS and VDS measurements; (b) Photo of prototype measurement board.
Figure 3.
(a) Schematic for online VSS and VDS measurements; (b) Photo of prototype
measurement
As can beboard.
seen from Figure 3a, the VDS measurement covers only the voltage drop across the
semiconductor, while VSS measures the voltage drop solely across the bond-wires and the surface
metallization.
Therefore,
it would
logical
assume that a fault
in the
semiconductor
DS) would
As can be seen
from Figure
3a,bethe
VDStomeasurement
covers
only
the voltage (V
drop
across the
have
no
impact
on
V
SS
,
and
vice-versa.
We
conducted
two
experiments
to
test
this
hypothesis:
one
to
semiconductor, while VSS measures the voltage drop solely across the bond-wires and the surface
emulate
a
semiconductor
side-related
failure,
and
another
to
induce
a
bond-wire
failure.
metallization. Therefore, it would be logical to assume that a fault in the semiconductor (VDS ) would
The following experiments are performed on SiC MOSFETs, which were chosen purely because
have no impact
on VSS , and vice-versa. We conducted two experiments to test this hypothesis: one to
of the prevalence of a kelvin-source connection in these devices. It should be noted that the primary
emulate a semiconductor side-related failure, and another to induce a bond-wire failure.
objective of this article is to demonstrate a proof-of-concept that the described measurement circuit
Thethe
following
experiments
are performed
SiC MOSFETs,
whichseparately.
were chosen
purely the
because
has
ability to
monitor semiconductor
andon
bond-wire
degradation
Therefore,
of thearticle
prevalence
of
a
kelvin-source
connection
in
these
devices.
It
should
be
noted
that
the
primary
does not focus on the analysis of failure mechanisms specific to SiC devices—the experiments
objective
thisequally
article been
is to demonstrate
proof-of-concept
that the described measurement circuit has
couldofhave
performed on asilicon
IGBTs.
the ability to monitor semiconductor and bond-wire degradation separately. Therefore, the article does
3.2. Gate
Voltage of
Failure
not focus
on Driver
the analysis
failure mechanisms specific to SiC devices—the experiments could have
equally been
performed
on silicon
IGBTs.
The first
experiment
involved
the emulation of a gate driver failure. Here, the objective is to
induce a fault in the semiconductor side, while leaving the bond-wires in a healthy state.
3.2. Gate
Driver Voltage
Failure helped to verify that the measurements of both VDS and VSS could be
Additionally,
the experiment
performed in full switching conditions.
The first experiment involved the emulation of a gate driver failure. Here, the objective is to
To do this, we operated four 4L-TO247 packaged SiC MOSFET devices (Wolfspeed
induce a fault in the semiconductor side, while leaving the bond-wires in a healthy state. Additionally,
C3M0120100K, Cree Inc., Durham, NC, USA) in an H-Bridge inverter, and varied the gate driver
the experiment
helped to verify that the measurements of both VDS V.
and
V inverter
could had
be performed
in full
voltage from the recommended 15 V, to a “faulty” condition of 12
The SS
a switching
switching
conditions.
frequency
of 7.5 kHz, with the load current at a frequency of 4 Hz. The resistances of both the
To
do
this, and
we operated
fourdie
4L-TO247
packaged
devicesfor(Wolfspeed
C3M0120100K,
bond-wires
the MOSFET
(calculated
using VSSSiC
and MOSFET
VDS, respectively)
one device during
one
Creesinusoidal
Inc., Durham,
NC, are
USA)
in an
inverter,
the using
gate driver
from the
half-period
shown
in H-Bridge
Figure 4. The
currentand
wasvaried
measured
a LEM voltage
55-P current
transducer.15 V, to a “faulty” condition of 12 V. The inverter had a switching frequency of 7.5 kHz,
recommended
It cancurrent
be seen at
that
there was aof
large
variation
in the MOSFET
resistance
depending
on the
the gate
with the load
a frequency
4 Hz.
The resistances
of both
the bond-wires
and
MOSFET
voltage
used.
The
MOSFET
resistance
was
around
10
mΩ
higher
when
the
gate
voltage
was
lowered
to are
die (calculated using VSS and VDS , respectively) for one device during one sinusoidal half-period
12 V. This result is logical, as the reduction in gate voltage reduces the charge in the inversion layer,
shown in Figure 4. The current was measured using a LEM 55-P current transducer.
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It can be seen that there was a large variation in the MOSFET resistance depending on the gate
voltage used. The MOSFET resistance was around 10 mΩ higher when the gate voltage was lowered to
Energies 2017, 10, 384
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12 V. This result is logical, as the reduction in gate voltage reduces the charge in the inversion layer, and
the MOSFET
resistance
consequently
increased.
At the same
resistance
of theofbond-wires
and the
MOSFET is
resistance
is consequently
increased.
At thetime,
same the
time,
the resistance
the
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showed
no significant
changeto
with
to the gate voltage.
showedbond-wires
no significant
change
with respect
therespect
gate voltage.
and the MOSFET resistance is consequently increased. At the same time, the resistance of the
bond-wires showed no significant change with respect to the gate voltage.
(a)
(b)
Figure 4. (a) MOSFET and bond-wire resistances at different gate voltages for one sinusoidal
Figure 4. (a) MOSFET and bond-wire resistances at different gate voltages for one sinusoidal half-period
(a)
(b) VDS, while bond-wire
half-period in a single-phase
inverter. MOSFET resistance is calculated using
in a single-phase
calculated
using
VDS
, whileisbond-wire
resistance is
resistance isinverter.
calculatedMOSFET
using VSS; resistance
(b) H-bridgeisinverter
schematic
(red
MOSFET
the Device under
Figure 4. (a) MOSFET and bond-wire resistances at different gate voltages for one sinusoidal
calculated
using VSS ; (b) H-bridge inverter schematic (red MOSFET is the Device under Test).
Test).
3.3.
half-period in a single-phase inverter. MOSFET resistance is calculated using VDS, while bond-wire
resistance is calculated using VSS; (b) H-bridge inverter schematic (red MOSFET is the Device under
3.3. Accelerated
Aging Test with 20 A Silicon Carbide MOSFETs
Accelerated
Test).Aging Test with 20 A Silicon Carbide MOSFETs
The second experiment performed was an accelerated aging test of three 20 A SiC MOSFETs. The
The second experiment performed was an accelerated aging test of three 20 A SiC MOSFETs.
3.3.
Aging
witha20single
A Silicon
Carbidemodule
MOSFETs
threeAccelerated
MOSFETs
wereTest
from
six-pack
(Wolfspeed CCS020M12CM2, Cree Inc.,
The three
MOSFETs
wereThe
from
a single
six-pack
module
(Wolfspeed
CCS020M12CM2,
Cree Inc.,
Durham,
NC,
USA).
MOSFETs
were
aged
using
a
traditional
constant
power cycling
The second experiment performed was an accelerated aging test of
three 20current
A SiC MOSFETs.
The
Durham,
NC,
USA).
The MOSFETs
were aged
usingrepetitive
a traditional
constant
cycling
test,
test,
where
thermal
induced
through
self-heating
andcurrent
cooling power
phases.
The
three
MOSFETs
werefatigue
from is
a single
six-pack
module (Wolfspeed
CCS020M12CM2,
Cree Inc.,
where thermal
fatigue
is
induced
through
repetitive
self-heating
and
cooling
phases.
The
objective
for
objective
for
this
test
was
to
induce
bond-wire
degradation.
Durham, NC, USA). The MOSFETs were aged using a traditional constant current power cycling
5
displays
the
basic
schematic
for
the
test,
while
Table
1
shows
the
test
parameters.
A
this testtest,
wasFigure
to
induce
bond-wire
degradation.
where thermal fatigue is induced through repetitive self-heating and cooling phases. The
constant
current
ofthe
22.5
Atoisinduce
injected
sequentially
each MOSFET
a period
of 2test
s, with
a
objective
for
this test
was
bond-wire
Figure
5 displays
basic
schematic
fordegradation.
thethrough
test, while
Table 1forshows
the
parameters.
0.1 s Figure
overlap5time.
The temperature
of each MOSFET
was
monitored
using
optical
fibers
through the
displays
the
basic
schematic
for
the
test,
while
Table
1
shows
the
test
parameters.
A
A constant current of 22.5 A is injected sequentially through each MOSFET for a period of 2 s,
module dielectric
With
the
heatsink
temperature
set to
75 MOSFET
°C, the temperature
swing
for
the
constant
current
ofgel.
22.5
A istemperature
injected
sequentially
through
each
for a periodusing
of 2 s,optical
with
a fibers
with a 0.1
s overlap
time.
The
of each
MOSFET
was
monitored
hottest
MOSFET
was
around
75
°C,
with
a
maximum
temperature
of
160
°C.
0.1 s overlap time. The temperature of each MOSFET was monitored using optical
fibers
through
the
through the module dielectric gel. With the heatsink temperature set to 75 ◦ C, the temperature swing
module dielectric gel. With the heatsink temperature set to 75 °C, the temperature swing for the
◦ C, with a maximum temperature of 160 ◦ C.
for the hottest
MOSFET
was
around
75with
hottest MOSFET
was
around
75 °C,
a maximum temperature of 160 °C.
Figure 5. Setup for Power Cycling Test of three SiC MOSFETs.
Figure 5. Setup for Power Cycling Test of three SiC MOSFETs.
Figure
5. Setup for Power Cycling Test of three SiC MOSFETs.
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Table 1. Power Cycling Test Parameters.
Table 1. Power Cycling Test Parameters.
Parameter
Value
Table 1. Parameter
Power
Cycling Test Parameters.
Value
Current
Current
Heatsink
Temperature
Parameter
Heatsink Temperature
Minimum
Current
Minimum TTjj
Maximum TTjj
Heatsink Temperature
Maximum
Minimum
Tj
Pulse
Duration
(on)
Pulse Duration
(on)
Maximum
Tj
Pulse
Duration
(off)
Pulse
Duration
Pulse
Duration
(on) (off)
Temperature
Swing
(Coolest Chip)
Chip)
Pulse Duration
(off)(Coolest
Temperature
Swing
Temperature
Swing
(Hottest
Chip)
Temperature
SwingSwing
(Coolest
Chip) Chip)
Temperature
(Hottest
Temperature Swing (Hottest Chip)
22.5 A
A
22.5
75 °C
85A°C
°C
22.5
85
◦
75160
C °C
160
°C
85 ◦ C
2 ss
2
160 ◦4Cs
2 s4 s
60
°C
460
s °C
◦
75C°C
°C
6075
◦
75 °C
Value
75 C
All three
three MOSFETs
MOSFETs were
were monitored
monitored for
for V
VDS
DS and VSS using the previously described
All
and VSS using the previously described
measurement
board,
so
the
resistances
of
both
MOSFET
die and
and
the
bond-wires
could be
be calculated
calculated
All
three
MOSFETs
were
monitored
for
V
and
V
thethe
previously
described
measurement
DS
SS
measurement board, so the resistances of both MOSFET using
die
bond-wires
could
as
the so
testthe
progressed.
A
total
of 16
16 measurements
measurements
were made
made could
during
each
pulse,
with
board,
resistancesA
of total
both of
MOSFET
die and the were
bond-wires
beeach
calculated
as thewith
test
as
the
test
progressed.
during
22 ss pulse,
measurements
performed
every
15
min
throughout
the
duration
of
the
test.
Figure
6
displays
an
progressed. Aperformed
total of 16every
measurements
were made
eachof2the
s pulse,
with measurements
measurements
15 min throughout
theduring
duration
test. Figure
6 displays an
example from
from
MOSFET
of how
how the
thethe
measurements
enabled
the tracking
tracking
of resistances
resistances
due
to
performed
every
15 min 11throughout
duration of the
test. Figure
6 displays
an example
from
example
MOSFET
of
measurements
enabled
the
of
due
to
self-heating
during
the
2
s
pulse,
while
also
showing
how
the
resistances
evolved
as
the
number
of
MOSFET
1
of
how
the
measurements
enabled
the
tracking
of
resistances
due
to
self-heating
during
self-heating during the 2 s pulse, while also showing how the resistances evolved as the number of
temperature
cycles
increased.
From
this
figure, there
there
is already
already
clear contrast—the
contrast—the
MOSFET
the 2 s pulse,cycles
while also
showing
howthis
the figure,
resistances
evolved
as theaa number
of temperature
cycles
temperature
increased.
From
is
clear
MOSFET
resistance
appears
to
be
stable
throughout
the
test,
while
the
bond-wire
resistance
increases
by
increased.
From
this
figure,
there
is
already
a
clear
contrast—the
MOSFET
resistance
appears
be
resistance appears to be stable throughout the test, while the bond-wire resistance increasesto by
almost
50%.
stable throughout
the test, while the bond-wire resistance increases by almost 50%.
almost
50%.
(a)
(a)
(b)
(b)
Figure
6. (a)
MOSFET
resistance
throughout
the
current
pulse,
after
increasing numbers
numbers of
of
Figure 6.
(a) MOSFET
MOSFET resistance
resistance throughout
throughout the
the 222 sss current
current pulse,
pulse, after
after increasing
increasing
Figure
(a)
numbers of
temperature
cycles
throughout
the
power
cycling
test;
(b)
Bond-wire
resistance
throughout
the
2
temperature cycles
cycles throughout
throughout the power cycling test;
throughout the
the 22 sss
temperature
test; (b)
(b) Bond-wire
Bond-wire resistance
resistance throughout
current
pulse,
after
increasing
numbers
of
temperature
cycles
throughout
the
power
cycling
test.
currentpulse,
pulse,after
afterincreasing
increasingnumbers
numbersof
oftemperature
temperaturecycles
cyclesthroughout
throughoutthe
thepower
powercycling
cyclingtest.
test.
current
Figure 77 displays
displays the evolution
evolution of
of MOSFET
MOSFET and
and bond-wire
bond-wire resistances
resistances for
for all three
three devices.
devices. The
The
Figure
Figure 7 displaysthe
the evolution
of MOSFET
and bond-wire
resistances all
for all three
devices.
values on
on these
these graphs
graphs are
are taken
taken from
from the
the last
last measurement
measurement in
in the
the 22 ss pulse.
pulse. It
It is
is clear
clear that
that there
there are
are
values
The values
on these graphs
are taken from
the last measurement
in the 2 s pulse.
It is clear
that there
opposing
trends:
the
resistance
of
the
bond-wires
in
all
three
devices
increases
by
around
1.5
mΩ,
opposing
trends:
the the
resistance
of the
bond-wires
in in
allall
three
are opposing
trends:
resistance
of the
bond-wires
threedevices
devicesincreases
increasesby
byaround
around1.5
1.5 mΩ,
mΩ,
while
the
MOSFET
resistances
show
a
slight
decrease
of
up
to
1
mΩ.
while
while the
the MOSFET resistances show a slight decrease of up to 1 mΩ.
(a)
(a)
(b)
(b)
Figure 7. (a) Evolution of MOSFET resistances throughout the power cycling test; (b) Evolution of
Figure
Evolution
of
resistances throughout
the
Figure 7.
7. (a)
(a)
Evolutionthroughout
of MOSFET
MOSFET
throughout
the power
power cycling
cycling test;
test; (b)
(b) Evolution
Evolution of
of
bond-wire
resistances
theresistances
power cycling
test.
bond-wire
resistances
throughout
the
power
cycling
test.
bond-wire resistances throughout the power cycling test.
Energies 2017, 10, 384
7 of 8
MOSFET 1 showed the largest variation in both its MOSFET and bond-wire resistance.
Coincidently, MOSFET 1 also had the highest baseline MOSFET resistance of 135 mΩ, and thus
had the highest temperature swing. On the other hand, MOSFET 3 showed almost no change in
its MOSFET resistance; however, its bond-wire resistance showed an increase consistent with the
other two.
4. Conclusions
This article demonstrates a preliminary proof-of-concept for separate condition monitoring of
semiconductor and bond-wire degradation in devices with a kelvin-source (or emitter) terminal.
The article shows a simple measurement circuit that produces two output voltages that are dependent
on the condition of the semiconductor die and of the bond-wires. These output voltages are
demonstrated to be independent of each other. That is, a failure in the semiconductor side (e.g.,
gate driver failure) does not influence the signal for bond-wire status, while degradation in the
bond-wires does not influence the signal for semiconductor status. Therefore, the degradation in these
components can be monitored separately. The conventional failure precursor—to monitor a single
forward voltage—cannot distinguish between semiconductor die or bond-wire degradation.
Future work will include applying the measurement circuit to a statistically significant number of
devices, and using the data to more clearly specify critical levels of degradation. Therefore, the risk of
false positives when deciding when to halt device operation can be reduced. The method should also
be tested on power semiconductors with several semiconductor chips in parallel.
Author Contributions: Nick Baker conceived the measurement concept and also designed all measurement
circuitry and data acquisition. Nick Baker also wrote the paper. Francesco Iannuzzo and Haoze Luo provided the
current cycling test bench for accelerated aging of the MOSFET devices, including optical fibres for measuring
junction temperature.
Conflicts of Interest: The authors declare no conflict of interest.
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