Download Runtime Mechanisms for Leakage Current Reduction in CMOS VLSI

Runtime Mechanisms for Leakage Current
Reduction in CMOS VLSI Circuits
Afshin Abdollahi
University of
Southern
California
Farzan Fallah
Fujitsu
Laboratories of
America
Massoud Pedram
University of
Southern
California
Outline
•
•
•
•
•
•
Introduction
Leakage Reduction Techniques
Input Vector Control
Adding Control Points
Modifying Gates
Results
1
Introduction
Decrease in Transistor Size
Increase in Operation Frequency
Increase in Density
Increase in Dynamic Power
Decrease in Breakdown Voltage
Low Power Design
Low Supply Voltage
Maintaining
Performance
Low Threshold Voltage
I sub
High Leakage Current
qV
− DS


= K 1 − e kT

×e




q (VGS −VT +ηVDS )
nkT
Leakage Reduction Techniques
Power Supply Gating
Low Threshold
High Threshold
+ Huge reduction in
leakage current
SLEEP
Virtual
Vdd
Gate1
P
IN
Gate2
Gate3
- Reduced voltage swing
OUT
Virtual
Ground
N
Virtual
Ground
SLEEP
- Requires change in the
CMOS technology
process
- Lower circuit speed
SLEEP
- Reduced DC noise
margin
- Less effective as
technology scales down
2
Leakage Reduction Techniques
Dual and Variable Threshold Voltages
• Dual Threshold CMOS
. High-Threshold devices on non-critical paths
. Low-Threshold devices on critical paths
- Requires technology process modification
• Variable Threshold CMOS (VTCMOS)
. Dynamically change the substrate voltage to control the
leakage and speed
. Substrate voltage higher than Vdd (for P transistors)
. Substrate voltage lower than Gnd (for N transistors)
- Requires triple-well technology and additional power supply
- Performance penalty (delay of retrieving the substrate voltage)
- Less effective as technology scales down
Input Vector Control
Input Dependence of the Leakage Current
X0
X1
X0
X1
Technology: 0.18 micron
Supply Voltage = 1.5V
Threshold Voltage = 0.2V
X0 X1
Leakage
00
01
10
11
23.60 nA
47.15 nA
51.42 nA
82.94 nA
3
Input Vector Control
Minimum Leakage Vector Identification
Original
Circuit
Primary
Inputs
Internal
Signals
Primary
Outputs
Leakage
Computing
Circuit
Circuit
Leakage
<
Leakage
Level
1
Search for the minimum leakage level for which the above
Boolean network is satisfiable
Input Vector Control
Boolean Satisfiability Formulation
a0
b0
)
s0
s 0 = a 0 ⊕ b0
a0 b0 ⇒ s0
a0 b0
s0
clause
0 0
0
cl1 = a0 + b0 + s0
0 1
1
cl2 = a0 + b0 + s0
1 0
1
cl3 = a0 + b0 + s0
l = AND ( cl1 , cl 2 , cl 3 , cl 4 )
1 1
0
cl4 = a0 + b0 + s0
( s 0 = a 0 ⊕ b0 ) ⇔ (l = true )
a0 b0 + s0
a 0 + b0 + s 0
4
Input Vector Control
Leakage Computing
Xj0
0.18 micron
Xj1
VDD = 1.5V
VT = 0.2V
Xi0
Xi1
Xj
Leakage
00
23.60 nA
L00
01
51.42 nA
L01
10
47.15 nA
L10
11
82.94 nA
L11
D11j = X j 1 X
j0
-Quantize the leakage values to k levels:
D 00j = X
j1
X
j0
D 01j = X
j1
X
D10j = X
j0
j1
X
j0
Leakage ( X j ) = D L 00 + D L 01 + D L 10 + D L 11
j
00
j
01
j
10
j
11
Input Vector Control
Reducing Number of Additions
n
= LNAND = ∑ Leakage NAND ( X j )
Contribution of all NAND
gates to the total leakage
j =1
one bit m bits
L NAND =
n
n
n
n
j =1
j =1
j =1
j =1
∑ ( D00j L00 ) + ∑ ( D01j L01 ) + ∑ ( D10j L!0 ) + ∑ ( D11j L11 )
(n-1)m single-bit additions
log n bits
n
m bits
n
n
n
j =1
j =1
j =1
L NAND = ( ∑ D ) L00 + ( ∑ D00j ) L00 + ( ∑ D00j ) L00 + ( ∑ D11j ) L11
j =1
j
00
(n -1+ m log n) single-bit additions
5
Input Vector Control
Leakage Computing Circuit
X 10
1
D 00
X 11
L NAND
2-to-4
D111
2-to-4
X n1
L NAND ( 00 )
L00
decoder
X n0
decoder
Number of L00 appearances in the total leakage
D 00n
D11n
L NAND (11 )
L11
LOR
Total_Leakage
<
Leakage
Level
1
Input Vector Control
A Linear Search Algorithm for Minimum Leakage
Start
C = Trivial Upper Bound
on the leakage
MLV = {}
C = C-1
Generate Boolean
If
total_leakage < C – 1
clauses corresponding to
then total_leakage < C
total_leakage < C
Solve the resulting
satisfiability problem
Satisfiable?
MLV = satisfying vector
Yes
Stop
Minimum Leakage = C+1
No Min-Leakage Vector = MLV
6
Input Vector Control
Number of Instances
Comparing Maximum and Minimum Leakage Values
12
10
8
6
4
2
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Max/Min Leakage Ratio
Input Vector Control
Applying the Minimum Leakage Vector
Primary
Inputs
0
Min-Leakage
Vector
1
Circuit
sleep
Min-Leakage Input = 0
input
sleep
input’
Min-Leakage Input = 1
input
sleep
input’
sleep
input’
sleep
input’
0
input
0
input
1
0
1
1
7
Input Vector Control
Number of Instances
Leakage Power Reduction by Applying Min-Leakage Vector
14
12
10
8
6
4
2
0
10% 15% 20% 25% 30% 35% 40% 45% 50% 55%
Percentage of Energy Saving
Comparing minimum leakage with average leakage in the standby mode
Adding Control Points
Controllability of Internal Gates
sleep
Min-leakage input
1
0
8
Adding Control Points
sleep
X=0
sleep
X=1
Y=0
X=1
Y=1
X Y Parameters
X = 0 : No change
X = 1 : Multiplex with
optimum value
Y = 0 : Optimum
value = 0
Y = 1 : Optimum
value = 1
0
0
Leakage(MUX)Y=0
Leakage(MUX)Y=1
00
01
10
11
XY
L MUX 1
L'total
LMUX k
Ltotal
<
1
Leakage level
Adding Control Points
Power Reduction by Adding Control Points
Number of Instances
15
10
5
0
25% 30% 35% 40% 45% 50% 55% 60% 65% 70%
Percentage Energy Saving
9
Adding Control Points
Breakeven Time
Number of Instances
14
12
10
8
6
4
2
0
50
100 150 200 250 300 350 400 450 500
Minimum Cycles in Idle Mode
Modifying Gates
A)
B)
C)
P
in
P
out
in
out
N
in
g
P
out
in
N
in
g
X=1
sleep
sleep
N
out
sleep
X=0
out
in
Y=0
g
out
sleep
X=1
Y=1
10
Modifying Gates
Delay Calculation
in1
LeakageA
LeakageB
LeakageC
00
01
10
11
out
inm
Leakage arrival_time(in1)
delay(in1, out)
XY
MAX
arrival_time(out)
MAX
circuit_delay
arrival_time(inm)
DelayA
DelayB
DelayC
00
01
10
11
Delay
delay(inm, out)
arrival_time(PO1)
XY
arrival_time(POn)
Modifying Gates
Equivalent Boolean Network
Delay
Constraint
>
Delay
Computing
Circuit
XY
variables
Primary
Inputs
Original
Circuit
1
Internal
Signals
Leakage
Computing
Circuit
Leakage
Level
<
11
Modifying Gates
Energy Saving for Different Speed Degradations
40
0% speed degradation
Number of Instances
35
5% speed degradation
30
10% speed degradation
25
15% speed degradation
20
15
10
5
0
10%
20%
30%
40%
50%
60%
70%
Percentage Energy Saving
Modifying Gates
Runtime of the Algorithm
Number of Instances
25
Algorithm runtime for 32 quantized levels.
20
Algorithm runtime for 64 quantized levels.
15
10
5
0
1
2
3
4
5
6
7
8
9
10
Runtime (x1000 seconds)
12
Conclusions
• Two runtime mechanisms for reducing the leakage
current of a CMOS circuit are presented
– A "sleep" signal is used to shift in a new set of external
inputs and pre-selected internal signals into the circuit so as
to minimize the total leakage current in the circuit
– NMOS and PMOS transistors are added to some of the
gates in the circuit to increase the controllability of the
internal signals of the circuit and decrease the leakage
current of the gates using the "stack effect"
• Experimental results on the circuits in the MCNC91
benchmark suite demonstrate that it is possible to
reduce the leakage current by up to 70% in VLSI
circuits at the expense of a very small overhead.
13