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Electrical and Computer Engineering
Register Bank – A Design and Implementation Project
By Prawat Nagvajara
I. Design Specification
The design is a bank of four 4-bit registers which stores and displays data. It is common to
denote the content of a register with angle brackets, for example, <A> denotes the content of A
where A is a name for placeholder whether it is a variable in programming language which is
typically an address in the computer memory or a name for a hardware unit. The contents of the
registers are unsigned numbers, that is, 0 ≤ <Ri> ≤ 15, i = 0, 1, 2, 3. Each register has its own load
enable connected to a push button. The design uses 4 buttons total. The 4-bit data (not to
confused with the four registers) are the switches, for example, sw3, sw2, sw1, sw0. User can
load a 4-bit vector “<sw3> <sw2> <sw1> <sw0>” into any register selected. To emphasize the
“placeholder and name” or “box and pointer”, note that, the switches named sw3, …, sw0 have
the contents <sw3>, …, <sw0> each is one bit (character type) and a vector is a string of
characters (double quotation marks).
4-bit data (SW’s)
Registers
Multiplexer
<R3>
7-segment displays
for contents of
R3, R2, R1, R0
4-to-8
Decoder
<R2>
<R1>
<R0>
Fig. 1 Register Bank Data Path
Figure 1 shows a block diagram description of the data path (it does not include control signals
such as register enables, reset and clock signals). The frontend of the design involves diverting
data from single source to multiple destinations (de-multiplex). A shared set of parallel wires is
called a bus, in Fig. 1, the lingo is that the registers are on an input bus connected to the input
switches. The registers only load data from the bus they don’t drive the bus.
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The backend of the design displays the contents of the registers on seven-segment displays. The
design uses multiplexer to resolve data from the four registers. The output of the multiplexer is
the 4-bit content from one of the registers which gets decoded to an 8-bit data connected to an
8-bit bus. The four 7-segment display units are connected to this bus. A seven-segment display
has 8 inputs CA, CB, CC, CD, CE, CF, CG, DP, and an enable signal AN. The input CA, …, DP (DP
denotes decimal point) source the LED segments (on when they are zeros). The unit is on when
AN is a zero. The display shows one of the hexadecimal characters - 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, b,
C, d, E and F. according to the 4-to-8 decoder.
The design uses time-division multiplex for displaying the contents of the registers in a roundrobin fashion. Consider four time slots T0, T1, T2, T3 occurring in as a periodic events. During the
time slot Ti, 0 ≤ i ≤ 3, the controller (state machine) in the design selects Register i content. The
decoder output – the seven-segment display code, drives the bus, and during this interval Ti the
controller activates the display unit i and turns other units off. When the period of the round
robin is fast enough the four display units will appear as if they were on simultaneously,
however, with different characters displayed.
II. Design Stages
A design process commonly comprises of progressive stages and subcomponents according to
the design specification. A plausible design stages for the register bank are
1. Frontend – Selective load registers
2. Multiplexed Displays – Selectively displays a register content on a seven-segment
display
3. Time-Division Multiplex – Simultaneously displays the register contents on the sevensegment displays
4. Final Stage – Combine the frontend, the multiplexed displays and the time-division
multiplex.
2.1 Stage 1 Selectively Load
This stage simplifies the data sizes to 2-bit content for the registers which are displayed on the
LEDs for verification (testing). Figure 1 shows a block diagram of the selective-load design stage.
2-bit datum
from 2 switches
Load selects from
4 buttons
Four
Registers
2-bit
contents to
8 LEDs
2-bit Registers
Fig.1 Selective Load Functionality – Stage 1
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VHDL Code for Stage 1
Buttons Assignment on Basys3
A plausible buttons assignment for the load enables is the right button for Register 0, and going
clockwise the upper button for Register 1, the left button for Register 3 and the bottom button
for Register 3.
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2.2 Stage 2 Selectively display 2-bit characters (0, 1, 2 and 3) on seven-segment displays. Figure
2 shows a block diagram of this stage.
Four selects
from buttons
Display enables
Four 2-bit
vectors
from 8
switches
7-segment
displays
Z, 8-bit display data
Muxltiplexer and
2-to-8 encoder
Fig. 2 Selectable 2-bit Character Displays
Seven-Segment Displays
Fig. 3 Seven-Segment Display, Source Basys3 Reference Manual [1]
An individual display segment (Fig. 3) shows the Segments A, B, … , G, and DP (Decimal Point)
connections. For instance, to display a hexadecimal character ‘F’ assign Z <= “01110001”, this
activates segments A E F and G and disable segments B, C, D and DP. Note that Z(7) down to Z(0)
map to A down to DP. The LED segment emits light when the corresponding datum wire (blue in
Fig. 3) is pulled to ground (0V).
In this design stage the data are simplified to 2-bit vectors and they are decoded to the 8-bit
seven-segment data for ’0’, ‘1’, ‘2’ and ‘3’. This requires 2-to-8 decoder (see VHDL code below).
In the final full specification, Stage 4 the data are 4-bit vector, a 4-to-16 decoder maps 4-bit
vector to hexadecimal characters appear on the displays.
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All four segments get the same data CA down to DP, i.e., Z(7 downto 0). The signals AN3 down
to AN0 however individually enable the display units. They are connected to the base terminal
of pnp BJT transistors which operate as switches [2], [3] (see Fig. 4). The switches conduct
current when the base voltage is 0V. For instance, to activate the rightmost display assign
Disp_en <= “1110”, this connects the rightmost display to 3.3V and open circuit for other
displays. The common anode (Fig. 3) provides the energy to the LEDs (diodes) from the power
source controlled by the AN signal. When the anode is 3.3V the inputs CA, …, DP provide a pulldown for LEDs to emit light or and an equal potential 3.3V (logic ‘1’) for which the LEDs don’t
emit light.
Fig. 3 Basys3 Board General Purpose Input Outputs, Source Basys3 Reference Manual [1]
The design in Fig 2 connects the 8-bit display data Z: out std_logic_vector(7 downto 0) to the
ports W7 down to V7 (Fig. 3) and Disp_en : out std_logic_vector(3 downto 0) to W4 down to
U2. The ports W7 down to V7 are connected to CA down to DP and the ports W4 down to U2
are connected to AN3 down to AN0.
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Seven-Segment Design Constraints Assignment
The port assignments for Z in the Basys3 Master Design Constraints, the Artix ports Seg[0] to
Seg[7] correspond to W7 down to V7 which are segments A down to DP (see Fig. 5 below and
Fig. 3), thus, Z[7] replaces Seg[0], …, Z[1] replaces Seg[0] and Z[0] replaces dp. With the port
assignments for Disp_en, the port an[0] to an[3] correspond to U2 to W4 (see Fig. 5 and Fig. 3),
thus, Disp_en[0] replaces an[0], … , and Disp_en[3] replaces an[3].
Fig. 5 Basys3 Master Design Constraints File – 7-Segment Displays Ports
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VHDL Code for Stage 2
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2.3 Stage 3 State Machine for Time Division Multiplex (TDM).
This stage uses a clock divider to provide sufficient time period for displaying each of the sevensegment displays separately one-at-a-time. The time slots for the displays are in a round-robin
fashion. This stage is incremental from the stage 2. It involves adding a synchronous design – a
state machine for controlling the multiplexing of the switches inputs to be displayed on the 7segment displays. The clock signal CK_DIV (generated by the clock divider process) which
dictates the duration of the enable signals, makes the four 7-segment displays to appear as if
they were simultaneously enable. It also affects the brightness of the displays. The signal CK_DIV
frequency cannot be too high since the displays will not get sufficient energy, on the other hand,
CK_DIV frequency must be to high enough to give the simultaneously enable appearance. Figure
6 shows a block diagram for Stage 3.
Switch pair selects
State
Machine
TDM control
Display enables
Four 2-bit
vectors
from
switches
7-segment
displays
Z, 8-bit display data
Select logic and
2-to-8 encoder
Fig. 6 TMD of 2-bit Character Displays
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VHDL Code for Stage 3
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2.4 Stage 4 Complete Specification Version
The final stage is an incremental design to Stage 3 to include the design from Stage1 – the four
4-bit registers and selective load. The data size now conforms to the design specification. The
design displays the 4-bit contents of the registers as hexadecimal characters. The user can
change the switch positions and load new contents to any the registers.
The stage 4 entity can be declared as follows:
entity reg_v4 is
port (sw : in std_logic_vector(3 downto 0);
Btn: in std_logic_vector(3 downto 0);
z : out std_logic_vector(7 downto 0);
disp_en : out std_logic_vector(3 downto 0);
ck, reset: in std_logic);
end reg_v4;
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In Stage 4 the code incorporates the stage 1 register process into the stage 3, where R0, R1, R2
and R3 signals are declared in this modification of the stage 3 code. The signal R0, R1, R2 and R3
are assigned to the variable temp replacing the sw(7 downto 6), sw(5 downto 4), sw(3 downto
2) and sw(1 downto 0) signals in the stage 3 code.
With these modifications to the stage 3 code (data size, select load registers process and
assignment of the temp variable), reader can build and test the full specification of the register
bank project.
References
1. https://www.digilentinc.com/Data/Products/BASYS3/Basys3_rm.pdf
2. http://www.electronics-tutorials.ws/transistor/tran_4.html
3. http://wiki.analog.com/university/courses/eps/bjt-switch
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