Download Pass Transistor Logic

Pass Transistor Logic
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We want to transfer a logic 1 using
the circuit below.
Vin
Vx
Cx
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Vg
Assume Vin = VDD, Vg makes a
transition from 0V to VDD and at
t=0 Vx = 0V.
Pass transistor starts to conduct
when the clock Vg makes the
transition.
The pass transistor Tp operates in
saturation since Vgs = Vds and
Vds>Vgs-Vtn
Pass transistor operating in
saturation region starts to charge up
capacitor Cx.
Using the equation for the pass
transistor in saturation we have that
the change in voltage at node x
with respect to time is given by:
Cx
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dVx

dt
n
2
VDD  Vx  Vtn 2
The threshold voltage is subject to
substrate bias effect and thus
depends on the voltage level Vx.
We can simplify the analysis by
neglecting the Vsb factor.
Pass Transistor Logic
• If we integrate the expression describing Cx we can solve for Vx.

t
0
dt 
2C x

dV x
Vx
 V
0
DD
 V x  Vtn 
2

2C x 
1

  V DD  V x  Vtn
 Vx
 | 0

 

2C x 
1
1
  


  V DD  V x  Vtn   V DD  Vtn 
From the above expression for time we can solve V x (t ) to get :
t
V x (t )  V DD
  V DD  Vtn  

t
2
C
x

 Vtn  
  V DD  Vtn  
t
1  
2C x


Pass Transistor Logic
•
The variation of the node voltage
Vx as a function of time shows that
if
thetvoltage
 at node x
cannot exceed a maximum of
•
Vmax  Vx |t   VDD  Vtn
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The above expression assumes that
VSB is at logic 0. What would be
the expression assuming a
changing VSB since the
source/drain voltage changes?
The pass transistor turns off when
Vx=Vmax since at this point the
gate-to-source voltage is equal to
the transistor’s threshold voltage.
We need VGS>Vtn for ON.
VG
Vin
•
Vx
There are several possible states the
terminals could be in:
VG=0=Vin=Vx, VG=VDD with Vin
=Vx=0, VG=VDD=Vin, with Vx=0
etc.
Pass Transistor Logic
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The nMOS device therefore passes
good 0s and poor 1s since the
source cannot be pulled to a value
above VDD-Vtn (the threshold drop).
When the source voltage rises VSB
is not equal to zero any more an
body effects occur.
The threshold drop tends to violate
noise margins.
The pMOS device passes good 1s
and poor 0s.
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Vx of the pMOS drops to below
|Vtp| and the transistor cuts off.
pMOS devices thus pull down to
only |Vtp| above ground (GND).
VDD
Vmax3=VDD-Vtn4
VDD
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V1
V2
V3
Why isn’t, Vmax4 VDD-Vtn1-Vtn2Vtn3-Vtn4?
What would happen if we
configured the series devices above
to have each drain/source drive the
next device’s gate?