Download design for semiconductor reliability

DESIGN FOR
SEMICONDUCTOR RELIABILITY
George Denes, Dipl.Eng.
Senior Semiconductor Reliability Consultant
SEMICONDUCTOR DEVICE LIFE STAGES
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To evaluate the reliability of an electronic system, reliability information on the components used in
that system is important.
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Failure rates are often used as an index for reliability. A failure rate indicates how often a failure
occurs per unit time, and failure-rate values generally change over time as shown in the graph:
SEMICONDUCTOR DEVICE LIFE STAGES
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Early failure stage:
- failures occur at a high rate following the initial operation
- failure rate declines rapidly over time: potential failures that could not be screened in fabrication
fail in a short time if stress such as temperature or voltage is applied, as:
- micro particles collecting on the wafer
- material defects
- photolithography defects
- oxide damage during the fabrication process, etc.
Expectations: memory devices: 1-5 PPM, ASICS, microprocessors: less than 20 PPM
consumer devices: below 2-300 PPM
Random failure stage:
After early failures are eliminated, the failure rate drops to an extremely low value.
Some failures randomly occurring after a long time, the failure rate never decreases to zero.
FR is almost constant because the failures occur sporadically (f. mechanisms on further slides).
Expectations: memory devices: 1-5 FITs, microprocessors: 5-20 FITs, ASICs: 20-30 FITs,
consumer: below 100 FITs.
Wear-out failure stage:
- failures occur with increasing frequency over time and are caused by age-related wear and
fatigue, as: - electronic metal migration
- oxide film destruction (TDDB)
- transistor wear out due to hot carrier damage.
Expectations: consumer: 10 yrs or less, special applications: up to 50-100 yrs.
MAIN ELEMENTS OF SEMICONDUCTOR RELIABILITY
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BIR (Built In Reliability), DfR (Design for Reliability), DfT (Design for Testability)
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(Packaging related DfR is not in this discussion).
1. BIR (Built In Reliability) methods designed and used during wafer fabrication technology process
development and on-going reliability monitoring.
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Reliability metrics: for each process module (can be 14-34) vertically integrated, as:
- ion implantation
- oxide growth
- photo lithography, etching
- metal processes, etc.
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Special wafer level rel. stress-test structures being used to test module reliability, as:
- gate oxide capacitors (large area)
- poly silicon resistors
- metal traces
- interlayer dielectric capacitors (large area)
- contact-and via chains
- stand-alone minimum size transistors, etc.
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WLR (Wafer Level Reliability) testing: utilizes the special test structures (on product wafers or
on special test wafers within the production wafer lot).
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WLR aids process design/development and on-going process reliability monitoring of critical
process modules, as:
- oxide reliability (TDDB),
- hot carrier injection damage
- metal electro migration: SWEAT (Standard Wafer-level Electro migration
Acceleration Test)
- ionic contamination, etc.
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Maintaining tight distribution of reliability metrics is crucial for IC reliability.
DESIGN FOR SEMICONDUCTOR RELIABILITY
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DfR (Design For Reliability)
Design rules: developed by the wafer processing facility for optimized maximum lifetime set by
each physical failure mechanism for each process module, as:
- max. allowed voltages
- transistor channel length
- max. current per unit metal line width
- max. current per contact and via
- interconnect layout rules
- active area spacing
- transistor layout rules, etc.
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Failure to comply with the reliability design rules may lead to unpredictably shorter IC lifetime.
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IC Design Engineering jointly with Reliability Engineering develops special reliability test chips if
needed to emulate and evaluate the reliability of critical circuit design features and/or design
concepts, examples:
- ESD protection circuits
- latch up immunity of the I/O-s and internal circuits
- special circuits to emulate the most reliability-critical circuit modules of the planned IC with easy
electrical access to stress and test, examples: - memory cell transistors (DRAM, SRAM,
EPROM, Flash, etc.)
- highest speed circuit modules
- high power circuit modules
- high voltage modules
- voltage reference circuits
- A/D and D/A conversion circuits
- phase locked loops
DESIGN FOR SEMICONDUCTOR RELIABILITY
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Reliability simulator software programs facilitate prediction of IC lifetimes.
Examples:
MULSIC on-the-chip metal interconnect processing simulator (like damascene
metal process, etc.), it is also an interconnect behavioral and reliability simulator,
can be integrated with overall IC circuit design simulation software (TCAD,
SPICE, etc.)
APET (Georgia Tech.) interconnect reliability and circuit hot spot evaluation
software.
TSMC contract wafer foundry (Taiwan) “eReliability Estimator” program for all
their wafer process technologies, enabling customers to do lifetime estimation for
the major IC reliability failure mechanisms in their design environment, as:
electromigration (metal interconnect, contact, via),
– Time Dependent Dielectric Breakdown (TDDB) of MOS gate oxide and
interlayer oxides,
– Hot Carrier Damage of MOS transistors due to high conducting channel
electrical fields,
– negative gate bias induced device degradation (NBTI) effecting mostly
PMOS transistors, etc.
Reliability Engineering should perform due diligence auditing of all
previously listed activities if done by a contract IC manufacturing facility.
SEMICONDUCTOR DESIGN FOR RELIABILITY
TESTABILITY
• DfT (Design For Testability)
• We are addressing IC chip reliability testability, closely related to
volume production functionality screen testing.
• IC life testing (HTOL) requires dynamic close to “lifelike” functioning
of the device under stress during ALT.
• To achieve dynamically stimulated functional realistic stimulation
and loading of the IC devices during ALT, we do the followings:
• For digital ASIC circuits min. 85 % gate toggle coverage is desired
during ALT for a reasonable degree of confidence. The following
methods are utilized to “exercise” the chip during ALT:
SEMICONDUCTOR DESIGN FOR RELIABILITY
TESTABILITY
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asserting a large number of functional test vectors (0-s and 1-s patterns) in
parallel on all digital inputs (with the IC outputs loaded); these test vectors are a
subset of the product functional test vectors (generated by circuit simulations)
used for production pass/fail testing,
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using JTAG serial boundary input scan vectors (IEEE Std. 1149.1) if the ASIC
chip is designed with test circuits (shift registers) to use serial test input vectors
to toggle all logic gates of the IC with a serial input vector during Dynamic Life
Testing (ALT),
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invoking special stress modes of reliability critical circuits during ALT, if such
special stress modes are designed-in on the IC, example: for flash memories
stressing all word lines and all bit lines simultaneously.
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utilize the on-the-chip designed-in BIST (Built In Self Test) feature for
embedded memories in ASICs (if available) during the Dynamic Life Test (ALT) to
stimulate/exercise all transistors of the embedded memories.
DESIGN FOR SEMICONDUCTOR RELIABILITY
3. IC Package Reliability Modeling
* Computer-aided engineering (CAE) is the modern tool of designing for IC package
reliability. These tools are utilizing finite element modeling (FEM).
* Validated computer models can be used for design of experiments (DOE) studies
of IC package geometry, material properties, thermo-mechanical properties, etc. under
application-and test conditions.
* Modeling capabilities exist for both first-and second level package reliability prediction
(package-die interaction and package-circuit board interaction).
* Model types and potential reliability issues covered:
- Thermo-Mechanical Stress Modeling for: structural reliability, identifies high stress areas
due to mismach of coefficients of thermal
expansion.
Correlated with warpage measurements from moire
interferometry and cross section analysis.
- Viscoelastic Warpage Modeling: more sophisticated than linear-elastic (stress) modeling.
Good molding compound properties analyzer (requires
time dependent viscoelastic material properties).
* Moisture Diffusion Modeling: moisture induced IC package failures, as: popcorning and
delamination (both can happen during solder reflow due to
sudden vaporization).
DESIGN FOR SEMICONDUCTOR RELIABILITY
IC Package Reliability Modeling (continued):
* Hygroswelling Modeling: simulates hygroswelling or hygro-mechanical stress due to
a mismatch of coefficient of moisture expansion of package materials
when moisture is absorbed.
* Vapor Pressure Modeling: simulates the distribution of vapor pressure during solder reflow
process to asses the “popcorning” failure mechanism.
A moisture diffusion model is applied to predict the local moisture
concentration at the critical interfaces. The vapor pressure induces
additional mismatch to the package, which is of the same order as
the thermo-mechanical and viscoelastic mismatch stress.
* Integrated Stress Modeling: combines all stress and associated failure mechanisms to
enhance good IC package design for reliability.
* Board Level Solder Joint Reliability Modeling (second level reliability):
package-circuit board interaction. Critical issue for QFP, TFBG, QFN packages.
The model is correlated to temperature cycling results . The solder joint faigue life calculated
using this model.