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CUSTOMER_CODE
SMUDE
DIVISION_CODE
SMUDE
EVENT_CODE
JAN2016
ASSESSMENT_CODE BCA1040_JAN2016
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
5709
QUESTION_TEXT
Explain in brief any four types of electronic DACs.
SCHEME OF
EVALUATION
Solution:
Explanation of each – 2.5 marks x 4 = 10 marks
Answer:
The Pulse Width Modulator, the simplest DAC type. A stable
current or voltage is switched into a low pass analog filter with a
duration determined by the digital input code. This technique is
often used for electric motor speed control, and is now becoming
common in high-fidelity audio.
Oversampling DACs or Interpolating DACs such as the Delta-Sigma
DAC, use a pulse density conversion technique. The oversampling
technique allows for the use of a lower resolution DAC internally. A
simple 1-bit DAC is often chosen because the oversampled result is
inherently linear. The DAC is driven with a pulse density modulated
signal, created with the use of a low-pass filter, step nonlinearity (the
actual 1-bit DAC), and negative feedback loop, in a technique called
delta- sigma modulation. This results in an effective high-pass filter
acting on the quantization (signal processing) noise, thus steering
this noise out of the low frequencies of interest into the high
frequencies of little interest, which is called noise shaping (very high
frequencies because of the oversampling). The quantization noise at
these high frequencies are removed or greatly attenuated by use of
an analog low-pass filter at the output (sometimes a simple RC lowpass circuit is sufficient). Most very high resolution DACs (greater
than 16 bits) are of this type due to its high linearity and low cost.
Higher oversampling rates can either relax the specifications of the
output low-pass filter and enable further suppression of
quantization noise. Speeds of greater than 100 thousand samples per
second (for example, 192kHz) and resolutions of 24 bits are
attainable with Delta-Sigma DACs.
The Binary Weighted DAC, which contains one resistor or current
source for each bit of the DAC connected to a summing point. These
precise voltages or currents sum to the correct output value. This is
one of the fastest conversion methods but suffers from poor
accuracy because of the high precision required for each individual
voltage or current. Such high-precision resistors and current-
sources are expensive, so this type of converter is usually limited to
8-bit resolution or less.
The R-2R Ladder DAC, which is a binary weighted DAC that uses a
repeating cascaded structure of resistor values R and 2R. This
improves the precision due to the relative ease of producing equal
valued matched resistors (or current sources). However, wide
converters perform slowly due to increasingly large RC-constants
for each added R-2R link.
The Thermometer coded DAC, which contains an equal resistor or
current source segment for each possible value of DAC output. An 8bit thermometer DAC would have 255 segments, and a 16-bit
thermometer DAC would have 65,535 segments. This is perhaps the
fastest and highest precision DAC architecture but at the expense of
high cost. Conversion speeds of >1 billion samples per second have
been reached with this type of DAC.
Hybrid DACs, which use a combination of the above techniques in a
single converter. Most DAC integrated circuits are of this type due
to the difficulty of getting low cost, high speed and high precision in
one device.
o The Segmented DAC, which combines the thermometer coded
principle for the most significant bits and the binary weighted
principle for the least significant bits. In this way, a compromise is
obtained between precision (by the use of the thermometer coded
principle) and number of resistors or current sources (by the use of
the binary weighted principle). The full binary weighted design
means 0% segmentation, the full thermometer coded design means.
100% segmentation.
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
5710
QUESTION_TEXT
Explain the important characteristics of DAC devices.
Characteristics of DAC devices.
Resolution (2 marks)
Maximum sampling frequency (2 marks)
SCHEME OF EVALUATION
Monotonicity (2 marks)
THP + N (2 marks)
Dynamic range(2 marks)
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
72381
QUESTION_TEXT
Explain the rules for simplifying functions using K–map.
SCHEME OF
EVALUATION
Summary of rules for simplifying functions using Karnaugh maps
1. While implementing minterm function, cells in K-map should be
included with all 1’s but not 0’s. While implementing maxterm function,
cells in K-map should be included with all 0’s but not 1’s. 2. Group
only cells which are horizontally or vertically adjacent to each other.
3. In –map the group size should be in power of 2 .i.e., group size can
be 1, 2, 4, 8 and so on.
4. The largest size groups are used to obtain the simplest form. Use
the fewest groups possible.
5. In order to achieve the step 4, overlaps can be used.
6. A horizontal ‘wrap around’ can be done for 3-variable map,
horizontal and vertical ‘wrap around’ can be done for 4-variable
map.7. Include 'don't cares' within groups as needed to achieve the
goals of point 4 above. 'Don't cares' should not be included if by so
doing the groups are not made larger or fewer.
These are six rules. Any five should be there. Each carries 2 marks.
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
72382
QUESTION_TEXT
Explain the recommended steps for the design of sequential circuit.
SCHEME OF
EVALUATION
The steps are:
● Specify the problem (Word description of the circuit behavior)
● Derive the state diagram
● Obtain the state table
● The number of states may be reduced by state reduction
method
● Determine the number of flip-flops needed
● Choose the types of flip-flops to be used
● Derive excitation equation
● Using the map or any other simplification method, derive the
output function and the flip-flop input function
● Draw the logic diagram
All the steps should be given clearly.
QUESTION_TYPE DESCRIPTIVE_QUESTION
QUESTION_ID
72385
QUESTION_TEXT Explain universal gates along with their truth tables.
SCHEME OF
EVALUATION
The NAND gate is a digital logic gate that behaves in a manner that corresponds
to the truth table to the left. A LOW output results only if both the inputs to the
gate are HIGH. If one or both inputs are LOW, a HIGH output results. The NAND
gate is a universal gate in the sense that any Boolean function can be
implemented by NAND gates.
Digital systems employing certain logic circuits take advantage of
NAND's functional completeness. In complicated logical expressions,
normally written in terms of other logic functions such as AND, OR, and
NOT, writing these in terms of NAND saves on cost, because
implementing such circuits using NAND gate yields a more compact
result than the alternatives. NAND gates can also be made with more
than two inputs, yielding an output of LOW if all of the inputs are HIGH,
and an output of HIGH if any of the inputs is LOW. These kinds of gates
therefore operate as n-ary operators instead of a simple binary
operator.
(4 marks)
(2 marks)
The NOR gate is a digital logic gate that implements logical NOR - it behaves
according to the truth table to the right. A HIGH output (1) results if both the
inputs to the gate are LOW (0). If one or both inputs are is HIGH (1), a LOW
output (0) results. NOR is the result of the negation of the OR operator. NOR is
a functionally complete operation - combinations of NOR gates can be
combined to generate any other logical function. By contrast, the OR operator
is monotonic as it can only change LOW to HIGH but not vice
versa.
(3 marks)
(1 mark)
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
72387
QUESTION_TEXT Explain the functions of decoders.
SCHEME OF
EVALUATION
A decoder is a digital device which decodes the original information
from the encoded inputs. The functionality of a decoder is exactly the
reverse of an encoder. In order to decode the information from the
signals, the method used to encode the information is reversed.
In digital systems, decoder is a logic circuit with multiple inputs and
multiple outputs that produces a coded output from the coded inputs.
In decoder the input and output codes are different i.e., if there is an nbit input code then decoder produces 2^n output code.
The outputs of a decoder without enable input are assumed as single
"disabled" output code word. In digital circuits, decoders are used in
many applications like 7 segment display, multiplexing of the data and
decoding of the memory address.
(4 marks)
When all the input of an AND gates are "high" the output will also be
"high", therefore the AND gate can be considered as the simple
decoder. The output which goes "high" when the inputs are high is
known as "active High output". If NAND gate is connected instead of
AND gate, then when all the inputs are "high" the output will be "Low"
(0). Such output is called as "active low
output".
(1 mark)
A slightly more complex decoder would be the n-to-2n type binary
decoders. With n-to-2n binary decoders, maximum of '2n' outputs are
generated from 'n' coded inputs which carry information. For 'n' bit
coded input, if there are any unused combinations then number of
outputs of the decoder can be less than 2n. From above discussion we
can say that a decoder can produce maximum of 2n outputs. . In digital
systems various types of decoders like 2-to-8 decoder, 2-to-4 decoder or
4-to-16 decoder are used. Two 2-to-4 decoders along with enable signal
can be used to construct a 3-to-8 decoders.
(2 marks)
In the same way, a 4-to-16 decoder can be constructed by combining
two 3-to-8 decoders. In the above design process, the 4th input which is
given as enable input to both 3-to-8 decoders acts like selector between
two 3-to-8 decoders,. The outputs D(0) through D(7) are produced by
the first decoder and D(8) through D(15) are produced by the second
decoder, the 4th input in 4-to-16 decoder enables either the first
decoder or second decoder.
This kind of decoders with enable signals is also known as a decoderdemultiplexer. Thus, we have a 4-to-16 decoder produced by adding a
4th input shared among both decoders, producing 16
outputs.
(3 marks)