Download Advanced VLSI Design - WSU EECS

EE 587
SoC Design & Test
Partha Pande
School of EECS
Washington State University
[email protected]
1
System Design Issues
2
Low Energy FPGA Architecture
• Architectural level optimization
– Level 0 – Nearest Neighbor
– Level 1 – Mesh
– Level 2 - Hierarchical
3
Different Architectures
4
Paths in Interconnect
LE
LE
LE
Wiring channel
• Connection may be long, complex:
LE
LE
LE
LE
LE
LE
Wiring channel
LE
LE
LE
LE
LE
LE
5
Interconnect Architecture
• Connections from wiring channels to LEs.
• Connections between wires in the wiring channels.
Wiring channel
LE
LE
6
channel
Switchbox
channel
channel
channel
7
Mesh-based Interconnect Network
Switch Box
Routing of the data
Connect Box
Connects cell I/Os
To the global
interconnect
Interconnect
Point
Courtesy Dehon and Wawrzyniek
8
Circuit Level Optimization
• The
connecting path from one CLB to
another is an RC chain
9
Low Swing Interconnect
Mode
E (pj)
D (ns)
ED
Full Swing
72.3
1.9
137
Low Swing
31.4
2.3
72
10
Low Power SRAM Design
11
Memory Organization
2L-K
Bit line
Storage cell
AK
AK-1
Word line
AL-1
M.2K
Sense amplifiers/drivers
A0
AK-1
Column decoder
Input-Output (M bits)
12
SRAM Cell
VDD
Precharge
circuit
PC
EQ
WL
BL
BL
Output
bit
Sense
amplifier
bit
13
Cell Array Power Management
• Smaller transistors
• Low supply voltage
• Lower voltage swing (0.1V – 0.3V for SRAM)
– Sense amplifier restores the full voltage swing for outside
use.
14
SRAM Cell Design
•
•
6 transistor SRAM cell reduces static current
(leakage) but take more area
Vth reduction in very low Vdd SRAMs suffer from
large leakage current
 Use multiple threshold devices:
Memory cell with high Vth (reduce leakage)
Peripheral circuits with low Vth (improve speed)
15
Banked Organization
• Banking targets total switched capacitance to achieve reduced
power and improved speed
16
Divided Word Line
•
•
Main idea: Divide each row of RAM cells into segments (blocks), use a
decoder to access only one segment
Only the memory cells in the activated block have their bit line pair
driven
17
Divided Word Line
• Pros:
 Improves speed (by decreasing word line delay)
 Lower power dissipation (by decreasing the number of bit
line pair activated)
• However, local decoders add delay
• Less cells/block reduces power, but increases area (more local
decoders)
• Chang, 1997:
49.8% power reduction, 14.8% area penalty
82.9% power reduction, 24.8% area penalty
18
Reduced Bit Line Swing
•
Limit voltage swing on bit lines to improve both speed and
power:
1.
2.
•
Pulsed word line
Bit line isolation
Need sense amplifiers for each column to sense/restore
signal
19
Pulsed Word Line
•
Main idea: Isolate memory cells
from the bit lines after sensing,
to prevent the cells from
changing the bit line voltage
further
20
Pulsed Word Line
SA
Word Decoder
Memory Core
Word Driver
Dummy Column
Accessed Row
Q
Sense Amplifiers
R
Reset from dummy sense-amp
S
Word enable
21
Pulsed Word Line
•
•
•
Dummy bit lines reach full swing, but trigger pulse shut off when regular
bit lines reach 10% swing
Generation of word line pulses very critical
– Too long: power efficiency degraded
– Too short: Sense amplifiers operation may fail
Generation of word line using delay lines is susceptible to process and
temperature
22
Bit Line Isolation
•
Main idea: Isolate sense amplifiers from bit line after sensing, to
prevent from having large voltage swings
23
Row Decoders
Collection of 2M complex logic gates
Organized in regular and dense fashion
(N)AND Decoder
NOR Decoder
24
Hierarchical Decoders
Multi-stage implementation improves •performance
••
WL 1
WL 0
A 0A 1 A 0A 1 A 0A 1 A 0A 1
A 2A 3 A 2A 3 A 2A 3 A 2A 3
•••
NAND decoder using
2-input pre-decoders
A1 A0
A0
A1
A3 A2
A2
A3
25
Data Retention in SRAM
1.30u
1.10u
0.13 m m CMOS
Ileakage
900n
700n
500n
(A)
Factor 7
300n
0.18 m m CMOS
100n
0.00
.600
1.20
1.80
VDD
SRAM leakage increases with technology scaling
26
Reducing Retention Current
•
•
•
•
Turning off unused memory blocks
Increasing the thresholds by using body biasing
Inserting extra resistance in the leakage path
Lowering the supply voltage
27
Suppressing Leakage in SRAM
V DD
V DD
low-threshold transistor
V DDL
sleep
V DD,int
sleep
V DD,int
SRAM
cell
SRAM
cell
sleep
SRAM
cell
SRAM
cell
SRAM
cell
SRAM
cell
V SS,int
Inserting Extra Resistance
Reducing the supply voltage
28