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Transcript
CHARACTERIZATION OF SUBSTRATE NOISE COUPLING, ITS
IMPACTS AND REMEDIES IN RF AND MIXED-SIGNAL ICs
DISSERTATION
Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy
in the Graduate School of the Ohio State University
By
Ahmed A. Helmy, B.S., M.S.
*****
The Ohio State University
2006
Dissertation Committee:
Professor:
Mohammed Ismail, Adviser
Professor:
John Volakis
Professor:
Steven Ringel
Approved by
Adviser
Graduate Program in Electrical and
Computer Engineering
© Copyright by
Ahmed Helmy
2006
ABSTRACT
Substrate noise coupling in integrated circuits is the process by which interference signals
in the form of voltage and current glitches generated by high speed digital and high power blocks
cause parasitic currents to flow in the silicon substrate and electrically couple devices in various
parts of the circuits on this common substrate. In RF and mixed signal ICs the switching noise is
coupled to the sensitive analog circuits through the substrate causing degradation in performance
that impacts the yield. Thus, overcoming substrate coupling is a key issue in successful “system
on chip” integration. The integration of RF blocks and high speed IO interface circuits with the
digital signal processing section to reach a system on chip and higher levels of integration due to
the continuous shrinking of the technology feature size make the coupling even more pronounced
in the present ICs realizations.
In this thesis a novel substrate aware design flow is built, calibrated to silicon and used as
part of the design and validation flows to uncover and fix the substrate coupling problems in
RFICs in the design phase. The flow is used to develop the first comprehensive RF substrate
noise isolation design guide to be used by RF designers during the floor planning, circuit design
and validation phases. This will allow designers to optimize the design to maximize noise
isolation and protect sensitive blocks from being degraded by substrate noise coupling. Several
effects of substrate coupling on circuit performance will be identified and remedies will be given
based on the design guide. Three case studies are designed to analyze the substrate coupling
problem in RFICs. The case studies are designed to gradually attack the problem from the device
(case1), circuit (case2) and finally a system level (case3) wraps it up by applying the research
ii
findings on a system level industrial problem. On the device level a special emphasis is given to
the design of on chip inductors as an important device in today’s SOC systems and the impact of
substrate noise coupling on the inductor performance is characterized. An accurate model is
developed for a broadband fit of the inductor scattering parameters to a lumped macro model that
is used in the system analysis of case study 3. This model is shown to be scalable and is proven to
be accurate when applied to various frequency bands and inductor geometries. A special
emphasis is put on the DFM effects that affect the design robustness. A circuit level case study is
developed and results are compared to simulations and silicon measurements to highlight the
need for such a flow before tapping out to ensure a yielding part. In case study 3 a system level
problem is studied on a GSM cellular receiver chain and the research results are directly applied
to it as a demonstration vehicle to debug and resolve a system level substrate noise coupling
problem that otherwise caused a product to be on the edge of malfunction, which has a direct hit
on its yield and hence its profit margins
iii
Dedicated to Yasmin, Zeina, Aly, Omar, Tahany, Helmy, Amira and Tarek
iv
ACKNOWLEDGMENTS
I would like to express my sincere gratitude to Professor Mohammed Ismail for giving
me the opportunity to be one of his students. His skilful and professional academic guidance,
technical insight and supervision as well as his pleasant personality are the main factors that
empowered this research work. I really learned from him a lot on the technical, professional and
personal levels.
I would also like to extent my gratitude to my professors in Cairo, Egypt, Prof. Hani
Fikry and Prof. Wael Fikry the first to teach me the basics and the persistence needed in the
research work.
I am very thankful to all my colleagues at the Analog VLSI Laboratory., the Ohio State
University for their team spirit and providing a great place to work.
I would like to express the deepest and warmest gratitude to my parents and in-laws for
their support during my study at the Ohio State University.
Last but not least I am extremely grateful to my lovely wife for her unlimited support and
continuous belief in me and her never lasting sacrifices.
v
VITA
November 23, 1972 . . . . . . . . . . . . . . . . . . . .
Born, Cairo, Egypt
1994 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B.S. Electrical Engineering, Ain Shams University,
Cairo, Egypt
1996 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device modeling Engineer Mentor Graphics, Cairo,
Egypt
1999 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M.S. Engineering Physics, Ain Shams University,
Cairo, Egypt
2000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Graduate research Associate, Analog VLSI Lab, The
Ohio State University
2002 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Graduate Intern Intel Corporation Chandler Arizona
2003-Present . . . . . . . . . . . . . . . . . . . . . . . . .
Staff Design Engineer, Intel Corporation, Chandler,
Arizona
PUBLICATIONS
Research Publications
1. Ahmed Helmy and Mohammed Ismail, “A Design Guide for Reducing Substrate Noise
Coupling in RF Applications” IEEE Circuits and Devices magazine, volume 22, issue 4
July-August 2006
FIELDS OF STUDY
Major Field: Electrical Engineering
vi
TABLE OF CONTENTS
Page
Abstract
.......................................................
ii
.....................................................
iv
Dedication
Acknowledgements
Vita
..............................................
v
..........................................................
vi
List of Tables
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
List of Figures
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii
Chapter 1
Introduction
1
1.1
Motivation and Research Objectives
........................
1
1.2
Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
1.3
Thesis Organization
7
.....................................
Chapter 2
Analysis of Substrate Noise Coupling
8
2.1.
Process Regions
2.2.
Process cross sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
2.3.
Connection of devices to the substrate
........................
13
2.3.1.
Devices directly connected to the substrate network . . . . . . . . . . .
13
2.3.2.
Devices indirectly connected to the substrate network . . . . . . . . . .
14
2.4.
.....................................
Noise coupling mechanism
2.4.1.
..............................
Substrate Noise Injection Mechanisms
.................
9
15
15
2.4.1.1.
Noise Injection through Capacitive Coupling
...........
16
2.4.1.2.
Noise Injection through impact ionization
...........
17
vii
2.4.1.3.
Noise Injection due to Power Grid Fluctuations . . . . . . . . . . .
19
2.4.2.
Substrate Noise Reception Mechanisms
..................
20
2.4.3.
Substrate Noise Transmission Mechanisms
.................
21
2.5.
Substrate doping profile tradeoffs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
2.6.
Substrate Model extraction in the IC design flow . . . . . . . . . . . . . . . .
24
2.7.
Doping Profile Considerations
..............................
24
2.8.
Substrate model extraction kernels . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
2.8.1.
Finite Difference method
..............................
26
2.8.2.
Boundary Element method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
2.8.3.
Comparison between the two Techniques
.................
28
2.8.4.
Approximations in the Model Extraction Algorithm . . . . . . . . . .
29
2.8.4.1.
The Electrostatic Assumptions . . . . . . . . . . . . . . . . . . . . . . . .
29
2.8.4.2.
The Linearity Assumption . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
2.8.4.3.
The Equipotential Assumption . . . . . . . . . . . . . . . . . . . . . . . .
30
2.9.
Conclusion
............................................
31
Chapter 3
Experimental Data to calibrate the design flow
32
3.1.
Introduction
...........................................
32
3.2.
The test chip
...........................................
34
3.3.
Baseline Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
3.3.1.
3.4.
Data analysis
.... ....................................
Effect of p-guard ring on isolation
3.4.1.
3.5.
Data analysis
...........................
38
....................................
39
Effect of n-guard ring on isolation
3.5.1.
3.6.
Data analysis
.......................
41
....................................
44
Effect of deep n-well on isolation
3.6.1.
3.7.
Data analysis
.......................
44
....................................
45
Effect of deep trench on isolation
3.7.1.
.......................
47
.....................................
47
.....................................
49
...........................................
52
Data analysis
3.8.
De-embedding
3.9.
Conclusion
36
viii
Chapter 4
Design Guide for Substrate Noise Isolation for RF Applications
53
4.1.
Introduction
............................................
4.2.
Isolation in Low resistivity substrate
........................
54
4.3.
Isolation vs. Frequency for different isolation structures . . . . . . . . . . .
54
4.4.
Effect of back plane connection on the noise isolation in high resistivity
aaaaaasubstrates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.
Substrate Contacts: Front side or Backside? Both
4.6.
P+ Guard Ring Isolation
53
56
...........
58
...............................
61
4.6.1.
Guard Ring Isolation vs. D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
4.6.2.
Guard Ring grounding scheme
.......................
63
4.6.3.
Guard Ring Isolation vs. d
..............................
65
4.6.4.
Guard Ring Isolation vs. “w”
.......................
67
4.7.
P+ and N+ Guard Rings Isolation
.......................
69
4.8.
Floor planning techniques to minimize coupling . . . . . . . . . . . . . . . . .
72
4.9.
Circuit techniques to minimize coupling . . . . . . . . . . . . . . . . . . . . . . . .
75
4.10.
Active guard rings
....................................
76
4.11.
Conclusion
...........................................
77
Chapter 5
On Chip Inductor Design Flow
78
5.1.
Introduction
5.2.
Integrated Inductors
....................................
79
5.3.
Inductor Design Flow
....................................
81
5.4.
Analytical exploration of the design space
.................
82
5.5.
Inductor Model and Substrate Parasitics . . . . . . . . . . . . . .. . . . . . . . . .
89
5.6.
Calibrating the field solver
5.7.
Model fit
5.8.
DFM effects
5.9.
...........................................
78
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.8.1.
Impact of bumps
5.8.2.
Impact of temperature variation
5.8.3.
Impact of process variation
5.8.4.
Impact of metal fill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Conclusion
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
. . . . . . . . . . . . . . . . . . . . . . . . 101
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
ix
Chapter 6
Case studies for the impact and remedy of substrate noise coupling
6.1.
Introduction
...........................................
6.2.
System Level Case study
107
107
..............................
108
6.2.1.
Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
109
6.2.2.
Design Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
111
6.3.
6.3.1.
Block Level Case study
....................................
120
Design details
....................................
120
..............................
126
...........................................
129
6.4.
Device Level Case study
6.5.
Conclusion
Chapter 7
Conclusion and Future work
131
Appendix A
Scattering Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
133
Appendix B
Measurements Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
137
Bibliography
.........................................................
142
x
LIST OF TABLES
Table
Page
5.1
set of parameters that should be considered during designing the inductor . . .
81
5.2
process information relevant to the inductor design . . . . . . . . . . . . . . . . . . . . .
94
5.3
process corner definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
103
6.1
C/N calculations for the receiver chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
111
6.2
substrate noise coupling level at mixer input relative to the noise source . . . . .
115
6.3
substrate noise coupling level at victim points with and without deep trenches. . 117
6.4
substrate noise coupling level at victim points for all three versions . . . . . . . . . 119
6.5
inductor parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
xi
LIST OF FIGURES
Figure
Page
1.1
History of Moore's law . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
Trend in Silicon Systems and products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1
Cross section of a general BICMOS process
......................... 9
2.2
Contacts in N-well resistors and capacitors
. . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3
Poly resistor model showing substrate network already accounted for
2.4
device models must be studied to accurately separate devices from the substrate 14
2.5
device to substrate capacitive coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
2.6
cross section of a packaged chip showing bond wire noise
...........
20
2.7
Substrate cut-off frequency fc as a function of resistivity ρsub
...........
22
2.8
Substrate as an undesired noise transfer medium . . . . . . . . . . . . . . . . . . . . . . . .
24
2.9
Disretization of substrate doping profiles
2.10
representing a substrate by a mesh of resistors
3.1
The Design flow used to characterize substrate noise coupling
3.2
the test bench used to simulate the substrate model of the isolation structures . . 33
3.3
Die photograph of the test chip used to measure the isolation of different
rrrrrrrrrrsubstrate structures
3.4
1
. . . . . 13
. . . . . . . . . . . . . . . . . . . . . . . . . 25
. . . . . . . . . . . . . . . . . . 27
. . . . . . . . . . . 33
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Layout & cross section of the structure used to measure and simulate the
rrrrrrrrrrbaseline isolation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.5
Measurement vs. simulation for baseline isolation structure
...........
3.6
Layout and cross section of the structure used to measure and simulate the
37
rrrrrrrrrrp+-guard ring isolation structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.7
careful grounding is needed not to increase substrate noise coupling . . . . . . . . . 40
3.8
p+_guard ring isolation once surrounding the receiver and once surrounding the
rrrrrrrrrtransmitter
3.9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Layout and cross section of the structure used to measure and simulate the
rrrrrrrrrrn+-guard ring isolation structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
3.10
42
measurement data for n+_guard ring isolation structure
xii
.................
Figure
Page
3.11
measurement vs. simulation for n+_guard ring isolation structure . . . . . . . . . .
43
3.12
comparison between isolation techniques
43
3.13
Layout and cross section of the structure used to measure and simulate the deep
rrrrrrrrrrn-well guard ring isolation structure
3.14
.......................
..............................
45
measurement and simulation data of the deep n-well guard ring isolation structure
........................................................
3.15
comparison between the isolation of two deep n well guard rings and two n well
rrrrrr
guard rings
3.16
Layout and cross section of the structure used to measure and simulate the deep
rrrrrr
trench isolation structure
3.17
isolation of a p guard ring with a surrounding deep trench as compared to a
...........................................
rrrrrrrrrrregular p guard ring
....................................
...........................................
46
46
48
48
3.18
Layout and equivalent circuit of the GSG structure with the DUT . . . . . . . . . .
49
3.19
Layout and equivalent circuit of the GSG open structure . . . . . . . . . . . . . . . . .
50
3.20
Layout and equivalent circuit of the GSG short structure . . . . . . . . . . . . . . . . .
50
4.1
test structure used to simulate the backplane impact on isolation for resistive
rrrrr
coupling
..................................................
58
4.2
Baseline isolation for resistive coupling vs. backplane inductance . . . . . . . . . .
59
4.3
test structure used to simulate the backplane impact on isolation for capacitive
rrrrr
coupling
4.4
Baseline isolation for capacitive coupling
4.5
test structure used to simulate the impact of guard rings on isolation
4.6
Guard ring Isolation vs. distance D
.................................................
.......................
59
60
....
62
..............................
62
4.7
Guard ring grounding schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64
4.8
Guard ring grounding scheme simulation data LGR=1nH . . . . . . . . . . . . . . . .
64
4.9
Guard ring Isolation vs. distance “d”
..............................
66
4.10
Guard ring Isolation vs. distance “d”
..............................
66
4.11
Structure used to simulate guard ring isolation vs. distance “w”
..........
67
4.12
Guard ring Isolation vs. ring width “w” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
4.13
P and N Guard ring Isolation structure
..............................
70
4.14
P and N Guard ring Isolation vs. enclosure distance “d” . . . . . . . . . . . . . . . . .
71
4.15
floor planning to minimize substrate noise coupling
72
xiii
.................
Figure
Page
4.16
placements and biasing of the guard rings and ground lines
..........
73
4.17
layout used to simulate the impact of guard rings on differential noise
....
75
4.18
differential isolation using p guard ring and dual p & n-well guard rings . . . .
76
5.1
Inductor design flow
...........................................
82
5.2
Inductor layout showing design parameters and some DFM rules . . . . . . . . . .
84
5.3
L contours as a function of OD and W at a given N and S
..........
84
5.4
Q contours as a function of OD and W at a given N and S
..........
85
5.5
L, Q contours as a function of OD and W at a different N and S
.........
86
5.6
Q vs. f showing different losses mechanisms
.......................
89
5.7
differential inductor macro model
..............................
90
5.8
test bench used to extract model parameters
5.9
Q and L simulation vs. measurement
5.10
Q and L simulation vs. measurement zoom in (left), parallel differential inductor
rrrrrr
(right)
........................................................
95
5.11
Q and L macro model fit vs. sp file and percentage error . . . . . . . . . . . . . . . . .
96
5.12
inductor parameters (left) macro model and its fitting parameters (right) . . . . .
97
5.13
Q and L macro model fit vs. sp file and percentage error (left) inductor parameters
rrrrrr
(right)
5.14
macro model fitting parameters
5.15
Bump relative position to the on-chip inductor
5.16
Impact of bumps on the inductor Q and L (OD=120um, W=4.7um, S=0.6um, N=5)
.......................
91
........................
94
........................................................
....................................
.......................
.......................................................
.......................
97
98
100
100
5.17
impact of temperature on the inductor Q and L
5.18
impact of process variation on inductor performance
5.19
inductor with metal fill patterns, top metal (left), n-1 metal (middle), n-2 metal
rrrrrr
(right)
........................................................
104
5.20
inductor with metal fill patterns, metal 1, (left), ploy, ndiff, pdiff (right) . . . .
105
5.21
inductor with via fill patterns
105
5.22
impact of dummification on Q and L
6.1
Block diagram of the RF receiver used in the case study
6.2
6.3
.................
...................................
..............................
102
103
105
................
108
LO phase noise specification
....................................
113
LO phase noise mixing data
....................................
113
xiv
Figure
Page
6.4
substrate noise coupling model
....................................
114
6.5
layout of the VCO, LO and mixer
..............................
114
6.6
substrate noise coupling distribution (case of vco perturbation)
6.7
substrate noise coupling distribution (case of blocker perturbation) . . . . . . . . . . 115
6.8
layout comparison of both versions
6.9
Adding deep trenches in and around the VCO
6.10
Noise levels without deep trenches added (left), and with deep trenches added
rrrrrr
(right)
6.11
Noise aggressor and victim points using the modified VCO (left), noise levels
...........
.............................
.......................
.......................................................
(right)
................................................
6.12
A die photograph showing the VCO mixer section
6.13
Transmit buffer schematic without substrate network
6.14
Transmit buffer schematic with substrate network
6.15
Pout and Pgain vs. Pin with and without substrate model vs. silicon data
@ 1.9GHz
115
116
117
117
118
...............
119
.................
121
................
121
.................................................
122
6.16
S12 measured and simulated with and without substrate model vs. silicon data
rrrrrr
@ 1.9GHz
6.17
transmit buffer layout
..........................................
124
6.18
transmit buffer layout
..........................................
124
6.19
transmit buffer PN unmodified layout (right) modified layout and measurement
................................................
123
(left). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
125
6.20
inductor test cases
127
6.21
inductance vs. freq for the four test cases
........................
128
6.22
Quality factor vs. freq for the four test cases . . . . . . . . . . . . . . . . . . . . . . . . . .
129
A.1
Low-frequency description of two-port
134
A.2
High-frequency description of two-port. Z0 is the characteristic impedance . . . . 135
...........................................
..............................
of the lines
B.1
VNA setup to measure S-parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
138
B.2
Layout of the measured differential inductors . . . . . . . . . . . . . . . . . . . . . . . . . .
139
B.3
Layout of the measured differential inductors with all de embedding structures . 140
B.4
Transmit buffer measurement setup and calibration steps . . . . . . . . . . . . . . . . .
xv
141
CHAPTER 1
INTRODUCTION
1.1.
Motivation and Research Objectives
The current trend in process technologies is marching towards 45nm production in 2007
and 32nm production in 2009 [60]. The trend is still obeying Moor's law [61], which states that
the number of transistors on a single chip doubles every 2 years. Figure 1.1 shows the history of
Moore's law. In addition to the number of transistors, the demand on system on chip "SOC" and
system in package "SIP" is increasing drastically to implement low cost, low power and small die
size products.
Figure 1.1 History of Moore's law [61]
1
Figure 1.2 shows the trend in silicon products as of 2005 [60]. Examining this figure
shows that the number of digital content is increasing in the presence of analog/RF and low
power circuitry to achieve "SOC". The increased number of digital gates is accompanied by the
introduction of multi clock domains that can fulfill the signaling requirement. Such environment
generates tremendous amount of interference signals that can couple to the analog/RF and other
sensitive parts of the SOC, and in the presence of a scaled down supply voltage (to cope with the
scaled geometry) the analog/RF become even more sensitive to noise, in addition the noise
margins of the digital gates are also decreased.
Figure 1.2 Trend in Silicon Systems and products [60]
Signal isolation, especially between the digital and analog regions of the chip, is a particular
challenge for scaled technologies and for increased integration complexity. Noise coupling may
occur through the power supply, ground rails and shared substrate. The difficulty of integrating
analog and high-performance digital functions on a chip increases with scaling in both device
geometry and supply voltage. Signal isolation is critical for success in co-integrating high
performance analog circuits and highly complex digital signal processing (DSP) functions on the
same die or substrate. The growth of the personal mobile computers and handheld
2
communications market in recent years has led to a great demand for “SOC” integration.
Functional analog circuits such as PLL, analog-to-digital converters, digital-to-analog converters
and RF circuits are placed on the same die with high speed digital signal processing circuits
containing large number of logic gates. In such an environment, noise disturbances generated by
high switching rates of digital circuits and the presence of strong interference signals between
tightly coupled channels can propagate through the common silicon substrate due to the nonzero
conductivity of the substrate material and couple to circuits located in different parts of the
substrate. The disturbances are, in many cases, significant enough to degrade the performance of
the analog circuits and the sensitive high speed digital interfaces sharing the same substrate.
Certain types of circuits have traditionally been built on separate substrates in order to minimize
parasitic interaction between them, for example low noise amplifiers and switching circuits such
as dividers and high power circuits such as buffers and power amplifiers are traditionally built on
separate substrates. Then a SIP or a “system in package” is designed to build a single chip
“module” to be presented to the end user as a single package solution for integration on the
system board. Such a process although beneficial in many cases adds a huge overhead to project
resources as far as design, validation testing and integration. Integrating high power switching
noise generating circuits and sensitive low noise circuits on the same substrate while avoiding
performance degradation due to substrate coupling is being currently viewed as a major challenge
by circuit and system designers as well as validation and system debug teams.
Higher levels of integration have several associated advantages and disadvantages.
Obvious advantages are the reduced package count and die area. This leads to lowered costs and
reduced sizes. The power dissipation can also be reduced as fewer pads and interconnect lines
need to be driven, thereby avoiding the associated capacitance and parasitic inductance both self
and mutual. It may also be possible to improve the high frequency response of circuits or even
3
extend the frequency range of circuit performance, as the package interconnect parasitics often
degrade the frequency response at the high frequency end of the application.
A major disadvantage of integration is the increased interaction between circuits. This interaction
can appear in two major ways. It can occur due to the significant mutual inductance and
capacitance, which exist between any two bond wires and pins in a package. The second method
for interaction is through the common substrate shared by the circuits.
In this research the problem of substrate coupling is addressed. The goals of this research
are as follows. First is to build a calibrated design flow and develop a substrate design guide that
can be adopted in a production worthy design environment that is capable of designing the
substrate isolation structures and debugging the substrate coupling problems and implement fixes
to such problems on device, circuit and system levels. Second is to design these fixes to take into
consideration design for manufacturing effects. Examples of DFM effects are process skew
variations, temperature variation, and effect of density dummification, wire bonds and C4 bumps.
Such effects are being ignored for a while as being second order effects, but as technology scales
these effects have started to surface as critical issues that must be addressed early in the design
cycle. The objective here is to study the impact of such effects to ensure high resolution
functionality and to eliminate costly reiterations
The sources of coupling are identified in different technologies as well as in various
devices, both active and passive. Then the mechanisms of noise reception and propagation
through the substrate and the problem of efficient modeling of substrate coupling are discussed.
The impact of substrate coupling on circuit behavior is discussed. Experimental results that verify
the design flow will be carried on silicon. In this research different layout and isolation
techniques will be suggested and verified to minimize substrate noise coupling. The third
objective of the research is to study the impact of the substrate characteristics and isolation
techniques on the design of RF passive devices. Precision passive devices are a new demanding
4
challenge for current and future on-chip architectures. The request for high quality capacitors,
inductors and resistors is mainly driven by advanced mixed-signal, high frequency (RF) and
(SOC) applications. In the past, the traditional method of realizing passive circuit elements (for
example, capacitors, resistors) on ICs was integration during front end processing. In this case
doped monocrystalline Si substrate, polycrystalline Si and Si-oxides or Si-oxynitrides are used
[1]. Because of their vicinity to the Si substrate, those passive devices fabricated during front end
processing suffer increased performance degradation especially when used at high frequencies.
Therefore, there is an increasing demand for low loss, low parasitics, but high quality passive
devices in the interconnect levels. A part of this research is dedicated to develop an accurate
inductor design flow that takes into consideration the substrate characteristics, isolation
techniques and design for manufacturing effects. The focus is put on high quality on-chip
inductors as they are critical components in analog/mixed signal and high frequency (RF)
applications. With increasing frequencies, on-chip inductors will gain even more importance in
the future [1], [2], [3]. Currently they are widely used in RF circuits especially for impedance
matching, RF filters, RF transceivers, voltage controlled oscillators (VCO), power amplifiers and
low noise amplifiers. Several design examples are developed in this research relying on the
inductor design methodology that is also developed and adopted to design these structures. The
impact of substrate is highlighted and isolation techniques are implemented. The designed
inductors are selected to span the different flavors of on chip spiral inductors that fit various RF
application needs. The fourth objective is to apply the research learning to real life circuits and
system level problems and demonstrate how to uncover a substrate noise coupling problem, its
impacts and remedies.
1.2.
Contributions
The research objectives are carefully selected to complement the previous work found in the
literature and to provide simulation and measurement based analysis instead of the rule-of-thumb
5
guidelines now used to deal with substrate noise problems found in the literature. The research is
focused on the RF and high speed serial IO link applications and their frequency of operation.
The research contributions are summarized as follows:
•
A substrate aware design flow is build that uses the substrate model kernel extractor that
represents the industry standard. The emphasis is focused on calibrating the flow to the
process technology at hand.
•
The flow is calibrated to silicon measurements, based on a test chip that is designed and
tested for this purpose.
•
The emphasis of this work is put on the RF and high speed serial IO links frequencies
(1~10GHz) vs. the MHz frequency range of applications found in the literature
•
A complete and novel substrate noise isolation design guide is developed based on the
calibrated design flow. The design guide studies various isolation structures in modern
process technologies used for RF and mixed signal ICs, their geometrical and electrical
parameters, frequency of operation, floor plan, power and ground domains design.
•
A design flow is developed to design on-chip spiral inductors based on analytical
formulas found in the literature and an industrial tool used as a 3D full wave field solver.
The flow is calibrated to silicon measurements and is used to study the substrate
parameters and their impact on the inductor performance.
•
The DFM effects are studied that impact the on-chip inductor performance. Such effects
that directly impact robustness and yield.
•
The two design flows are used in the design phase and is applied to three case studies on
device, circuit and system levels where the noise coupling issue is uncovered and fixed.
Simulation and silicon measurements are used to validate the existence of the problem
and to validate the fix implemented.
6
1.3.
Thesis Organization
In chapter 2 the phenomena of substrate coupling is studied. Devices to substrate interface,
noise injection, reception and propagation are discussed in details. The industry standard
algorithms used to model the substrate are studied and compared. The design methodology used
to account for and integrate the substrate model in the design flow is discussed. In chapter 3 our
design experiments are discussed, the test chip is described together with the de-embedding
technique and measurement procedure. The design flow is then developed to model the substrate
and is calibrated to the measurement data and simulations vs. measurements are reported as a
foundation of a design flow that is used in the next chapters. In chapter 4 a substrate isolation
guide is developed based on two main methodologies. First, circuit and layout considerations to
maximize isolation, namely floor planning techniques, power line distribution as well as ground
rails are designed to maximize substrate isolation. Second is the design of isolation structured that
will aid the isolation level. Biasing and sizing of such structures are discussed all are based on the
calibrated design environment developed in chapter 3. In Chapter 5 the learning of the impact of
these isolation structures and the substrate characteristics is used to develop a design flow for on
chip spiral inductors. Measurements to simulations are compared to validate the flow and various
flavors of on chip inductors are designed to fit the needs of several RF applications. A scalable
inductor macro model is developed that is shown to be usable to a very good accuracy across a
wide variety of inductor geometries and frequency bands. DFM effects are studied and their
impacts are highlighted on the inductor performance. Chapter 6 concludes the research by
applying the learning to three industrial case studies. The case studies are designed to gradually
show the impact of substrate coupling on a device, a circuit and then a system. The isolation
techniques developed are applied to the case studies to enhance the performance, simulation and
measurement results are shown with and without applying the isolation techniques and results are
compared.
7
CHAPTER 2
ANALYSIS OF SUBSTRATE NOISE COUPLING
In this chapter the steps needed to prepare the design environment that will be used in the
next chapters to characterize the substrate noise coupling problem are studied. First, the device
models of the process are studied to clearly define the devices-substrate interface. Second, the
noise injection, reception and transmission mechanisms are studied to understand the process
parameters involved and frequency limitation that impacts the coupling phenomena, so that
approximations and justifications can be engineered. Finally, the field solvers are studied and
compared and an industry standard kernel is adopted in our flow.
To set the foundation of analyzing the substrate coupling mechanism a generic cross
section of a modern BICMOS process is shown in figure (2.1). The process is characterized by
regions and cross sections. The motivation behind this diagram is to study where and how the
devices are connected to the substrate and what should be considered part of the substrate model
that is connected to the circuitry and what should be left out from the substrate model since it is
usually accounted for in the device model. Care should be exercised here since failing to make
this distinction may result in double counting junction caps and substrate parasitics or in some
cases missing these parasitics from the model of the entire system completely. In other words at
the interface between the devices and the substrate a clear cut should be made to distinguish
8
between features that are modeled in the front end device models and features that are not and
hence should be part of the substrate model with no features left out and no features accounted for
twice.
In the next section, process regions and cross sections are explained; a BICMOS process is used
since it has both Bipolar and CMOS devices and acts as a superset of process technologies.
Figure 2.1 Cross section of a general BICMOS process
2.1.
Process Regions
Figure (2.1) lists the process different regions as follows
Default: This corresponds to the default p substrate where there is no well implant present.
Devices implemented in this region are NMOS devices.
N-well: This corresponds to the region where an n-well implant has been made to create an n-well
tub for including p-type PMOS devices.
Deep n-well: This region has an n-well implant (similar to the n-well region above) but in
addition to this implant, there is a buried n layer underneath the n-well thus increasing the depth
of the n-well in the substrate. Devices implemented in this region are PMOS devices that need
special substrate isolation.
9
Triple well: This region corresponds to a p-well tub that has been completely separated from the
default substrate region by the presence of the buried n-well structure that forms the floor of the
tub. Devices implemented in this region are triple well NMOS. In addition to noise isolation,
triple well NMOS are usually used to eliminate body effect or back bias by furnishing a dedicated
bulk connection to this transistor that is separated from the rest of the common substrate and
hence can be connected to a dedicated connection without sharing the common substrate
connection. This is used to bias the device in a drowsy mode, which is used for power saving
during stand-by operations. The overhead of such device is both wafer cost and die area.
Sinker: This region corresponds to the n-type buried layer that is contacted through an n-sinker.
This normally occurs in the bipolar transistors.
Deep trench: This region represents the oxide trench that goes deep into the substrate. This is
used primarily for substrate noise isolation.
Passives: This region represents the place where passive devices are implemented on higher level
metal layers. Examples of passive devices are poly resistors, inductors, metal capacitors and
routing interconnects. This region can be combined with the default region where NMOS
transistors are not present.
2.2.
Process cross sections
Seven distinct cross sections are shown in figure (2.1) where the arrows are pointing.
1-Default: This corresponds to the section with no active diffusion implants in the process. This
is the section with only the field thick oxide or Shallow Trench Isolation “STI”.
2-Contact: This cross-section denotes the active diffusions that are bias contacts (substrate and/or
well ties or taps) into the substrate mostly from power and ground supplies (for example P+ ties
in the default region is connected to ground pads, while N+ contacts in the n-well regions will be
connected to power supply pads). In some cases these contacts are also present in well resistors
10
and well capacitors (N+ in n-well) where they are not necessarily connected to power and ground
pads as shown in figure (2.2)
Figure 2-2 Contacts in N-well resistors and capacitors
3-Source drain: This cross-section denotes a p-n junction which is formed by a diffusion implant
in the substrate (P+ in n-well, N+ in default p-substrate). This would be used for connecting to
sources and drains of MOS transistors as well as p-n junction diodes. Note that the source_drain
cross section in the substrate should not include the junction parameters for the p-n junction.
These are obtained from the device models as discussed later in this chapter.
4-channel: This cross-section represents the substrate underneath the gate of the MOS device
under active conditions. MOS devices are connected to the substrate via this cross section and its
bulk terminal.
5-deep_device: This is primarily used to account for devices that include the n-well to substrate
p-n junction inside the device model. Here the profiles representing the substrate start from below
the n-well junction to the bulk substrate.
6-Bipolar: This is used to account for devices that already include the n-buried layer to substrate
junction inside the device model. Here the profile representing the substrate starts from below the
n-buried layer junction to the bulk substrate.
11
7-passives: This cross section lies under passive devices such as inductors and metal capacitors.
In many situations these devices are surrounded by substrate taps or guard rings to isolate the
substrate region under the devices which minimizes noise coupling to/from these devices.
The combination of a region and a cross section denotes a unique profile in the substrate
and this in turn ties to devices appropriately. The following discussion for the different active and
passive devices present in today’s technologies clarifies the connectivity of different devices into
the substrate. First, the regions and cross sections associated with each other are as follows:
Region default can only have these cross sections: default, contact, channel, s/d.
Region n-well can only have these cross sections: default, contact, channel, s/d, deep_device
Region deep_n-well can only have these cross sections:
default, contact, channel, s/d,
deep_device
Region sinker can only have these cross sections: bipolar
Region deep_trench can only have these cross sections: default
Region triple_well can only have these cross sections:
default, contact, channel s/d,
deep_device.
Region passives can only have these cross sections: default, contact
In addition to that, substrate taps (or ties) are extracted as a one pin device (“TIE”). The single pin
of the device is connected to the appropriate supply connection. This is achieved by stamping the
connectivity to the metal layers on top.
Next will be how each device is modeled and how will this impact the connection to the substrate.
For example, the n-well resistor device can have three terminals where the third terminal (“sub”)
is connected to p-sub. This means that the device model includes a diode modeling the n-well to
substrate junction. In this case, the n-well shape associated with this device is taken out from the
n-well region shape output in the substrate model because it is accounted for already in the
model. If the “sub” terminal of the n-well resistor is a contact in the n-well then the substrate
12
model should consider the n-well p-sub junction and its capacitance as part of the substrate model
underneath this device.
2.3.
Connection of devices to the substrate
This section lists the connection between the different types of devices and the substrate.
Some devices are considered directly connected to the substrate while others are indirectly
connected as explained below.
2.3.1. Devices directly connected to the substrate network
MOS devices: These MOS devices are connected to the substrate through the bulk pin “sub” or
“B”. They are connected to the “channel” cross section in the substrate.
Poly Resistors: Since almost all poly resistor models account for the capacitance to substrate and
the substrate network underneath the poly resistors as shown in figure (2.3), these resistors are
connected to the substrate through the bulk pin “B”. These are connected to the “default” or
“deep device” cross section if they are poly over sub or poly over n-well respectively. Same
argument applies to all passive devices, inductors, MIM capacitors, etc.
Figure 2.3 Poly resistor model showing substrate network already accounted for
13
N-well Resistor: The n-well resistor is connected to the substrate through the bulk pin “sub”. This
is connected to the “deep_device” cross section (nwell-sub diode is part of the device model).
Inductors: The inductors are connected to the substrate through the bulk pin “sub”. They are
connected to the “default” or contact cross sections, depends on whether the inductor has a guard
ring TIE around it or not.
MIM Capacitors: The Metal to Metal capacitors are connected to the substrate through the bulk
pin “sub”. They are connected to the “default” or deep device cross section depending if the MIM
is over sub or over n-well (nwell-sub diode is part of the device model).
Poly Gate Capacitor: This capacitor is connected to the substrate through the bulk node “sub”. It
is connected to the “deep_device” cross section (nwell-sub diode is part of the device model).
2.3.2. Devices indirectly connected to the substrate network
The devices diode, bipolar and the varactor are considered indirectly in the substrate network.
These devices always have a guard ring (tied to a supply) around them, so the guard ring is
considered as a TIE which is connected to the substrate network via the default cross section.
Now that the device models are studied and a decision is made to identify the devicessubstrate interface, substrate is modeled separately as a semiconductor medium and then its
model is connected back to the circuit to create a netlist with the substrate modeled. Figure (2.4)
shows a methodology for such separation.
Figure 2.4 device models must be studied to accurately separate devices from the substrate
14
2.4.
Noise coupling mechanism
Three processes act sequentially to complete the substrate noise coupling phenomena.
First the noise currents are injected from the devices into the substrate through the devicessubstrate interface, and then noise propagates through the substrate medium to reach other
locations on the same substrate. The nature of such propagation depends on the substrate
resistivity and isolation structures implemented as well as grounding techniques and frequency of
operation. Finally the substrate noise is received at the sensitive circuit node, where it modifies
device characteristics. The challenge of modeling the substrate coupling is therefore a three-fold
issue. Modeling of the injection mechanisms, substrate medium and the reception mechanisms is
required to accurately analyze substrate coupling. Injection and reception mechanisms are
modeled within the device models. The modeling of the substrate medium is provided separately.
In this section, we will discuss substrate noise injection, propagation and reception mechanisms.
2.4.1. Substrate Noise Injection Mechanisms
In mixed signal designs, devices induce currents in the substrate through several
mechanisms. The most dominant are diffusion capacitive coupling, impact ionization and
inductive coupling due to power grid fluctuations at substrate contacts with power and ground
lines. According to [5], there are other less significant mechanisms through which currents are
injected to the substrate, gate-induced drain leakage (GIDL) due to the gate induced barrier
lowering, photon-induced reverse current and diode junction leakage current. The effects of these
mechanisms are negligible compared to the above mentioned ones. They become only significant
under certain bias conditions not applicable to the majority of applications, thus we will not focus
on such effects in our analysis.
15
2.4.1.1.
Noise Injection through Capacitive Coupling
An important mechanism by which noise is injected to the substrate is capacitive
coupling. Devices inject currents into the substrate through the p-n junction depletion capacitance
of drain and source regions or collector regions to substrate Cjs.
Cjs =
 N1N 2 
qε


2(ψ + Vb )  N1 + N 2 
………..
2.1
Where Cjs is the capacitance per unit area of the abrupt p-n junction, q is the charge of an
electron, ε is the Si dielectric constant, ψ is the junction built in potential, Vb is the magnitude of
the reverse bias voltage, N1 and N2 are the doping concentration of the p and n regions of the
junction.
The strength of the coupling is dependent on the device size and the switching
frequency. As technology feature size is reduced, the doping concentration of the diffused regions
is increased to avoid total pinch-off effect. Higher doping concentration leads to higher depletion
capacitance and therefore lower capacitive impedance from the diffusion regions to the substrate
and hence more coupling effects. Note that this capacitance is always included in circuit
simulators such as SPICE as model elements "CJ0" and "CJSW" (these are the source/drain-tosubstrate capacitance). Figure (2.5) shows a few types of devices-to-substrate capacitive coupling.
Other than the p-n junction capacitive coupling, passive devices like resistors, capacitors and
inductors can also capacitively induce current into the substrate. Resistors in modern processes
are either poly-type or diffused. Poly resistors have a comparatively smaller parasitic capacitance
to the substrate Thus diffusion resistors inject more noise into the substrate than poly resistors for
the same dimensions.
16
Figure 2.5 device to substrate capacitive coupling
Capacitors can be either metal-to-metal, or poly-to-substrate types. Metal-to-metal capacitors
have the largest ratio of the parasitic capacitance to the substrate for a given capacitance. Hence if
these devices are used for implementing large on-chip capacitors, they can act as significant
substrate noise-injectors. On-chip inductors and interconnects inject noise into the substrate
through the parasitic oxide capacitance with the substrate. The substrate parasitic can lead to
lowering of the inductor quality factor. Thus the substrate loss must be modeled to obtain an
accurate prediction of inductor performance as discussed in chapter 5.
2.4.1.2.
Noise Injection through impact ionization
As transistor feature sizes are being reduced, the electric field in the channel increases
and therefore impact ionization currents are becoming more significant compared to other
injection mechanisms. When MOS devices are biased in saturation regime, a high electric field in
the depleted region of the channel is formed near the drain. Due to the high electric field, impact
ionization takes place when “hot” carriers dissipate their excess energy via collision generating
electron-hole pairs. For a p-type substrate, in case of NMOS transistors, the generated holes are
swept to the substrate generating an effective drain to-substrate current [5]. For PMOS transistors,
the impact ionization current is less due to the lower hole mobility. In addition, PMOS transistors
are physically located inside n-well regions. The well junctions serve to reduce coupling of
currents to the surrounding p-type substrate due to its capacitive impedance. Thus it may be
17
expected that PMOS devices cause lower substrate bounce than comparably sized NMOS
devices. This is indeed the case as long as the n-well has a very low impedance ac ground contact.
If the well potential is allowed to vary with respect to the substrate potential, the well acts as a
large injector, with a large reverse biased well to substrate capacitance and can cause significant
substrate noise injection. The impact ionization substrate current dependence on the transistor
drain current is given by the following semi-analytical expression [6]
 − K2 
Isub = K 1(Vds − Vdsat )Id exp
 ………..
 Vds − Vdsat 
2.2
Where Id is the drain current Vds is the drain to source voltage and Vdsat is the drain to source
voltage at saturation. K1 and K2 are empirical constants. K2 depends on the oxide thickness tox and
the drain junction depth xj as
K2 α tox 1/3 xj 1/2 ………..
2.3
This phenomenon is discussed extensively in [6]. It is derived by considering the exponential
dependence of the carrier ionization coefficients on the electrical field in the channel. Integrating
the substrate current generated per unit length over the length of the channel results in eq. 2.2.
Recent experimental evidence suggests that hot-electron induced substrate currents are the
dominant cause of substrate noise in NMOSFETs up to at least one hundred megahertz [7].
Shorter device channel lengths in future technologies are likely to increase the impact ionization
currents due to increased channel fields and smaller tox and xj.
The nature of current injection due to capacitive coupling and impact ionization induced
currents is different because hot-electrons induced currents are always injected into the substrate
irrespective of the polarity of the injectors. In a switching CMOS inverter, hot-electrons induced
current will be injected into the substrate during both the 0-1 and 1-0 transitions, while the
capacitive component of the current will reverse direction during the two edges. As a
consequence, hot-electron induced currents will possess large even-harmonics of the fundamental
18
switching frequency and a DC component. On the other hand, the capacitive currents will possess
large odd-harmonics and no DC component. Thus careful circuit design such as differential
circuit techniques can minimize the even-harmonics and decrease the impact ionization
component. The presence of a DC component in any substrate current can be potentially very
harmful to circuit operation. In addition to causing a drift in threshold voltages, it can also lead to
an increase in minority-carrier injection into the substrate due to partial forward-biasing of
device-to-substrate junctions. This leads to severe degradation in the circuit performance or in
many cases a malfunction.
For small-signal analysis, the effect of the hot-electron induced current can be modeled as
a drain-to-body transconductance gdb [8] given by
gdb =
∂Isub
K 2 Isub
=
………..
∂VD (Vds − Vdsat )2
2.4
The major effect of this parameter on small-signal circuit analysis is that this term appears in
parallel with the ro of the device and tends to lower the output impedance of the transistor in
saturation hence lowering its gain in saturation.
2.4.1.3.
Noise Injection due to Power Grid Fluctuations
Due to parasitic effects associated with the package, mainly bond wire inductance, power
supply lines become very noisy because of currents drawn by the switching digital circuits. These
currents induce large voltage glitches when they switch (Ldi/dt noise) at substrate and well
contacts. This represents a significant amount of noise injection into the substrate depending on
the switching speed and the availability of other noiseless substrate ties. In addition, the power
grid noise can be also capacitively coupled through metal-to-substrate parasitic capacitance.
Figure (2.6) shows a cross section of a packaged chip and the coupling between bond wires.
19
Figure 2.6 cross section of a packaged chip showing bond wire noise
2.4.2. Substrate Noise Reception Mechanisms
The reception of noise by most devices on the silicon surface takes place through
capacitive sensing. This is true for BJTs, resistors, capacitors and interconnects lines. For MOS
transistors, noise couples through drain and source junctions. For devices like diffusion resistors
and well-to-poly capacitors, the noise is coupled through the well junction capacitance. Because
junction capacitances are typically small, capacitive coupling effects become significant only at
high frequencies. Metal interconnects and poly resistors are also capacitively linked by oxide
capacitance to the substrate. Substrate noise can also indirectly affect the circuit performance
through the package and interconnect parasitics, ∆I noise across bond wire inductance may cause
serious performance issues.
In addition to capacitive pickup through the source and drain depletion junctions, MOS
devices also exhibit a more severe form of substrate interaction due to the body effect. The
threshold voltage of a MOS transistor is a relatively strong function of the substrate potential. For
a uniform surface impurity concentration, the dependence of the threshold voltage is given by [8].
Vt = Vt 0 + γ
(
2φf + Vsb − 2φf
)……..
2.5
Where Vto is the threshold voltage at zero source-to-bulk bias γ is bulk threshold parameter and
φf is the surface inversion potential. The change in threshold voltage has a direct effect on the
drain current Id through the following equation:
20
Id =
KW
(Vgs − Vt )2 ………….. 2.6
2 L
The dependence is represented as gmb, the bulk-to-source small-signal transconductance gmb
gmb =
∂Id
γ
= gm
…………. 2.7
∂Vbs
2 2φf + Vsb
Where gm is the gate-to-source transconductance at the same operating point. In typical processes
the ratio (gmb/gm) varies from 0.1 to 0.3. The parasitic body-to-source gain is thus lower than the
gate-to-source gain by a factor of 14-20 dB only. The body effect in MOSFETs makes these
devices especially vulnerable to substrate noise reception. While the capacitive pickup exhibited
by most devices becomes significant only at high frequencies, the body effect can be an issue at
low frequencies.
2.4.3. Substrate Noise Transmission Mechanisms
Substrates act as the media for coupling of noise from one device to another. Thus in
order to understand the phenomenon of substrate coupling, it is essential to study the nature of the
substrate as a transmission media and the process technology parameters that affect that as well as
the frequency impact on the behavior of the substrate as the transmission media.
Since the substrate acts as a lossy dielectric, a derivative of Maxwell’s equations shown below is
applicable to the substrate [27]
J = (σ + jωε Si )E ………..…. 2.8
Where J is the current density in the substrate (A/cm2), E is the electric field (V/cm), σ is the
conductivity (S/cm) and εsi is the dielectric permittivity of silicon (εo 8.854e-14 * εr 11.7 F/cm), ω
is the frequency in rad/s. The substrate impedance and the behavior of the substrate as a noise
transmission medium are frequency dependent. As long as σ >> ωε Si the current in the substrate
will be dominated by the resistive nature. At low frequencies, dielectric capacitive behavior of the
21
substrate is insignificant and hence, it can be considered merely as a resistive medium. This
assumption is valid below a certain cut-off frequency fc given as [9]
fc = 1 / (2πρsubεsi) …………. 2.9
Where ρsub is the resistivity of the substrate. Figure (2.7) shows a plot between the substrate
resistively ρ = 1/σ and the frequency at which σ = ωε Si called the cutoff frequency fc.. For ρsub
=10 Ω-cm, the substrate can be considered as a resistive medium below 15 GHz. Thus for most of
the cases in this research the substrate medium is treated as a resistive medium except in some
specific conditions that will be highlighted where they fit.
cut off freq vs. substrate resistivity
80
cut off freq vs. substrate
resistivity
cut off frequency (GHz)
70
60
50
40
30
20
10
0
0
10
20
30
40
50
60
substrate resistivity (Ohm-cm)
Figure 2.7 Substrate cut-off frequency fc as a function of resistivity ρsub
The above model considers current flow only due to drift (field induced) currents. This model
would be sufficient for low-level majority-carrier conduction. Minority-carriers, once injected
into the substrate, can exist for long periods of time (carrier lifetime) and cause significant local
variations in conductivity. However a large injection of minority-carriers into the substrate
22
usually indicates a fault condition, as this occurs when a device-to-substrate junction is turned on.
Hence to model substrate cross-talk we only consider the drift-induced substrate currents.
2.5.
Substrate doping profile tradeoffs
Conductivity is the parameter that determines the nature of the noise transmission media
in the substrate. The conductivity σ depends on the carrier concentration “p” and the hole
mobility “µp” and hence is a function of the doping profiles in the substrate. Substrate coupling
depends on the type of the substrate whether it is lightly-doped or heavily-doped. Intuitively, the
higher the resistivity of the substrate the lower the noise coupling will be. Tradeoff between noise
coupling, latch up effects and wafer cost is what dictate the wafer doping profile of different
process technologies based on the target application. The modern process technologies are
categorized into three main types. First, the memory and RF processes with a high resistivity
substrate (all TSMC and UMC processes [10], [11]). Second the digital CMOS processes with a
low resistivity substrate and a high resistivity epitaxial layer (option for all TSMC and UMC,
STMicro, IBM [10], [11], [12], [13]). Third, the bipolar processes with high resistivity substrate
and epitaxial layer and low resistivity buried layers (IBM, STMicro [12], [13]). High resistivity
substrates are used for RF application since noise isolation is critical as well as to minimize eddy
currents in the substrate and hence enhance the quality factor of all the passive devices built on it
that are critical for RF applications. Many CMOS fabrication processes today use a lightly doped
epitaxial layer grown on top of a heavily doped bulk substrate. The lightly doped epitaxial layer
provides a tightly controlled level of doping for device performance, while the low resistivity of
the heavily doped bulk helps to prevent latchup. The buried layers are usually low resistivity players at the top of the substrate that prevents inversion of the bulk regions outside the transistor
channel areas.
23
2.6.
Substrate Model extraction in the IC design flow
In the circuit design flow, the substrate model is in the form of a sub-circuit RC network
that represents the substrate. The resulting substrate model is considered an additional subsystem
to be electrically linked to the original design that assumes no substrate coupling. The substrate is
represented by a linear multi-port network figure (2.8) and the role of the substrate model is to
extract the admittance/impedance matrix elements representing the electrical behavior of the
substrate. The substrate model acts as a transfer function between the noise sources and the
sensitive circuits. The electrical behavior of the substrate transfer function is determined by the
process parameters, layout and substrate impedance to ground. For high-resolution analog
circuits, the substrate transfer function is designed to strongly attenuate noise injected by digital
circuits. This can be achieved by careful layout design such as the placement of carefully
designed guard rings as will be discussed in chapter 4.
Figure 2.8 Substrate as an undesired noise transfer medium
2.7.
Doping Profile Considerations
In order to model the effect of substrate coupling, doping information is required to
calculate the resistivity of the silicon at different points. Doping profiles for a certain process can
be obtained either by physical measurements on fabricated wafers or through accurate computer
device simulators. For every process technology, there is more than one doping profile at
24
different regions of the fabricated devices. In order to simplify the substrate-modeling problem,
the doping profile at each device region is approximated by a stack of uniformly doped layers of
silicon [14]. The doping concentration of each layer is the mean of the non-uniform doping
profile within that layer. This process is called profile discretization as shown in Figure 2.9. As
the number of layers increases, a more accurate substrate model can be obtained, however there is
Figure 2.9 Disretization of substrate doping profiles
always the trade-off between the accuracy and performance of the modeling tool. Depending on
the process, modeling engineers could find a suitable refinement level at which the accuracy is
acceptable within a reasonable time frame. The discretizations of doping profiles and resistivity
setting are determined based on calibrating the modeling tool to Si measurements as preprocessing steps upon which a process specific technology file is produced in our model strategy.
2.8.
Substrate model extraction kernels
Different techniques had been be employed in the literature to solve the equations
governing the physical problem of the substrate coupling, and then to represent it as an equivalent
matrix of admittances (or impedances) connecting the terminals (ports). The most common
approaches use the Finite Difference techniques and the Boundary Element Method (Green’s
function is evaluated). With the discretization of doping profiles mentioned before, the substrate
25
can be treated as a stack of uniformly-doped layers. In these layers, a simplified form of Maxell’s
equations, that ignores the influence of the magnetic fields, can be formulated as [15]:
ε.
∂
(∇.E ) + 1 ∇.E = 0 ………..
∂t
ρsub
2.10
Where E is the electric field intensity vector, and ρsub and εsi are the sheet resistivity and the
dielectric constant of the silicon respectively. Equation 2.10 can be discretized on the substrate
volume either in differential form using the Finite Difference (FD) techniques or in integral form
using the Boundary Element Methods (BEM). In general, the discretization process leads to a
large matrix representing the coupling in the substrate, which can be reduced to a simple
equivalent macro-model connecting the substrate sub-system ports. Before matrix reduction, the
Finite Difference method produces a large sparse matrix regardless of the number of the substrate
ports. Integral approaches, such as using the Boundary Element Methods, produce a matrix size
that is proportional to the number of ports. Although the matrix size is much smaller in BEM, the
matrix is very dense and must be inverted, a rather computationally intensive process [16]. Hence
there is a compromise between accuracy and complexity in the two famous techniques found in
the literature. The industry standard tool used in the research uses the finite difference method.
2.8.1. Finite Difference method
Extraction of the substrate macromodel requires the solution of the Laplace equation in
the substrate. Solution of partial differential equations by the use of numerical techniques has
been studied extensively and has been presented by several authors ([17], [18]). These techniques
usually involve approximating the differential equations of the system by difference equations.
The resulting matrix is then solved using a method, which is appropriate for the matrix size
involved. One of these methods is the finite difference technique. The Finite Difference approach
is widely used in modeling the substrate behavior [19], [20]. In this approach, the silicon substrate
26
is modeled as a three- dimensional resistor mesh. Layers of the doping profiles, combined with
the device layout geometrical structures, constitute a matrix of cubiods as shown in figure 2.10.
Figure 2.10 representing a substrate by a mesh of resistors
Every cuboid is modeled as a resistor in parallel with a capacitor [21]. The values of the resistors
in the mesh are determined from the process information (layer sheet resistivity or doping
density) and the geometry defined by the layout. As indicated earlier, the capacitance can be
neglected except for the well-to-substrate junction capacitance. The resulting resistance mesh
interconnects the substrate ports and models the electrical behavior of the substrate. The 3D mesh
network connecting the ports of the substrate can then be reduced and translated into a SPICE
sub-circuit consisting of resistors mesh. The sub-circuit could be used to simulate the substrate
coupling using a typical circuit simulator such as SPICE3. Being a purely numerical technique,
the accuracy of the obtained solution is highly dependent on the resolution of the discretization
[22]. Because of its accuracy at high resolutions, the FD method is useful for high accuracy with
complex substrate profiles, where analytical methods can be rather complicated [23], this is why
this method is used in the industry standard tool extracting the substrate model.
27
2.8.2. Boundary Element method
The Boundary Element Method of extracting the substrate resistances is an analytical
method that starts with discretizing each port on the substrate into a collection of panels [24].
This method is based on using Green’s function of the substrate. The Green’s function for a
medium is defined as the potential at any point in the medium with suitable boundary conditions
due to a unit current injected at any point within the medium [24]. The Green function can be
analytically determined for the substrate as in [25]. Using Green’s function of the substrate, the
impedance matrix representing the substrate behavior is analytically evaluated. The impedance
matrix is then inverted to obtain the substrate admittance matrix [22], [26]. The substrate
resistance between the ports is then obtained as the reciprocal of the sum of the corresponding
admittance matrix elements. A major advantage of the BEM is that it is not as sensitive to
discretization as the Finite Difference technique. As mentioned earlier, the resulting matrix of
BEM methods is much smaller; however, the computational advantage of having a dramatically
smaller matrix is limited by the fact that the impedance matrix to be inverted is fully dense
(unlike the sparse matrix generated by FD method). If heuristics are further employed, the
resulting matrix may be sparsified.
2.8.3. Comparison between the two Techniques
Two techniques have been presented in the literature for computing the substrate macromodels. The first technique is purely numerical while the second utilizes a combination of
numerical and analytical methods. The primary advantage of the second technique is the speed of
computation, which was found to be significantly superior to the numerical technique for small
structures. The computation time in the numerical scheme is small for a small number of grid
points, but becomes large as the number of points is increased. For achieving good accuracy, the
memory requirement of the numerical technique is seen to be very large. An advantage of the
purely numerical technique is its versatility. The technique can be used to model lateral variations
28
in resistivity without any overheads, unlike the analytical method. The power of the analytically
based technique lies in the fact that meshing needs to be done only in the region of the contacts,
not in the bulk unlike the FD method that is applied to the 3-D substrate. Hence BEM reduces the
problem from a 3-D problem to a 2-D problem. In the analytical technique the number of mesh
points rises rapidly with the number of contacts. Another disadvantage of the numerical technique
is that for optimization, if a single contact is varied, then the entire problem has to be recomputed.
This is not a problem with the BEM.
2.8.4. Approximations in the Model Extraction Algorithm
Trade-offs between accuracy and simulation time are inevitable, as low computation
times are usually achieved by ignoring some of the second order effects in the simulation. In the
modeling technique a lumped equivalent macromodel representing the substrate is extracted by
solving the differential equations representing the medium. The lumped macromodel relates the
voltage and the current vectors at the substrate contacts. Several approximations must be made in
order to extract the macromodel in a reasonable amount of time. The approximations involved,
their validity and the point at which the approximations fail are discussed below.
2.8.4.1.
The Electrostatic Assumptions
The first approximation involved is that of considering the substrate as a resistive only
media with no capacitance and inductance effects as discussed in section 2.4.3. This
approximation is accurate at low to moderate frequencies but it fails at frequencies above ~15
GHz in typical silicon substrates of approx 10 Ω-cm. Another side of this approximation is to
ignore any radiation and wave phenomena in the substrate; this is valid in integrated circuit
substrates because the dimensions of the substrates are typically much smaller than the smallest
electrical wavelengths, thus distributed effects are not observed in the substrates. Above these
frequencies complete solution of Maxwell’s equations is necessary. Another deviation from the
electrostatic model will occur when the vertical dimensions of the substrates become comparable
29
to the skin depth in the medium. The skin-effect makes the resistance between two contacts on
the surface frequency-dependent. The computational simplification achieved from the
electrostatic assumption is enormous. Solution of the Maxwell equations in the substrate involves
the solution of two inhomogeneous wave equations [27]. In the electrostatic approximation the
scalar potential in the substrate satisfies the Laplace equation, and very efficient numerical
techniques for parasitic extraction can be developed. The key inference is that the low frequency
formulas suffice for first-order impedance estimates at most frequencies of interest.
2.8.4.2.
The Linearity Assumption
The conductivity of the silicon substrate is dependent on the electric field in the substrate.
Thus the current-field relationship is nonlinear in silicon. This effect becomes significant at
high-fields or at high current densities. The injection of minority-carriers can also make the
conductivity time, location and field dependent. The minority-carrier leakage is avoided by
reverse-biasing the devices-substrate junctions. The conductivity of the silicon layers is assumed
to be a constant, independent of the field. It is also assumed to be isotropic. Several nonlinear
effects are considered in device simulators. These tools, however, are completely unsuitable for
parasitic extraction due to the large computation times involved in even one or two devices
problems.
2.8.4.3.
The Equipotential Assumption
The devices-to-substrate junctions are treated as equipotential contacts with the surface.
A more accurate model of the junction would consider the devices-to-substrate junction as a
depleted semiconductor region (a dielectric). This model is difficult to implement in a fast
substrate noise simulator, since the extent of the depletion region depends on the voltage across
the junction. The magnitude of the error from this approximation is reduced considerably due to
the small dimensions of the devices compared to the substrate. Thus, while the instantaneous
variations of the voltage across the reverse-biased junction may change the value of the depletion
30
capacitance considerably, the change in the value of the substrate model impedance values is
expected to be small. The nonlinear behavior of the junction capacitors is included in circuit
simulators such as SPICE.
2.9. Conclusion
In this chapter the device models are studied to accurately identify the devices-substrate interface.
The injection, reception and transmission mechanisms in the substrate are studied together with
the solvers that are used for extracting the substrate model.
31
CHAPTER 3
EXPERIMENTAL DATA TO CALIBRATE THE DESIGN FLOW
3.1.
Introduction
In the previous chapter the ingredients of a design flow that models the substrate noise
coupling phenomena are studied. The design flow put together is summarized in figure 3.1. It
starts by defining the devices-substrate interface and integrating this in the runsets (rule files)
used for layout vs. schematic check and layout parasitic extraction. The rule files decides based
on the substrate-devices interface what to include in the substrate model and what to leave behind
as part of device models. The layout data is used to identify the geometries, interconnectivity and
location of the devices and the substrate isolation structures that are designed. The process stack
information and doping profile are another input to the solver. The above mentioned inputs are
fed to the substrate model extraction kernel. A commercially available tool [58] that represents
the industry standard is used as the extraction kernel. Figure 3.2 shows the test bench used to
simulate the isolation structures with the substrate RC model as part of this test bench. The test
bench has two signal ports for the two port single ended scattering parameters simulation that is
performed on the substrate model. The substrate model is extracted based on the layout structures
that are presented in the next section. To calibrate this design environment a test chip is designed
and measured to compare silicon measurements to the simulation results and ensure that the
design environment used is accurately predicting silicon behavior. Once this calibration is done
32
the use of the design environment and substrate model extraction and simulations will be
extended to other isolation structures to come up with a design guide for substrate noise isolation
using circuit techniques, floor planning and substrate isolation structures. Then the environment
will be used to assess the impact of substrate noise on device, circuit and system levels. Remedies
are then given based on the design guide. Next, they are validated to ensure that the impact of
substrate noise coupling on the circuit performance is minimized.
Figure 3.1 The Design flow used to characterize substrate noise coupling
Figure 3.2 the test bench used to simulate the substrate model of the isolation structures
33
3.2.
The test chip
A test chip is designed taped out and measured to assess the impact of different substrate
isolation techniques on the substrate noise coupling. The substrate isolation (or crosstalk)
characterization is performed on a high resistive substrate of a BICMOS process wafers with a
substrate resistivity of 10Ω-cm. The test chip used for this characterization contained various
substrate crosstalk reduction structures. The purpose of this test chip is to calibrate the design
flow used to model the substrate network to silicon data and not to measure all the various
options of the substrate isolation structures which occupy large die area. Thus, a limited set of
structures are designed and measured that scans the process technology features used for
isolation, while different sizes and geometries are deferred for being simulated using the
calibrated design flow. The frequency characteristics of substrate isolation structures are a
function of their vertical and lateral constructions. The vertical construction parameters include
substrate resistivity, doping profile, wafer thickness, and thicknesses of all the process wells (nwell, deep n-well, p-well). The lateral construction parameters include the isolation structures
between the two circuit blocks that acts as the receiver and the transmitter of the substrate noise
and their geometries and relative location on silicon. A gold ohmic-contact was made to the back
surface of the die and was connected to the measurement system ground during the testing. The
inductance used in the simulations for the backplane contact to match the measurements is
0.01nH. The different lateral isolation techniques are discussed in the next sections.
Figure 3.3 shows the die photograph of the test chip. The test chip has on wafer probing
RF GSG (ground-signal-ground) pads that are used to measure the scattering parameter of the
substrate structures vs. frequency. The scattering parameters vs. frequency are measured using a
probe station, RF probes and a 40GHz network analyzer. The probe pads are designed as two port
single ended structures and in some cases an extra DC probe pad is used to bias the different nwells used. The probe pads de-embedding structures are also designed and measured to isolate the
34
pads and feed lines parasitics from the total scattering parameters and extract the substrate
structures contribution alone. The de-embedding technique used in measurement is explained
later in this chapter, while the measurement setup is discussed in appendix B. The calibration is
done by tuning the doping profile of the various isolation structures to match Si data. The
structures are designed in a modular way to tune the doping concentration of a single implant at a
time. For example baseline isolation is used to tune p-sub concentration; p+ guard ring isolation
is used to tune the doping of the p+ implant used in the guard ring and so on.
Figure 3.3 die photograph of the test chip used to measure the isolation of different substrate
structures
3.3.
Baseline Isolation
To start with baseline information, the isolation between two p+ diffusion regions is
measured. This information will be used to compare the isolation of the different isolation
structures to the bare silicon isolation due to the distance between the noise transmitter and the
noise receiver. The layout used for the baseline isolation is shown in figure 3.4. The ground “G”
pads are tapped to the substrate and to the measurement system ground. The “G” pads are
connected together in both X and Y directions to form an equipotential surface that ensures
accurate measurements. Without such connection the measurements were too noisy. The ground
35
connection in the Y direction is done using top metal layers, while that in the X direction is done
using lower level metals as shown by the yellow line joining the ground pads in figure 3.4. This is
done to prevent shorting to the signal “S” pad which is put on the top metal layer to minimize its
parasitic capacitance to the substrate. The feed lines connect the receiver and the transmitter to
the signal “S” pads. The resistance of the feed lines and their vias together with the pad parasitic
capacitance are de-embedded to get the isolation information of the receiver and transmitter only.
Two ports single ended s-parameter measurement is done and the isolation S12 in dB vs.
frequency after de-embedding is shown in figure 3.5. The simulation result is overlaid on the
measurement in figure 3.5 after tuning the doping concentration fed to the solver to match the Si
data. The S12 values shown below are based on a setup where port 1 is the receiver while port 2
is the transmitter as shown in figure 3.2.
3.3.1. Data analysis
Both the receiver and the transmitter are p+ diffusion regions in a p-well substrate, thus they
both have ohmic contact to the substrate. Since the substrate used has a resistivity of 10 Ω.cm it
will behave as a resistive network up to the cutoff frequency as discussed in section 2.4.3. Thus,
the equivalent model between the receiver and the transmitter is all resistive and the S12 data
looks pretty much constant up to ~15GHz, as expected from an all resistive mesh. Beyond this
frequency which is identical to the cutoff frequency plotted in figure 2.7, the isolation behavior
starts to depart from a resistive behavior and it starts to decrease with increasing the frequency
due to the contribution of the distributed RC network that will now represent the substrate. The
existence of capacitive impedance in the substrate due to the non-zero permittivity and the ωε
term in equation 2.8 will cause a drop in the isolation as frequency increases. The simulation
results match the measurement up to 20GHz then it starts to deviate beyond 20GHz but remains
well within 0.8dB of accuracy on the pessimistic side up to 30GHz.
36
Figure 3.4 Layout & cross section of the structure used to measure and simulate the baseline isolation
Baseline Isolation
-20
-21
Basline_isolation_meas
-22
Basline_simulation
S12 (dB)
-23
-24
-25
-26
-27
-28
-29
-30
0
5
10
15
20
25
freq (GHz)
Figure 3.5 measurement vs. simulation for baseline isolation structure
37
30
3.4.
Effect of p-guard ring on isolation
The first isolation structure to be studied is the p+ guard ring surrounding the p+ diffusion
that acts as the receiver. Figure 3.6 shows the layout and the cross section of the isolation
structure. The p+ ring surrounds the p+ diffusion that acts as the receiver. The guard ring is
connected to the ground pads using a low ohmic contact connection as shown by the yellow
connection in figure 3.6. This ground connection is needed for the ring to act as a sink to the
substrate noise currents. A very low ohmic contact to the ground connection is needed to ensure
strong current sink. The layout is also used to serve the purpose of measuring the substrate
isolation if the guard ring surrounds the transmitter. This is achieved by also monitoring S21 in
addition to S12, i.e. flipping the roles of the noise transmitter and noise receiver during the
measurement can achieve this goal. Adding a second guard ring to simultaneously surround both
the transmitter and the receiver can be tricky. The reason is that both guard rings have to be
grounded to sink the substrate noise current and if they are both tied to the same ground node, this
can create a short circuit path to the substrate noise current as shown in figure 3.7. If Zsh<<Zgnd
adding a guard ring around the transmitter will increase noise coupling to the receiver, as shown
in figure 3.7 left hand side diagram. If on the other hand the two guard rings are tied to two
separate ground nodes, isolation is enhanced as shown in figure 3.7 right hand side diagram.
Figure 3.8 shows the measurement and simulation results of the above mentioned scenarios. The
simulation tracks the measurement data fairly well up to 20GHz, and then deviates to be within ~
2 dB from the measurement data up to 30 GHz. In the next chapter the simulation results
comparing the different ground connections of figure 3.7 will be discussed.
38
Figure 3.6 Layout and cross section of the structure used to measure and simulate the p+-guard ring
isolation structure
3.4.1. Data analysis
The isolation provided by the P+ guard ring is superior to the baseline isolation by
approximately 30 dB. The p+ guard ring can effectively eliminate the surface noise current flow
by sinking this noise current to the low ohmic ground connection. As mentioned in the previous
section, since p+ guard ring acts as a resistive network due to its ohmic contact to
the substrate and the substrate behavior is resistive up to the cutoff frequency, the isolation is
approximately constant “within 2 dB” up to 15 GHz, then starts to degrade with frequency due to
the capacitive behavior of the substrate beyond the cutoff frequency.
39
Figure 3.7 careful grounding is needed not to increase substrate noise coupling
S12 p+_ring around rec
S21 p+_ring around trans
p guard ring isolation
-50
S12_p_guard_ring_m eas
S12_p_guard_ring_sim
S21_p_guard_ring_m eas
S12 (dB)
-55
S21_p_guard_ring_sim
-60
-65
-70
0
5
10
15
20
25
30
freq (GHz)
Figure 3.8 p+_guard ring isolation once surrounding the receiver and once surrounding the
transmitter
40
Comparing the scattering parameters shown in figure 3.8, it is obvious that adding P+ guard
ring contact to surround the noisy circuit block “transmitter” is a more efficient technique to
reduce substrate crosstalk. The isolation in this case is larger than the case of the p+ guard ring
surrounds the receiver by approx 2.5 dB. Putting the p+ guard ring immediately surrounding the
noisy circuit attenuates the substrate current before it propagates through the substrate to other
locations in the system where it is attenuated further by the distance isolation of the high resistive
substrate. Also the impedance of the guard ring connection to ground can pick up substrate noise,
specially at high frequency and putting the guard ring around the receiver degrades the isolation
by injecting this picked up noise into the receiver, while putting it around the transmitter leaves
room for the residual noise that is not sunk to ground due to this impedance to be attenuated by
the distance isolation in the high resistive substrate.
3.5.
Effect of n-guard ring on isolation
The p+ guard ring in the previous section is compared to an n+ diffusion guard ring in an nwell ring isolation structure in this section. The layout of such structure is shown in figure 3.9.
Two n-guard rings are placed around the receiver and the transmitter. Here two extra DC probe
pads are needed to bias the n+ guard ring by DC supplies to create a reverse bias p-n junction
between the n rings and the p substrate. The structure can be used to measure the impact of a
single n ring around the receiver by keeping the n ring around the transmitter floating and
connecting that around the receiver to vdd1, which will act as an ac ground to sink the substrate
noise current. It is also used to measure the impact of a single n ring around the transmitter by
keeping the n ring around the receiver floating and connecting that around the transmitter to vdd2.
If both n rings are simultaneously connected to vdd1 and vdd2 respectively, the impact of two
rings is measured and compared to the above mentioned two cases. Figure 3.10 shows the
measurement data for the three cases. Figure 3.11 shows the simulation results overlaid on the
measurement. A good fit is obtained between measurements and simulations up to the cutoff
41
frequency then a deviation occurs within 2 dB error between measurements and simulations. At
such level of isolation ~65dB, 2dB is considered within measurement error. Figure 3.12 compares
the p+ guard ring and he n+ guard ring isolation technique in all of their configurations.
Figure 3.9 Layout and cross section of the structure used to measure and simulate the n+-guard ring
isolation structure
n guard ring Isolation
-60
-65
S12 (dB)
-70
-75
-80
-85
one n guard ring @ rec m eas
tw o n guard rings m eas
-90
one n guard ring @ trans m eas
-95
-100
0
5
10
15
20
25
freq (GHz)
Figure 3.10 measurement data for n+_guard ring isolation structure
42
30
n guard ring Isolation
-60
-65
S12 (dB)
-70
-75
-80
one n guard ring @ rec m eas
-85
one n guard ring @ rec sim
tw o n guard rings meas
-90
tw o n guard rings sim
one n guard ring @ trans meas
-95
one n guard ring @ trans sim
-100
0
5
10
15
20
25
30
freq (GHz)
Figure 3.11 measurement vs. simulation for n+_guard ring isolation structure
Comparing Isolation techniques
p guard ring @ rec
one n guard ring @ rec
p guard ring @ trans
one n guard ring @ trans
-60
-61
-62
S12 (dB)
-63
-64
-65
-66
-67
-68
-69
-70
0
5
10
15
20
25
freq (GHz)
Figure 3.12 comparison between isolation techniques
43
30
3.5.1. Data analysis
The p-n junction between the n guard ring and the p substrate introduces high capacitive
impedance at low frequency. This high impedance reduces substrate noise current reaching the
receiver. This is shown in figure 3.10 by the dip in the isolation at frequencies 0.1GHz up to
1GHz. Beyond this frequency, this impedance becomes smaller in comparison to the substrate
resistive network, thus the isolation remains almost constant up to the cutoff frequency. Beyond
this frequency the isolation is degraded as frequency increases due to the capacitive nature of the
substrate behavior that kicks in beyond the cutoff frequency. The cutoff frequency in this case is
more than the case of the p guard ring due to the fact that the conductivity of the n guard ring is
larger than that of the p guard ring. As shown in figure 3.10, putting the n guard ring around the
transmitter is a more efficient isolation technique. Isolation is increased by approximately 2.5 dB
if compared to the isolation of the n guard ring placed around the receiver. This conclusion is
similar to what was concluded for placing the p+ guard rings around the receiver and transmitter
in the previous section. Adding two n guard rings around both the transmitter and the receiver
provides 5 dB more isolation if compared to the isolation of a single guard ring placed around the
transmitter only, and 7.5 dB if compared to the isolation of a single guard ring placed around the
receiver only, provided that the ac ground of the guard rings are separate. The simulation results
as shown in figure 3.11 tracks the above mentioned behavior accurately. In figure 3.12 the p
guard ring is compared to the n guard ring. The n+ well guard ring provides higher isolation than
P+ guard ring due to its lower sheet resistivity that provides higher noise sinking ability. For the
same doping concentration, the n guard ring is ~ 2X less resistive due to the electron mobility in
the n guard ring being larger than the hole mobility in the p guard ring.
3.6.
Effect of deep n-well on isolation
In this section the effect of a deep n-well guard ring is compared to the p+ and the n+ guard rings.
Figure 3.13 shows the layout of this structure. A p+ diffusion representing the receiver is placed
44
in a p-well that is isolated from the common p-substrate by a deep n-well implant. An n-well
guard ring is designed to surround the receiver and be on top of the deep n-well tub. An n+
diffusion is implanted and contacted in the n-well guard ring and connected via low resistive
metal routing to the DC probe pad used to bias the n-well to vdd1. The transmitter is designed
exactly like the receiver, with the exception of the DC probe pad that is connected to a separate
DC supply vdd2. Figure 3.14 shows the measurement results of the isolation of this structure vs.
frequency. The simulation result of the isolation is overlaid on the measurement data. Figure 3.15
shows the measurement results comparing the isolation of the n guard ring discussed in the
previous section to the isolation of the deep n-well guard ring, the comparison is performed for
the case of two guard rings surrounding the receiver and the transmitter with the rings tied to
separate supplies.
Figure 3.13 Layout and cross section of the structure used to measure and simulate the deep n-well
guard ring isolation structure
3.6.1. Data analysis
The deep n-well acts as a low resistive current sink that is buried in the substrate. This
will provide a sink to deep substrate noise currents and will extend the effect of current sinking
45
from the surface to a distance deep down in the substrate. Such design will enhance the isolation
if compared to the regular n-well guard ring that only provide current sink to surface currents. A
substrate noise current is now forced to dive deep in the substrate to reach the receiver, such deep
path has more impedance due to the high resistive nature of the substrate.
Deep n-well Isolation
-20
deep n-well isolation meas
-30
deep n-well isolation sim
S12 (dB)
-40
-50
-60
-70
-80
-90
-100
0
5
10
15
20
25
30
freq (GHz)
Figure 3.14 measurement and simulation data of the deep n-well guard ring isolation structure
Comparing Isolation techniques
-20
-30
two deep n well guard rings
two n guard rings
S12 (dB)
-40
-50
-60
-70
-80
-90
-100
0
5
10
15
20
25
30
freq (GHz)
Figure 3.15 comparison between the isolation of two deep n well guard rings and two n well guard
rings
46
Figure 3.15 shows at least 5 dB of isolation enhancement of the deep n-well guard ring
over the n guard ring. Since the resistivity of the deep n-well is less than the p substrate, its cutoff
frequency is pushed beyond the 15GHz and the isolation remains more constant than the case of p
guard rings. At low frequency the isolation is better due to the reverse biased p-n junction
between the n-well and the p-substrate. Figure 3.15 shows that the low frequency behavior of the
deep n-well is different than that of the n-well. The deep n-well isolation is more at low frequency
and it degrades with increasing the frequency slower than the n-well. The reason for that is due to
the fact that the deep n-well is more lightly doped than the regular n+ well and hence the
capacitance of its p-n junction with the p substrate is smaller than that of the n+ well. Being less
capacitive increases the capacitive impedance of the p-n junction and hence it takes a higher
frequency for this impedance to vanish relative to the substrate resistive network. At this higher
frequency the dip in the isolation at low frequency vanishes and the isolation reaches its plateau
value.
3.7.
Effect of deep trench on isolation
Figure 3.16 shows the structure used to measure and simulate the effect of deep trench on
isolation. A deep trench is a trench in the silicon substrate approximately 10um deep that is filled
with oxide. A ring of deep trench surrounding a noise receiver is implemented and the isolation is
measured and compared to the p guard ring isolation surrounding the noise receiver. Figure 3.17
shows the measured and simulated data of this isolation structure together with the data of the p
guard ring for comparison.
3.7.1. Data analysis
The oxide in the deep trench acts as a high impedance insulator that forces the substrate noise
current to dive deep in the substrate. Hence the isolation is enhanced by adding a deep trench by
approximately ~ 2 dB. As the frequency increases, the impedance of the oxide tends to loose its
47
impact and the isolation in the presence of the deep trench approaches that of the basic p guard
ring.
Figure 3.16 Layout and cross section of the structure used to measure and simulate the deep trench
isolation structure.
p guard ring isolation with a deep trench
-50
p_guard_ring_meas
p_guard_ring_sim
-52
p_guard_ring&DT_meas
p_guard_ring&DT_sim
-54
-56
S12 (dB)
-58
-60
-62
-64
-66
-68
-70
0
5
10
15
20
25
30
fre q (GHz)
Figure 3.17 isolation of a p guard ring with a surrounding deep trench as compared to a regular p
guard ring
48
3.8.
De-embedding
In this section the procedure that is followed to subtract the effect of the GSG probe pad and
feed line parasitics is explained. To create an environment which is suitable for on-wafer RF
probing, wiring (feed lines) and probe pads have to be added to the DUT (device under test). To
obtain results for the DUT only the influence of these additional elements has to be subtracted,
i.e. de-embedded. Figure 3.18 shows a typical equivalent circuit for the DUT and the parasitics
elements for on-wafer measurements. Parasitic resistances of the feed lines are in series with the
DUT while the parasitic signal pad capacitance is parallel to the DUT and the parasitic
resistances. To de-embed the pad capacitance and feed line resistance, open and short structures
are designed as part of the test chip. The design and the equivalent circuit of the open structure
are shown in figure 3.19, while the short structures are shown in figure 3.20. Note that the open
structure has the pad capacitance, and identical pads and wiring, while the short structure has both
pad capacitance and feed line resistance. The short is created by inserting a very low ohmic path
to short the signals to the ground pads. The procedure for de-embedding is as follows.
Figure 3.18 Layout and equivalent circuit of the GSG structure with the DUT.
49
Figure 3.19 Layout and equivalent circuit of the GSG open structure
Figure 3.20 Layout and equivalent circuit of the GSG short structure
50
Step1
Convert measured S to Y parameters
Smeas, DUT Ymeas, DUT
Smeas, Short Ymeas, Short
Smeas, Open Ymeas, Open
Step2
De-embed DUT and short from parallel pad parasitics
Ymeas, DUT - Ymeas, Open = YDUT-Open
Ymeas, Short - Ymeas, Open = YShort-Open
Step3
Convert Y to Z parameters
YDUT-Open ZDUT-Open
YShort-Open ZShort-Open
Step4
De-embed DUT (without open) from serial resistive parasitics (Short without open)
ZDUT-Open- ZShort-Open = ZDUT
Step5
Convert DUT’s Z to S parameters
ZDUT SDUT
The Y, Z, S parameters are related to each other as given in [28]. Appendix B explains the
measurement details.
51
3.9.
Conclusion
In this chapter the measurement results of a test chip is presented. The test chip has different
substrate isolation structures that will be used extensively in the next chapters. The goal of this
test chip is two folds. First, is to calibrate the design flow used in simulating the substrate noise
coupling and second is to compare isolation structures and learn what isolation structures are
most efficient for substrate noise isolation as well as the design parameters involved, grounding
techniques and measurement procedures to de-embed the DUT data. The simulation results are
compared to the measurement data and found to be accurate to within 2 dB of the measurement
data across the entire frequency range used. Lots of learning about the efficient usage of isolation
structures is captured to be part of the substrate isolation design guide presented in the next
chapter.
52
CHAPTER 4
DESIGN GUIDE FOR SUBSTRATE NOISE ISOLATION IN RF
APPLICATIONS
4.1.
Introduction
In this chapter a novel substrate noise isolation design guide is developed. The
development of the design guide is based on the design environment flow studied in chapter 2
that is calibrated to silicon measurements in chapter 3. First the leanings from the design
experiments performed in the previous chapter are discussed which focuses on the frequency
behavior of the different isolation structures. Next, a series of simulations are performed to
expand the design guide to target three major categories of factors that affect the noise isolation.
First, the backplane connection is studied and its impact on isolation is highlighted. The
frequency dependence of the isolation and the impact of the backplane impedance are considered.
Second, the isolation as a function of: the geometrical parameters of the isolation structures, the
electrical parameters of the substrate, mainly the substrate resistivity, the inductance of the bond
wires connected to the isolation structures and the frequency of operation. Different grounding
techniques of the isolation structures are also studied. Third, the chip floor plan and the design of
the power & ground domains to enhance isolation. The design guide will be limited to the
substrate noise coupling as applied to RF applications, and hence the focus will be only on high
resistivity substrates (~10Ω.cm, which is the substrate of choice for this application, as discussed
in section 2.5), as well as the RF frequency of operation.
53
4.2.
Isolation in Low resistivity substrate
Low resistivity substrates are used in digital CMOS applications as discussed in section
2.5. In this case the substrate noise currents find a low impedance path in the substrate bulk and
are able to penetrate easily deep in the bulk, the majority of the currents pass through the bulk and
the surface components of these currents are minimum. Thus, in this case, the surface isolation
structures such as guard rings are ineffective in providing noise isolation. Same applies to the
inductance of the bond wires attached to the guard rings. This inductance becomes ineffective for
low resistivity substrate since almost all the noise is not conducted thought the surface of the
wafer where the guard rings exist and where their inductances matter. Large gains in substrate
isolation are achieved only by lowering the inductance of the wafer backplane connection. This
behavior can be expected in low resistivity substrates because current flow in these substrates is
mostly through the bulk, and providing low impedance to the backplane acts as a good sink to the
noise current in the substrate bulk [29]. Guard rings on the other hand are an effective current
sink for only the surface component of the current which dominates in high resistive substrates.
Also the distance between the noise transmitter and receiver is not effective beyond 4X of the epi
thickness in low resistive substrates [30].
4.3.
Isolation vs. Frequency for different isolation structures.
The findings of the previous chapter are summarized below to provide a design guide for
different isolation structures and their frequency dependence.
Design Guide 1: Baseline isolation (isolation between ohmic contacts to the substrate in the
absence of any isolation structure) is constant with frequency up to the cutoff frequency. Beyond
the cutoff frequency the isolation degrades as frequency increases. It is recommended to select
the resistivity of the process technology low enough to ensure a high cutoff frequency and high
enough to ensure low substrate eddy current losses.
54
Design Guide 2: A P+ guard ring with low impedance to ground surrounding the noise
receiver provides better isolation if compared to the baseline isolation at all frequencies. The
guard ring acts as a current sink to the surface noise currents which are the dominant noise
currents in high resistive substrates. The bulk impedance is high thus forces noise currents to the
surface.
Design Guide 3: Isolation due to P+ guard rings is constant with frequency for noise
receivers and transmitters that are contacting the substrate via ohmic contacts, up to the cutoff
frequency. The frequency dependency is not as constant if compared to the baseline isolation due
to the fact that the impedance of the guard ring connection to ground increases with frequency
hence it weakens the current sinking capability of the guard ring as frequency increases.
Design Guide 4: Placing the guard ring around the noise transmitter is a more effective
isolation technique than placing it around the noise receiver.
Design Guide 5: N+ guard rings provide better isolation than P+ guard rings specially at low
frequency due to the capacitive nature of the p-n junction that provides high impedance to noise
currents at low frequency. As frequency increases the isolation of the N+ ring approaches that of
the P+ ring, but still remains better due to the lower resistivity of the N+ ring which acts as a
better sink if compared to the P+ ring of the same geometry at the same frequency of operation.
Design Guide 6: Placing two N+ rings to surround the noise receiver and transmitter
provides better isolation than a single ring as long as the two rings are connected to separate
supply lines.
Design Guide 7: As the frequency increases and the guard ring impedance to ground
increases, the current sinking capability of the ring vanishes and the isolation approaches the
baseline isolation. Thus, it is crucial to ground the substrate isolation structures using very low
impedance connections to keep their effect up to the frequency of interest.
55
Design Guide 8: A deep n-well N+ guard ring provides more isolation if compared to the N+
guard ring and has a better isolation vs. frequency. Deep n-well forces the noise current to
penetrate deeper in the substrate where it faces high impedance. Also the low frequency isolation
is superior to the N+ guard ring because the deep n-well is lightly doped than the n-well and
hence its capacitance to the substrate is lower, thus its impedance is higher and the isolation
degrades slower with frequency.
Design Guide 9: A deep trench ring provides more isolation than the baseline and enhances
the GR isolation if placed around it.
4.4.
Effect of back plane connection on the noise isolation in high resistivity
substrates
The isolation between two surface contacts in a high resistive substrate is simulated with and
without backplane contact to study the impact of grounding the backplane on the noise isolation.
Figure 4.1 shows the layout of the structure simulated. Two baseline p+ diffusions are placed in a
p substrate structure similar to that used to measure the baseline isolation vs. frequency. The
parameters that are varied in the simulation are the following: The simulation frequency is set to
1GHz and 10GHz. The backplane inductance is set to 0.1nH and 2nH. The distance between the
contacts is varied from 10um to 400um. Figure 4.2 shows the simulation results for the case with
no backplane “bp” i.e. floating the backplane of the wafer at two frequencies, and then it shows
four plots with different frequencies and backplane inductances. Examining the simulation results
in figure 4.2, the following design guides are deducted.
Design Guide 10: grounding the backplane of the high resistive substrate provides
approximately 5dB more isolation at small distances (low bulk current) and ~10dB more isolation
at large distances (higher bulk current) if compared to the floating backplane substrate.
Grounding the backplane provides a path to ground for the bulk noise currents and hence
improves the isolation. The improvement is not significant (few dB) since it is hard for the noise
56
currents to get to the wafer backplane due to the high resistivity of the substrate. The percentage
of the noise currents that can make it to the backplane increases with frequency as the frequency
approaches the cutoff frequency and the substrate capacitive impedance starts to lower the overall
substrate impedance, but the impedance of the bp inductance increases with frequency and its
sinking ability decreases.
Design Guide 11: Minimizing the inductance of the backplane slightly enhances the
isolation. Small inductance provides a better ground current sink to the bulk component, while the
improvement is mild due to the fact that backplane current in high resistive substrate is not the
main noise current path.
Design Guide 12: The isolation gets better as the distance between the noise transmitter and
noise receiver increases. The distance driven isolation saturates as the distance gets large if
compared to the receiver and transmitter areas.
Design Guide 13: The baseline isolation is relatively frequency independent as long as the
frequency remains well below the cutoff frequency and the coupling to substrate is ohmic.
For noise sources that are capacitively coupled to the substrate the structure in figure 4.3 is
simulated. The noise transmitter is now a MOS capacitor that is capacitively coupled to the
substrate via the gate capacitance. Now the isolation becomes a function of frequency, with a
large enhancement at low frequency. Figure 4.4 shows the simulation result for the case of
capacitive coupling.
Design Guide 14: The isolation at low frequency is enhanced by ~20dB relative to the
resistive coupling case. At high frequency ~10GHz the improvement in isolation due to the
capacitive coupling nearly vanishes. The capacitance of the MOS cap introduces high impedance
at low frequency that diminishes the amount of noise that is coupled to the substrate relative to
the ohmic case. As frequency increases the capacitive impedance decreases and the isolation
approaches the ohmic case.
57
Going forward, since grounding the backplane provides better isolation; all the upcoming
simulated structures will have the backplane grounded with L=0.01nH.
4.5.
Substrate Contacts: Front side or Backside? Both.
In all cases where an electrical contact to the substrate is desired, front side substrate
contacts are the best recommended way to provide that contact. In other words, if a contact to the
chip substrate is desired, making a contact to the chip backside through a conductive mounting is
not sufficient. The chip backside may have a residual oxide coating that prevents an adequate
electrical contact. Also in most of the situations the chip backside is not metallized. However, it
should be understood that some electrical contact is likely to exist if the chip is placed on a
Figure 4.1 test structure used to simulate the backplane impact on isolation for resistive coupling
58
S12 (dB)
Basline Isolation vs. Distance for resistive coupling
f=1GHz, Lbp=0.1nH
f=1GHz, Lbp=2nH
f=10GHz, Lbp=0.1nH
f=10GHz, Lbp=2nH
f=1GHz, no bp
f=10GHz, no bp
-15
-17
-19
-21
-23
-25
-27
-29
-31
-33
-35
0
100
200
300
400
Distance in (um)
Figure 4.2 Baseline isolation for resistive coupling vs. backplane inductance
Figure 4.3 test structure used to simulate the backplane impact on isolation for capacitive coupling
59
Basline Isolation vs. Distance for a capacitively
coupled noise source
-15
f=1GHz, Lbp=0.1nH
-20
f=10GHz, Lbp=0.1nH
-25
S12 (dB)
-30
-35
-40
-45
-50
-55
-60
0
100
200
300
400
Distance in (um)
Figure 4.4 Baseline isolation for capacitive coupling
conductive mounting i.e. the chip backside is not a guaranteed insulator. Since it is desirable to
maintain the chip substrate at an equipotential to provide a good AC ground, contact to the chip
substrate is desired. The recommended method is to provide many contacts on the front side tied
to a good AC ground. Additionally, placing the chip on a conductive mounting and biasing the
chip backside to the same potential as the front side substrate contacts will provide enhanced AC
grounding. The connection between the front side contact potential and the backside should be
made as symmetrically as possible in order to maintain an equipotential on the backside. The DC
potential of the substrate should be such that the substrate is always reverse-biased with respect to
all N-type diffusions. Floating the chip backside by either not connecting the conductive
60
mounting to any potential, or by mounting on a nonconductive surface, is allowed, but is not
recommended as discussed in the previous section. The design of front side contacts to the
substrate “guard rings” is discussed next.
4.6.
P+ Guard Ring Isolation
In mixed analog-digital designs, a common layout design practice is to use guard rings to
improve noise isolation. Because of the uncertainty about the amount of additional isolation
provided by guard rings, designers may use guard rings that provide little isolation or may
increase noise coupling. This fact necessitates the quantitative understanding of the isolation
provided by the guard rings. It is also beneficial in avoiding unnecessary engineering time and
area overhead. Guard rings can be either majority rings, where the guard ring diffusion is of the
same type as the substrate doping (p+ in p-type substrate or n+ in an n-type substrate), or
minority rings, where the ring diffusion is of the opposite type of the substrate doping. Figure 4.5
shows the structure that is simulated. The geometrical and the electrical parameters are varied in
the next sections to study the impact of D, w, d, LGR, freq, and ρ on the isolation and compile the
design guide lines for designing the guard ring. Unless otherwise stated the following are
assumed as defaults: D=120um, d=10um, w=3um, LGR=0.01nH, freq=1GHz, ρ=10Ω.cm
4.6.1. Guard Ring Isolation vs. D
Figure 4.6 shows the simulation results of noise isolation vs. D for different frequencies and
guard ring inductances.
Design Guide 15: for all cases, isolation improves with distance ‘D”.
Design Guide 16: At low f *L as the case of L=0.01nH and f=1, 10 GHz, the isolation is
enhanced by ~10dB as D is changed from 20um to 400um. While at high f*L as the case of
L=2,4nH the isolation is enhanced by ~ 20dB. Thus the dependence of the isolation on the
distance D is not effective at low guard ring inductance as compared to the cases of high guard
ring inductance. This is because the isolation is mainly provided by the guard ring sinking the
61
noise current at low inductance, and increasing the distance adds only slight improvement. While
at high inductance the sinking capability is weakened and the distance can contribute more to the
isolation.
Figure 4.5 test structure used to simulate the impact of guard rings on isolation
Figure 4.6 Guard ring Isolation vs. distance D
62
Design Guide 17: in all cases the dI/dD is max at low D, thus increasing the distance
leads to diminishing return especially at low inductance.
Design Guide 18: Isolation at both high and low frequencies is very close in value as
long as the inductance is very low. This is because the high frequency is still below cutoff freq
and the guard ring is still a good sink even at high freq due to the low inductance. This will
change in the case of capacitive coupling, where low freq isolation is improved significantly.
Design Guide 19: As f and L both go up, D becomes effective in providing isolation.
This indicates that more current flows in the substrate and not sunk by the GR. As D increases the
isolation is improved since the current that is flowing in the substrate faces more impedance.
Design Guide 20: At high f and L the GR approaches being floating and the isolation
approaches that of the baseline. In real situations this LGR will inject noise due to mutual
inductance of the neighbor bond wires; in such case the GR is worse than the baseline, as will be
discussed later in this chapter.
4.6.2. Guard Ring grounding scheme
Figure 4.7 shows the structure used to simulate the effect of different grounding
techniques on the guard ring isolation. In case B both guard rings are connected to the same bond
wire inductance LGR1 , while case A has separate guard ring bond wire connections. As discussed
in section 3.4 and figure 3.7, the simulation results of the different situations is presented in figure
4.8.
63
Figure 4.7 Guard ring grounding schemes
p guard ring isolation
S12_P_guard_at_rec_only
-45
S21_P_guard_at_trans_only
S12_CaseB
-50
S12_CaseA
S12 (dB)
-55
-60
-65
-70
-75
0
5
10
15
20
25
freq (GHz)
Figure 4.8 Guard ring grounding scheme simulation data LGR=1nH
64
30
Design Guide 20: Figure 4.8 shows that the guard ring is more effective at the transmitter, dual
rings provides better isolation as long as they have separate ground connections. Tying both rings
to the same bond wire injects more noise around the receiver and degrades isolation.
4.6.3. Guard Ring Isolation vs. d
Next is to study the impact of the guard ring to the noise receiver distance on isolation.
The distance “d” shown in figure 4.5 is varied in a series of simulations that vary other
geometrical and electrical parameters to understand in depth the physical phenomena governing
the substrate noise isolation. Examining figure 4.9 and figure 4.10 yields several design guides.
Design Guide 22: A guard ring that is tightly enclosing the noise receiver provides up to
~7dB of extra isolation if compared to a guard ring that is away from the noise receiver, as long
as the guard ring inductance to ground is kept very small. The degradation in isolation saturates
as the enclosure distance “d” increases.
Design Guide 23: As the guard ring inductance increases and as the frequency increases
the guard ring losses its current sinking capability and its contribution to the noise isolation. In
this case the enclosure distance plays fewer roles in improving the isolation. This is shown in
figure 4.10 where the isolation improvement due to a smaller distance “d’ gets less as f*L
increases. Again it is noticed that the isolation value approaches its baseline value as f*L
increases.
Design Guide 24: The increase in isolation due to increasing the distance “D” is more
for a higher resistive substrate. In other words the rate of change of isolation vs. distance “D”
dI/dD is directly proportional to ρ. As seen in figure 4.9 on the left, the delta in isolation between
D=120um and D=400um when ρ=10Ω.cm is less than that on the right when ρ=50Ω.cm. As ρ
gets higher, increasing the distance “D” causes the impedance between the noise source and noise
receiver to increase rapidly if compared to a lower ρ.
65
Design Guide 25: The rate of change of isolation vs. substrate resistivity dI/dρ is directly
proportional to D. As shown in figure 4.9 the delta in the isolation curve on the top left vs. the
top right is smaller than that of the bottom left vs. the bottom right. At small distance “D’
changing the substrate resistivity won’t change the isolation much if compared to the case of
larger “D”.
Design Guide 26: for all cases, isolation improves with substrate resistivity.
Figure 4.9 Guard ring Isolation vs. distance “d”
Isolation as a function of ring enclosure distance "d"
substrate resistivity = 10 ohm.cm
-20
-25
S12 (dB)
-30
-35
D=120um, f=10GHz, L=4nh
D=400um, f=10GHz, L=4nH
D=120um, f=1GHz, L=2nH
-40
-45
-50
-55
0
10
20
30
40
50
d (um)
Figure 4.10 Guard ring Isolation vs. distance “d”
66
60
4.6.4. Guard Ring Isolation vs. “w”
Figure 4.11 shows the structure used to simulate the relation between the width of the
guard ring and isolation. In this study, the impact of noise coupled to the guard ring through
neighbor bond wire inductance is also highlighted. Bond wires of signals or ground and supply
lines that are close to the sensitive circuitry may be switching at high rates and introduce noise to
the guard ring under consideration through the mutual coupling between the bond wire inductors.
Figure 4.12 shows four plots of isolation vs. ring width for different parameters with and
without Vnoise. The bottom two plots have very low ring inductance, while the top two plots
have high guard ring inductance and high frequency of operation. In the two cases noise is added
to see the impact of noise coupling on the isolation between the noise transmitter and the noise
receiver.
Design Guide 27: For low guard ring inductance, increasing the ring width decreases its
resistivity and provides more current sinking capability and hence better isolation ~5dB. The
isolation improvement vanishes at higher “w’, compromise between area and isolation
improvement is needed.
Figure 4.11 Structure used to simulate guard ring isolation vs. distance “w”
67
Isolation vs. ring width
-10
-20
-30
S12 (dB)
D=120um, f=1GHz, L=0.01nH, d=10um
-40
D=120um, f=10GHz, L=4nH, d=10um
D=120um, f=10GHz, L=4nH, d=10um, noise added to the GR
-50
D=120um, f=1GHz, L=0.01nH, d=10um, noise added to the ring
-60
-70
-80
0
5
10
15
20
25
30
ring w idth w (um)
Figure 4.12 Guard ring Isolation vs. ring width “w”
Design Guide 28: Even in the presence of noise coupling, as long as the guard ring
inductance is kept very small, the guard ring will sink the coupled noise and isolation will not be
degraded, this is clear by examining figure 4.12 bottom plot with noise added, which gives nearly
the same isolation as the case where no noise is added, since L is 0.01nH in this case. This
inductance gives ~ 60mΩ at f=1GHz, which provides a good ground to sink the coupled noise.
Design Guide 29: As f*L increase the guard ring looses its sinking capability and the
isolation is degraded, in such case the width of the guard ring becomes an ineffective way of
providing isolation. In the presence of coupled noise and high f*L a wider guard ring will pick
more noise than a narrow ring and isolation degrades beyond baseline (with no ring altogether).
68
Design Guide 30: since wider guard rings provide only slight isolation improvement and
they may inject more noise if coupled to a noisy bond wire, narrower guard rings with very low
inductance to ground are recommended.
Design Guide 31: During chip floor planning, it is highly recommended to spatially
separate the noisy signals from sensitive circuits, both on chip as far as metal and interconnect
routing and on the package by separating the bond wires of these pins.
4.7.
P+ and N+ Guard Rings Isolation
As shown in the previous chapter, adding an N well guard ring provides extra isolation if
compared to the P guard ring. In the section below both rings are used simultaneously to study the
impact of a dual guard ring on isolation. Figure 4.13 shows the structure used in the simulation,
both guard ring connection inductances are assumed to be very low. The enclosure distance
between the receiver and the p guard ring is kept equal to the distance between both rings. This
will allow us to isolate the effect of adding the N well guard ring from other parameters. The
frequency used in the simulation is high enough to remove the low frequency isolation
enhancement introduced by the capacitive impedance of the p-n junction that is formed between
the N well and the P substrate; doing so will ease the comparison and rule out the parameters that
are not present in the case of a P guard ring alone. N guard ring provide extra isolation at high
frequency by forming a deep and relatively wide current sink area and thus forces the noise
currents to deviate deeper in the substrate. While its pn capacitance enhances the low frequency
isolation.
69
Figure 4.13 P and N Guard ring Isolation structure
Figure 4.14 shows the simulation results that compare the isolation of a P guard ring
alone to the case of dual P and N guard rings surrounding the noise receiver. Enclosure distance
“d’ is varied on the X axis. The substrate resistivity is varied going across the charts at a fixed
transmitter to a receiver distance “D”, while going down, the distance “D” is changed at a fixed
substrate resistivity. Examining the charts below yields the following guide lines:
70
Figure 4.14 P and N Guard ring Isolation vs. enclosure distance “d”
Design Guide 32: Adding an N guard ring to the P guard ring consistently improves the
isolation.
Design Guide 33: The isolation improvement is best at lower substrate resistivity and
lower distance “D”. The delta in isolation is reduced moving across the charts and also is reduced
moving down the charts. This could be explained as follows; the increase in substrate resistance
in the case of small D and small ρ introduced by the use of n-well ring is significant compared to
the original substrate resistance, and therefore the effect is significant. For the case of large D and
71
large ρ the change is small compared to the original substrate resistance and that results in a lower
delta.
4.8.
Floor planning techniques to minimize coupling
The next step in the design guide is to design the floor plan and the power domains of the
chip to minimize substrate noise coupling. Figure 4.15 shows the recommended methodology for
floor planning. The guide line is to spatially separate the building blocks based on their analog
and digital nature as well as the voltage amplitude and frequency of switching. Each block should
be surrounded by a guard ring, or a dual guard ring connected to a low impedance bond wire, in
some cases two bond wires in parallel are used to minimize inductance to ground. In some
situations the floor planning may contradict with the signal routing, so the floor plan below is
recommended as long as it is practical to implement vs. other constrains. The power domains of
each block should be kept separate to avoid noise coupling through the switching power supplies.
Figure 4.16 summarizes the correct placement and biasing of the guard rings and ground lines.
Figure 4.15 floor planning to minimize substrate noise coupling
72
Figure 4.16 placements and biasing of the guard rings and ground lines
The backplane of the die is glued with metal epoxy to the package ground metal plane. This
ground metal plane is connected to the external bottom plane of the package and connected to the
PCB to establish the “external” system ground. The on die pads that are connected to the different
ground domains “internal grounds” are tied down to the package ground plane using bond wires.
These on die ground pads are connected to the different guard rings. The guard rings and the
ground domains are designed to reduce substrate coupling by limiting the injected noise and
sinking the transmitted noise. To do so, the digital and analog transistors are treated differently.
The switching digital transistor sources are separated from the transistor bulks. The sources and
bulks are connected to two separate guard rings as shown in figure 4.16 top left section. Doing so
73
will prevent the switching noise from being injected to the bulk which is connected directly to the
substrate. To reduce the effect of the current which reaches the bulk, a low-impedance return path
is of uttermost importance [30]. For heavily doped substrates, the best result is obtained by
mounting the die with conductive epoxy to the lead frame using several bond wires to connect it
to the external ground. Eventually, large substrate contacts with a dedicated pin filling spare
places on the chip can be an alternative. In lightly doped substrates where most currents flow just
underneath the chip surface, a guard ring with dedicated pin surrounding the digital block is an
effective return pad. In these substrates, physical separation of noise sources and sensitive circuits
is also very effective as the resistance in the noise path continuously increases with the distance.
Substrate noise disturbs the analog circuits through their bulk to source voltage. To reduce this
bulk effect, bulk source voltage variations of analog MOS transistors should be minimized. The
bulk must thus be tied locally to the analog reference “on die” rather than to the (slightly
different) external one “on package”. This is achieved with bulk contacts close to the analog
transistors and biased with the local analog ground, which results in an optimal output voltage
relative to the local on-chip analog reference (analog reference or analog ground in most cases
are the sources of MOS devices). A guard ring with dedicated pin around the analog circuits
eventually enhances the noise immunity even further [30], but does not eliminate the need of the
good bulk contacts to the local analog ground. For a SiGe process where bipolar transistors are
more frequently used than MOS transistors the bulk terminal of the bipolar transistors that
represent their contact to the substrate as discussed in chapter two is connected to a ground pin
that is separate from the emitters of the bipolars. Same applies to the bulk of all passive devices in
the process. Such separation will prevent noise due to the switching transistors to be injected in
the bulk and cause substrate injected noise.
Another layout technique to minimize the substrate noise coupling is through careful routing.
Digital signals should not be routed over or through the analog portion of the chip, or be routed
74
next to sensitive lines. The floor plan should ensure that the package pin assignment does not
route sensitive analog signals near digital I/Os, supplies, or clock signals.
4.9.
Circuit techniques to minimize coupling
Differential circuits are always recommended over single-ended circuits in noisy
environments [35]. Substrate noise is not an exception. The noise, due to its random nature,
appears as a common-mode signal on the differential outputs. The differential noise signal is
typically several orders of magnitude smaller than what would be observed in a single-ended
implementation of the circuit. In this section, the use of guard rings in differential circuits to
reduce substrate noise is discussed. Figure 4.17 shows a simple asymmetric differential layout,
with both p+ and n-well rings used. The two noise receivers of the structure “a” and “b” are
placed asymmetrically with respect to the noise source. If the noise source is placed symmetrical
to the receivers, the differential noise will be close to zero. The simulation results of the baseline
isolation, isolation using a p+ guard ring only to surround the two receivers, and the isolation
when dual p+ and n well guard rings are used to surround the noise receivers are shown in figure
4.18.
Figure 4.17 layout used to simulate the impact of guard rings on differential noise
75
Figure 4.18 differential isolation using p guard ring and dual p & n-well guard rings
The delta in the isolation numbers of noise receivers a and b in the case of the baseline isolation is
shown on the left hand side of figure 4.18 to be 3.1 dB. On the right hand side of figure 4.18 the
delta is 1.78 dB in the case of a p guard ring only surrounding the noise receivers and 0.43 dB in
the case of a dual guard ring.
Design Guide 33: A dual guard ring when used for differential configurations, equalize noise
coupling on the two sides of the differential structure and decrease the differential noise if
compared to the p guard ring alone. P guard ring minimizes the differential noise if compared to
the baseline isolation.
4.10.
Active guard rings
Substrate noise suppression circuits are being discussed in several researches [31], [32],
[33], [34]. The basic idea is to use the passive guard ring in addition to active guard band circuits
to sense the substrate noise signal at a specific location and inject an opposite signal in another
location to cancel the substrate noise at a target sensitive location. This technique proved to
provide around 10 dB of extra isolation up to 100MHz, the limitations of this technique is as
follows. First the idea is based on canceling the noise that can reach deep into the substrate bulk,
because surface noise can be suppressed by passive guard rings. Hence, this technique is more
76
suitable to low resistive substrates and not to high resistive substrates. Second, this technique
used circuits like operational amplifiers to generate the negative of the noise source; such circuits
have a limited band width, thus limiting the effectiveness of this technique to frequencies below
the cutoff frequency of the active circuitry. Implementing these circuits as a high bandwidth
designs adds to the complexity and overhead of the design. Third, the application of this
technique is suitable for small designs, while for large designs it won’t be practical to repeat this
circuits several times to suppress noise in several locations on the chip.
4.11.
Conclusion
A novel design guide for the substrate noise isolation structures is developed in this chapter
based on a test chip and a deign environment calibrated to measurements. The focus was the RF
applications and the substrate types used for such application together with the frequency band of
operation of these applications. The different techniques of the isolation structures are studied
together with the electrical and geometrical parameters that affect their performance and guide
lines are provided to minimize substrate noise coupling. Next the layout and floor planning,
power domains and guard ring grounding techniques are discussed. The interaction between the
package and the die to define the internal and external grounds is discussed and a differentiation
is made between digital and analog transistors for ground connection consideration.
The
methodology of ground and bulk connection is also highlighted for CMOS and bipolar process
technologies.
77
CHAPTER 5
ON CHIP INDUCTORS DESIG FLOW
5.1.
Introduction
The performance of on-chip spiral inductors is heavily dependent on the substrate properties.
Further, the substrate isolation structures placed around the inductors can impact the inductor
performance even further. In this chapter a design flow is developed to accurately design and
model on chip spiral inductors taken into consideration all the substrate properties and interaction
effects. The impact of the isolation structures interaction will be studied in the next chapter.
Inductors are used in various RF and wireless circuit’s applications. Main applications are in
low noise amplifiers, power amplifiers and LC tank voltage controlled oscillators. Other mixed
signal applications are found in high speed serial IO circuit applications such as band width
extension, clock drivers and current peaking. At the heart of any RF receiver is the PLL
frequency synthesizer and VCOs. Early research efforts for the monolithic CMOS VCO had
focused on the design and implementation of high-Q resonator components, especially integrated
inductors, to achieve low phase noise at an acceptable level of power consumption [36–38]. The
two important challenges to implement RF VCOs in a fully integrated RF transceiver are; i) onchip noise coupling through cross-talk between blocks and substrate ii) CMOS fabrication
tolerances (process variation) [44]. Fully integrated PLL frequency synthesizer solution must
address top level implementation issues as well as individual block design issues. In the next
78
chapter on-chip noise coupling through cross-talk between blocks and substrate is studied, while
in this chapter a design flow for designing on chip inductors that take into consideration design
for manufacturing, such as metal density fill, bump effects for flip chip applications, as well as
the process and temperature variations impact on the inductors performance are studied.
5.2.
Integrated Inductors
Inductors can be implemented in three different ways in an IC technology; (i) external offchip inductors (ii) packaging bond-wires as inductors (iii) on-chip spiral inductors. The use of
external inductors is not preferred with CMOS technology for several reasons. The pin parasitics
of the package will limit the usable values of inductors, since cross coupling caps will limit the
inductor values especially for inductance larger than 3-4 nH. In addition, the crosstalk paths
between pins will inject noise into the resonator tank and degrade the noise performance of the
VCO. Also, ESD (electro-static discharge) protection networks in CMOS are probably the major
factor preventing the implementation of external resonator tanks. Although bondwire inductors
have a very high quality factor, they are not commonly used in VCOs because of lack of
reproducibility and mechanical stability. An excellent review of design and implementation of
bondwire inductors can be found in the reference [36]. On-chip integrated inductors are favored
over off-chip ones because pad and bond wire parasitics are eliminated. Also, on-chip inductors
exhibit good reproducibility since the inductor value is mainly determined by horizontal
dimensions which are tightly controlled by lithographic resolution in any CMOS technology. The
major drawback of on-chip inductors is the low-Q factor and large die area. On-chip integrated
inductors are built in spiral geometries including squares, octagons and circles. Compared to a
circular inductor, a square spiral inductor has larger inductance-to-area ratio but contributes more
series resistance which is due to longer overall metal length for a given inductance value.
Therefore, a spiral structure that more closely approximates a circle (whenever technology
79
permits) is preferred to increase the quality factor. While a square spiral is recommended when
high inductance is of more priority than a high quality factor.
For RF applications, the most important parameter for an integrated inductor is the quality
factor. High quality factor directly impact the phase noise of the frequency synthesizer and
directly affects the wireless channels spacing and frequency planning. The quality factor of
integrated inductors in CMOS technology suffers from three main loss mechanisms; metal sheet
resistance (ohmic loss), capacitive coupling to the substrate, and magnetic coupling to the
substrate [39]. Approaches to reduce these losses and obtain high Q on-chip inductors are as
follows; Reduce metal sheet resistance by using thicker metallization [40], stacking of metal
layers, and using lower resistivity metals (e.g. copper) [41]. Make the dielectric layer between
metal layers and the substrate as thick as possible by using top metal layers. Reduce substrate
losses by using high-resistivity substrate [45], by selectively removing the underlying substrate
with post-fabrication steps [42], by using patterned ground shield (This method is quite useful for
low resistivity substrates [43]. All approaches depend on the technology parameters. Modern RF
CMOS technologies offer a thick top metal layer between 2-10um on a medium resistivity
substrate (1 Ω.cm < ρ < 20 Ω.cm). One of the key issues in the use of an on-chip inductor in a
circuit design is the adequate prediction of its behavior. A straightforward method used by CMOS
foundries is to fabricate and measure a whole batch of inductors with varying geometries. A
library of inductors is obtained from measurement data. This library is also extended by fitting
measurement data to simple models. The fitted simple models allow only changes in one of the
geometry parameters around measured inductors, and hence limiting the available inductors to a
certain subset of the measured inductors. This is obviously not well suited for optimum inductor
design since the maximum Q and the smallest die are needed at a given frequency of interest.
80
5.3.
Inductor Design Flow
The inductor design flow that is developed in this research allows the designer to design
“custom” inductors that fit the design needs and restrictions. This gives more degrees of freedom
than what a fixed library of limited set of inductors can offer, without sacrificing accuracy. The
flow starts by defining the inductor specification. Table 5.1 lists the entire set of the parameters
that should be taken care of during designing the inductor. The list is extended beyond what is
found in the literature to accommodate very important design for manufacturing parameters that
affects the inductor yield and render the inductors production worthy.
Inductance L
Desired minimum quality factor Q at the operating frequency fo
The operating frequency fo
Minimum self resonance frequency fr
Maximum DC current
Maximum rms current
Bump pitch for flip chip
Maximum metal density rules
Metal design rules, maximum width, minimum width, minimum spacing
Table 5.1 set of parameters that should be considered during designing the inductor
Although there is much focus in the literature on L, Q, fr, there is not much focus on design
for manufacturing effects, Maximum DC and rms currents, bump pitch, metal density, metal fill
“dummification” and metal design rules. Such rules are vital for a production worthy inductors.
These DFM rules will limit the inductor design space and limit the available inductors for a
81
specific application. These specifications should all be met while minimizing the inductor area.
Figure 5.1 shows the flow chart of the design flow.
5.4.
Analytical exploration of the design space
Closed form analytical formulas are studied in the literature to calculate the L and Q of on
chip spiral inductors. The inductance is much easier to calculate analytically since its value at
high frequency is close to its DC value, given that the inductor is used well below the self
resonance frequency, thus the complexity of high frequency effects is not included in the
inductance calculation. The work presented in [46] is used to analytically predict the inductance
of square and octagonal inductors. The formula works fairly well although it assumes an
asymmetric, fully planar structure. However, cross-overs and underpasses are ignored by the
formula. Serial and parallel inductors can not be handled accurately by the formula, but the
analytical results for L gives a good starting point in exploring the design space. Quality factor is
much more complex to predict due to the many high frequency factors involved. Beside DC
ohmic loss, the following contribute to the quality factor: skin effect, proximity effect, eddy
current losses in the substrate, cross coupling capacitance between inductor turns, side way
capacitance between the inductor turns, capacitive coupling with the substrate.
Figure 5.1 Inductor design flow
82
For the quality factor, the physical model in [47] is employed. This model accounts for
the substrate losses and capacitance, oxide capacitance, inductor resistance and self-capacitance.
Of these, the self- capacitance is the most approximate because it requires a careful analysis of
the cross-overs and underpasses in the layout. The current approximation assumes an underpass
and simple capacitive coupling between the top inductor level and the next. The self-capacitance
that exists when the inductor is not planar is not accounted for at all. Both these equations are
implemented in a matlab program that takes as inputs (inductor desired L and Q, range of
inductor number of turns N, coil width W, turns spacing S, operating frequency and maximum
outer diameter OD) and gives as an output the design space contours. The set of parameters fed to
the program (W, S, N, OD) must take into consideration the specific technology design rules and
electro-migration specs. For example the range of metal spacing S should start at a number that is
greater than the minimum metal spacing allowed by the technology design “lithography” rule.
Also the maximum metal width range should stop at the maximum metal width allowed, or in this
case if more metal width is needed, metal slotting should be accounted for in quality factor and
inductance estimation. Metal slotting example is shown in figure 5.2, together with the
parameters definition. This figure shows a parallel inductor with two metal layers stacked in
parallel, the top metal is usually wide enough and hence slotting is not needed, the metal layer
below the top is what is shown and what needs slotting in most cases. Moreover, the two metal
layers are “viad” together to minimize over all resistance. Metal density rules is also a very
important restriction that should be accounted for. In all modern CMOS technologies, each metal
layer has a minimum and maximum metal density that should be met in a given area. For example
top metal layer density in a 50um x 50um area window should be more than 20% but less than
80%. Such rule is needed to avoid manufacturing problems and ensure uniform litho patterns.
Such rule will put a combined restriction on the number of turns, coil width and turns spacing
83
collectively. So some calculations must be carried to make sure that the ranges entered in the
contour plots will meet all the DFM and design rules simultaneously.
Figure 5.2 Inductor layout showing design parameters and some DFM rules
Figure 5.3 L contours as a function of OD and W at a given N and S
84
Figure 5.4 Q contours as a function of OD and W at a given N and S
85
Figure 5.5 L, Q contours as a function of OD and W at a different N and S
86
Figure 5.3 through figure 5.5 shows the L and Q contours of an octagonal inductor as a
function of outer diameter on the y-axis and metal width on the x-axis. The number of turns N,
and turns spacing S are given in different plots to avoid more than two dimensional plots. The
contours can be used to study the trade off between the design parameters (OD, W, S, N) to
achieve the desired L and Q. L is targeted first since it is more accurate to predict. Q is targeted
second, given OD bump distance limitation on the inductor area, (in flip chip application the
inductors must be centered away from the package bumps to avoid the interaction of the inductor
magnetic fields with the metal bumps, which degrades L and Q of the inductor) and W and S
design rules and density limitations. Although the analytical formula gives a good initial estimate
on the L and Q, it does not talk into account the following: Stacked metal and its eddy current
coupling, metal thickness, side wall capacitance and cross coupling capacitance between the
turns, via resistivity.
The current density in a wire is uniform at dc; however, as frequency increases, the
current density becomes non uniform due to the formation of eddy currents. The eddy current
effect occurs when a conductor is subjected to time-varying magnetic fields and is governed by
Faraday’s law [48], [49]. Eddy currents manifest themselves as skin and proximity effects. In
accordance with Lenz’s law, eddy currents produce their own magnetic fields to oppose the
original field. In the case of the skin effect, the time-varying magnetic field due to the current
flow in a conductor induces eddy currents in the conductor itself. The proximity effect takes place
when a conductor is under the influence of a time-varying field produced by a nearby conductor
carrying a time-varying current. In this case, eddy currents are induced whether or not the first
conductor carries current. This is essentially a transformer action. If the first conductor does carry
a time-varying current, then the skin-effect eddy current and the proximity-effect eddy current
superimpose to form the total eddy current distribution. Regardless of the induction mechanism,
eddy currents reduce the net current flow in the conductor and hence increase the ac resistance.
87
The distribution of eddy currents depends on the geometry of the conductor and its orientation
with respect to the impinging time-varying magnetic field. The most critical parameter pertaining
to eddy current effects is the skin depth δ which is defined as
δ=
ρ
πµf
5.1
where ρ, µ and f represent the resistivity in Ω-m, permeability in H/m, and frequency in Hz,
respectively. The skin depth is also known as the “depth of penetration” since it describes the
degree of penetration by the electric current and magnetic flux into the surface of a conductor at
high frequencies. The severity of the eddy current effect is determined by the ratio of skin depth
to the conductor thickness. The eddy current effect is negligible only if the depth of penetration is
much greater than the conductor thickness. Skin effect reduces the benefit of very thick top metal
layers found in modern processes. No matter how thick the metal layer is, if the skin depth is
smaller than the metal thickness the ac resistance will be skin depth limited. Since a spiral
inductor is a multi-conductor structure, eddy currents can potentially be caused by both proximity
and skin effects. Eddy currents can also be induced in the substrate and dissipate energy which
degrades the Q. Figure 5.6 shows the quality factor as a function of frequency and the different
factors impacting the Q as a function of frequency.
Because of the above limitations in the analytical formula, a 3D field solver that solves
Maxwell’s Equations [50] and that is calibrated to Silicon measurements is used to fine tune the
design and include all the above mentioned effects. The output of the solver is a scattering
parameter file that models the inductor. Once the design is finalized a compact macro model that
is frequency independent is developed to represent a broad band fit to the sp data. Such macro
model is used in the circuit analysis that uses the inductor in the next chapter.
88
Figure 5.6 Q vs. f showing different losses mechanisms
5.5.
Inductor Model and Substrate Parasitics
The differential inductor model developed is shown in figure 5.7. The model is symmetrical
around the center tap pin “port 3”. Three parallel sections of inductors are used to model the
distributed inductance effect of each half of the differential inductor Lsec, Lsec1, Lsec2. The three
inductors are “de-qued” by series resistors that model ohmic losses, skin effect and proximity
effect losses in the windings Rsec, Rsec1, Rsec2. Ccoup models the turn to turn capacitance and
capacitance to the underpass and the cross under. The center tap has its inductor and resistor Rct
and Lct. Mutual coupling coefficient K1 models the positive mutual inductance between the two
halves of the differential inductor. The substrate loss of the center tap is modeled by Csh2 and
Rsh2, while the major substrate network is that assigned to port 1 and port 2. Cox models the
oxide capacitance between the inductor metal coils and the substrate, Csh1 and Rsh1 model the
capacitive and resistive substrate model as discussed in chapter two. They also model the ohmic,
eddy and displacement current induced in the substrate. The model is parameterized and a circuit
optimizer is used to find the values of the 15 parameters of the model that fits the sp file produced
by the 3D field solver. Figure 5.8 shows the test bench used to perform such optimization.
89
Figure 5.7 differential inductor macro model
90
91
The test bench has the sp module that results from the 3D field solver connected to ports 3 and 4,
while the macro model shown above is connected to ports 1 and 2. Sp simulation is run and six
measurement equations are set and six corresponding optimization goals are minimized. The goal
here is to match the sp of the macro model to the sp of the 3D solver. The first four measurement
equations and goals are used to optimize the difference in sp between the sp file and the model to
zero. While the second goals are used to optimize the delta Qdiff “DQ” and delta Ldiff “DL”
S111=mag((S(1,1)-S(3,3))/S(3,3))
5.2
S221=mag((S(2,2)-S(4,4))/S(4,4))
5.3
S121=mag((S(1,2)-S(3,4))/S(3,4))
5.4
S211=mag((S(2,1)-S(4,3))/S(4,3))
5.5
DQ=(imag(Z(1,1)+Z(2,2)-2*Z(1,2))/real(Z(1,1)+Z(2,2)-2*Z(1,2))-imag(Z(3,3)+Z(4,4)2*Z(3,4))/real(Z(3,3)+Z(4,4)-2*Z(3,4)))/imag(Z(3,3)+Z(4,4)-2*Z(3,4))/real(Z(3,3)+Z(4,4)-2*Z(3,4)) 5.6
DL=((imag(Z(1,1)+Z(2,2)-2*Z(1,2))/(2*pi*freq))-(imag(Z(3,3)+Z(4,4)2*Z(3,4))/(2*pi*freq)))/(imag(Z(3,3)+Z(4,4)-2*Z(3,4))/(2*pi*freq))
5.7
The physical origin of Rsh1 is the silicon conductivity which is predominately determined by the
majority carrier concentration. Csh1 models the high-frequency capacitive effects occurring in the
semiconductor as discussed in chapter 2. For spiral inductors on silicon, the lateral dimensions are
typically a few hundred micro-meters which is much larger than the oxide thickness and is
comparable to the silicon thickness. Hence, the substrate capacitance and resistance are approx.
proportional to the area occupied by the inductor and can be estimated by a // plate formula
Cox =
1 εox
A.
2 tox
5.8
Csh1 =
1
A.Csub
2
5.9
Rsh1 =
2
A.Gsub
5.10
92
Where A is the inductor total area, εox and tox denotes the dielectric constant and thickness of the
oxide layer between the inductor and the substrate. Csub and Gsub are capacitance and
conductance per unit area for the silicon substrate.
5.6.
Calibrating the field solver
The field solver is fed with the dielectric and metal stack information which include the
conductivities, thicknesses, relative distances and dielectric constants of the metal layers used in
the process technology as well as the dielectric layers. The simulation is compared to the
measured data, and the stack information is tweaked to match the measurements. The
measurement was done over the corners of the design space, to ensure scalability. In most cases
the DC inductance was close to the analytical prediction (not the L at fo, which is not predicted
by the analytical formula) while Q of the analytical formula was off by ~ 20-25% depending on
the frequency and the inductor geometry and topology. Figure 5.9 shows the simulation vs.
measurement for three differential inductors designed using a stack of the upper two metal layers.
The relevant process information is summarized in table 5.2. Figure 5.9 shows the simulation vs.
measurement data after de-embedding. Appendix B explains the measurement details. The
inductor parameters are shown on the plots and they vary from 180µm outer diameter to 120µm,
and coil width of 11µm to 4.7µm. The target differential inductance is 3.6nH @ 3.2 GHz and
Qmin is 8 @ 3.2GHz. Figure 5.10 is a zoom in on the inductance chart near the operating
frequency as well as the three dimensional view of the stacked differential inductor. Measurement
and de-embedding technique is identical to that discussed in chapter two.
93
Top metal thickness =1 µm
n-1 metal thickness = 0.6 µm
top metal distance to substrate = 5 µm
n-1 metal distance to substrate = 4 µm
sheet rho of top metal layer = 20Ω/□
sheet rho of n-1 metal layer = 35Ω/□
Substrate resistivity = 10Ω.cm
Table 5.2 process information relevant to the inductor design
Q (OD=180, w=11, S=0.5, N=5)
Q (OD=155, w=8.2, S=0.6, N=5)
Q (OD=120, w=4.7, S=0,6, N=5)
Q_OD=180_measured
Q_OD=155_measured
Q_OD=120_measured
Quality factor vs. freq
12
Inductance vs. freq
25
10
L (OD=180, w=11, S=0.5, N=5)
L (OD=155, w=8.2, S=0.6, N=5)
L (OD=120, w=4.7, S=0.6, N=5)
L_OD=180_measured
L_OD=155_measured
L_OD=120_measured
20
L (nH)
Q
8
6
15
10
4
5
2
0
0
0
1
2
3
4
5
6
7
8
9
10
11
12
0
freq (GHz)
1
2
3
4
5
6
7
freq (GHz)
Figure 5.9 Q and L simulation vs. measurement
94
8
9
10
11
12
Inductance vs. freq
4
L (OD=180, w=11, S=0.5, N=5)
L (OD=155, w=8.2, S=0.6, N=5)
L (OD=120, w=4.7, S=0.6, N=5)
L_OD=180_measured
L_OD=155_measured
L_OD=120_measured
3.9
3.8
L (nH)
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3
0
1
2
3
4
freq (GHz)
Figure 5.10 Q and L simulation vs. measurement zoom in (left), parallel differential inductor (right)
Figure 5.9 illustrates the effect of layout area on three inductors with the same inductance but
different layout parameters. Three 3.6-nH inductors are designed with outer dimensions equal to
180, 155, and 120µm. The inductors fabricated using larger area can accommodate wider line
width; and as a result, achieve lower dc series resistance. However, they also have more shunt
substrate parasitics because they occupy larger area. At low frequencies, the larger inductors offer
higher quality factors because of lower series resistance. At high frequencies, the substrate effects
dominate and the smaller inductors actually achieve higher quality factors.
5.7.
Model fit
The distributed inductor topology together with the substrate network discussed above shows
an excellent fit to the sp file generated by the 3D field solver over a broad frequency range. The
model together with the optimization methodology provides a perfect fit for a very wide range of
inductors of different geometries, topologies and frequency of operation Figure 5.11 shows the
Qdiff_f (differential quality factor based on the sp file “f”) overlaid on the Qdiff_m (differential
95
quality factor based on the macro model “m”). DQ1 and DL1 are the percentage errors between
the sp file and the macro model. The inductor parameters are shown in figure 5.12, together with
the macro model and the fitting parameters. The specs are 3.6nH @ 3.2 GHz and Qmin is 8 @
3.2GHz. The same model topology is used at an operating frequency of 10GHz as shown in
figures 5.13. In this case also the model accuracy is well within 5% of the sp file across a broad
band of frequency. The self resonance, peak frequency and DC inductance are also accurately
captured by the macro model.
Figure 5.11 Q and L macro model fit vs. sp file and percentage error
96
Figure 5.12 inductor parameters (left) macro model and its fitting parameters (right)
Figure 5.13 Q and L macro model fit vs. sp file and percentage error (left) inductor parameters
(right)
97
Figure 5.14 macro model fitting parameters
5.8.
DFM effects
In this section the impact of the design for manufacturing effects on the inductor performance
is studied. The effects are namely, placing an inductor near a bump, process, temperature
variation and metal fill. Placing the inductor near a metal bump disturbs the magnetic flux that is
coupled to the inductor and hence the L and Q of the inductor are impacted. Metal fill or
dummification is the process by which almost all the process layers as well as vias are required to
be present in a specific size target window (the window size and the window stepping distance
depend on the layer under study) such that its density should be larger than a minimum and
smaller than a maximum percentage density. In oxide chemical-mechanical polishing (CMP)
98
processes, layout pattern dependent variation in the inter level dielectric (ILD) thickness can
reduce yield and impact circuit performance. Metal-fill patterning practices have emerged as a
technique for substantially reducing layout pattern dependent ILD thickness variation [52], [53].
Since inductors occupy large area, waiving the metal fill in the inductor area can impact the
inductor yield and render it malfunctioning. Process and temperature variation will impact the
dielectric and metal stack relative location, dielectric constant and metal conductivity as well as
substrate resistivity; such parameters have a direct impact on the inductor performance.
5.8.1. Impact of bumps
Figure 5.15 shows three relative positions of an on-chip inductor relative to the package
bumps. The distance “d” is varied and the impact of the bump location on the L and Q of the
inductor is simulated and results are given in Figure 5.16. The simulations compare the inductor
performance without bumps and with the bumps spaced at d=40um, 20um, 5um and -15um. The
middle figure of 5.15 shows the d=-15um which is an overlap of 15um between the inductor body
and the bumps. Also the case where the bump is right on top of the inductor is compared. The
simulation results show that unless the inductor is centered between the bumps and kept away by
at least 20um, the Q and L will be impacted badly. The worse case scenario is when the bump is
right on top of the inductor. In this case the Q dropped by more than 50% and L dropped by more
than 60%. The overlap case is also not recommended since Q lost 16% of its value at the
operating frequency and L lost about 14% of its DC value. When the distance d=5um the Q and L
lose about 5% of their value, while when d=20um the Q, L are almost not affected (only 1%
degradation if compared to the no bump case).
99
Figure 5.15 Bump relative positions to the on-chip inductor
Q vs. f showing bump effect
10.4
L (nH) vs. f showing bump effect
4
3.5
L (nH)
10
without bumps
with bump d=40um
with bump d=20um
with bump d=5um
with bump d=-15um
with bump on top
Q
9.6
3
without bumps
with bump d=40um
with bump d=20um
with bump d=5um
with bump d=-15um
with bump on top
9.2
2.5
8.8
2
8.4
1.5
8
3
4
freq (GHz ) 5
6
0
7
2
freq (GHz )
3
4
5
L (nH) vs. f showing bump effect zoom out
Q vs. f showing bump effect zoom out
12
25
without bumps
with bump d=40um
with bump d=20um
with bump d=5um
with bump d=-15um
with bump on top
8
6
without bumps
with bump d=40um
with bump d=20um
with bump d=5um
with bump d=-15um
with bump on top
20
L (nH)
10
Q
1
15
10
4
5
2
0
0
0
5
freq (GHz ) 10
15
20
0
5
freq 10
(GHz)
15
Figure 5.16 Impact of bumps on the inductor Q and L (OD=120um, W=4.7um, S=0.6um, N=5)
100
20
5.8.2. Impact of temperature variation
The impact of temperature on the inductor performance is studied in this section. The substrate
resistivity increases as the temperature increases due to the decrease in carrier mobility at high
temperature that is caused by the increase in lattice vibration and lattice scattering of the carriers
[51]. The thermal motion of the carriers at high temperature also adds to the increase in substrate
resistivity as temperature rises. Increase in substrate resistivity enhances the inductor quality
factor because of less substrate induced eddy currents and capacitively coupled currents. On the
other hand the metal resistivity rises with temperature and this increases the inductor ohmic loss,
which will negatively impact the inductor quality factor. Thus two phenomena are competing for
the inductor quality factor, and their individual impact is approximately balanced out. Figure 5.17
shows the simulations results of such impact. The substrate and metal temperatures are increased
one at a time and then they are simultaneously increased to get the combined effect. The
inductance is not impacted much by the variation is temperature as it depends mainly on the
geometry of the structure; the self resonance is very slightly impacted, while the quality factor is
impacted. Compared to room temperature, the combined impact of substrate and metal resistivity
change degrades the inductor Q by about 5 %. This indicated that the ohmic loss at this operating
frequency (3.2 GHz) is more dominant than the substrate losses.
101
Diff ind Q vs. f, OD=120um , w =4.7um , S=0.6um , N=5
Diff ind L vs. f, OD=120um , w =4.7um , S=0.6um , N=5
Metals_temp=115 C
12
25
Substrate_temp=115 C
Substrate_temp=115 C
Metals_temp=115 C
Substrate & Metals temp=115 C
Room temp
Substrate & Metals temp =115 C
Room temp
10
20
8
L (nH)
Q
15
6
10
4
5
2
0
0
0
1
2
3
4
5
6
7
8
9
10
11
freq in GHz
0
1
2
3
4
5
6
7
8
9
10
11
freq in GHz
Figure 5.17 impact of temperature on the inductor Q and L
The increase of substrate resistivity helps improve Q, especially at the higher frequencies. The
overall relative change in peak Q is ~ 5%. At low frequencies, room temperature and substrateonly curves overlap because substrate coupling is relatively negligible. Likewise, the lowfrequency portions of metal-only and metal & substrate curves overlap because metal loss is
predominant at low frequencies.
5.8.3. Impact of process variation
The process technology corners or process “skews” impact the metal and dielectric stack
parameters and their relative positions. The metal conductivities, dielectric constants and doping
concentration vary from wafer to wafer and from lot to lot. This variation must be taken into
consideration during design and modeling the inductors. Figure 5.18 shows the simulation results
of the Q and L plots of an inductor (OD=120um, W=4.7um, S=0.6um, N=5) under typical, slow
and fast process corners. These process corners are the three sigma process window for the metal
and dielectric stack parameters. Such variation should be used in conjunction with the transistor
model process, voltage and temperature corners during the circuit design where inductors are
used. Table 5.3 shows the process corners definition and how relative thicknesses are changed
102
and their impact on the parasitic interconnect resistance and capacitance. It is clear that for the
slow corner where the resistance is less than the typical value and capacitance is more than the
typical value, the Q increases and the self resonance decreases. For the fast corner the reverse is
true. Both process and temperature variations model can be combined for the inductor. This will
yield nine corners (slow cold, slow room, slow hot, typical cold, typical room, typical hot, fast
cold, fast room, fast hot) and used in “PVT” process, voltage, temperature simulations during
circuit design and validation. The design should be robust enough to accommodate the inductor
performance variation across process and temperature.
Skew ILD Thickness
Metal Thickness
R
C
fast
Increase
Decrease
Increase
Decrease
slow
Decrease
Increase
Decrease
Increase
Table 5.3 process corner definition
Diff ind Q vs. f, OD=120um, w=4.7um, S=0.6um, N=5
Diff ind L vs. f, OD=120um, w=4.7um, S=0.6um, N=5
12
25
typical
slow
fast
10
typical
slow
fast
20
freq (GHz)
Q
8
6
4
2
15
10
5
0
0
0
1
2
3
4
5
6
freq in GHz
7
8
9
10
11
0
1
2
3
4
5
6
7
8
9
10
11
L (nH)
Figure 5.18 impact of process variation on inductor performance.
5.8.4. Impact of metal fill
Metal fill is the processes by which metals, poly, vias and diffusion are added to the
layout as dummy cells to ensure uniform density of all layers that is needed to prevent inter level
103
dielectric ILD “dishing” or valley formation if there are very high and/or very low density areas.
[52], [53]. Adding metal dummies in the neighborhood of on chip inductors, if not designed
properly can increase capacitive coupling and eddy currents that may impact the inductor
performance. Figure 5.19, 20 and 21 shows the dummy fill patterns that are recommended to
minimize the impact on the inductor performance. Small islands of metal are symmetrically
spaced around the inductor coil. Figure 5.19 (left) shows how the metal fill of the top metal layer
is placed around the inductor top metal; much less dense islands are placed near the inductor,
while denser metal fill is placed away from the inductor. The middle figure shows the n-1 metal
fill together with the n-1 metal coil (inductor is designed using top metal and n-1 metal stacked in
parallel). The figure on the right is the pattern of the n-2 metal, note the less dense pattern under
the inductor body to minimize capacitive coupling. Figure 5.20 (left) shows the pattern of the rest
of the metal layers, while the one on the (right) shows the poly and diffusion pattern. Figure 5.21
shows the dummy via fill pattern, no via is stacked together to minimize capacitive coupling to
the substrate. The impact of the dummy fill on the Q and L of the differential inductor is shown in
figure 5.22. This dummification technique has a minimal impact of L, while the Q is impacted by
less than 4%.
Figure 5.19 inductor with metal fill patterns, top metal (left), n-1 metal (middle), n-2 metal (right)
104
Figure 5.20 inductor with metal fill patterns, metal 1, (left), ploy, ndiff, pdiff (right)
Figure 5.21 inductor with via fill patterns
Q vs. f OD=120um, W=4.7um, S=0.6um, N=5
11
10
9
8
7
6
5
4
3
2
1
0
L vs. f OD=120um, W=4.7um, S=0.6um, N=5
undummified
dummified
3.7
L (nH)
Q
undummified
dummified
3.6
3.5
3.4
3.3
3.2
3.1
0
0
1
2
3
4
5 6 7
freq (GHz)
8
9
0.8
10 11
1.6
2.4
freq (GHz)
Figure 5.22 impact of dummification on Q and L
105
3.2
4
5.9. Conclusion
In this chapter an inductor design flow is developed based on analytical formulas that explore
the design space and a commercial 3D field solver that is calibrated to silicon measurements and
that takes into account the substrate parasitics not modeled in the analytical formula. A special
emphasis is put on the substrate effects that impact the on chip inductor performance. A compact
macro model is developed that shows a very good fit to the sp file over a broad frequency band.
The design for manufacturing effects is studied and design recommendations are given to design
the on chip inductors taking into consideration yield implications and process and temperature
variations.
106
CHAPTER 6
CASE STUDIES FOR THE IMPACTS AND REMEDIES OF
SUBSTRATE NOISE COUPLING
6.1.
Introduction
The problem of substrate noise coupling on the system level is very hard to attack. As the
number of devices in the design increases it becomes difficult to take the entire system netlist to a
simulator and simulate the over all system performance. Simulation time and simulator capacity
become two major road blocks in any production worthy design. The interconnect parasitics
within blocks and those of the top level routing that connect blocks together adds to the size of
the netlist and in many cases causes the simulator to run out of capacity and/or face conversion
and runtime issues specially in RF designs where the simulations are based on complex Harmonic
balance [54] or periodic steady state algorithms [55]. If we are to add to that the substrate model
of the entire system to simulate the noise coupling between major blocks specially in the presence
of the digital signal processing block or a high power interfering signal “blocker”, we will be
making it harder for the design environment to handle the problem. For such system level
validation problems the industry has come with fast spice simulators and behavior level modeling
to aid the issue of system level verification, but both have their limitations. First fast spice solvers
are transient only based and in an RF chip where inter-modulation and phase noise with and
without a blocker are important, it requires very careful simulation setups and fast Fourier
107
transformation to go back and forth between transient and frequency domains and in going back
and forth quantization errors are inevitable, in addition to the simulation setups and runtime
hurdles. For behavioral modeling it is fairly impossible to model the substrate noise coupling
except if you take measurements and fit Si data to the behavioral model, which is too late in the
design cycle. Also scalability is another issue in the behavioral modeling. In our design flow the
substrate network is selectively added only to critical portions of the system where substrate
coupling matters, while the rest of the system remains without such model to achieve the needed
compromise between accuracy on one side and capacity and speed on the other side.
6.2.
System Level Case study.
Our case study for the substrate noise coupling on the system level can be summarized as
follows. The design at hand is a quad band RF front end receiver for cellular application. Figure
6.1 shows the high level block diagram of such receiver [56]. Four LNA’s are present to handle
the quad band input signal. A VCO representing the local oscillator “LO” and the LO path, that
contains the frequency dividers, feeds a quadrature mixer for frequency down conversion. A filter
with an automatic gain control is used to produce the final quadrature signals. A digital controller
block receivers a serial interface input and provides control signals to all the blocks on chip. Two
versions of this chip were measured, version A and B, and the problem statement is as follows.
Figure 6.1 Block diagram of the RF receiver used in the case study
108
Version A was marginally meeting some system specs while failing others, some of its blocks
were not meeting the block spec. Version B, the enhanced version, was meeting all the block
specs. For the entire system, the carrier to noise ratio C/N of the entire receiver chain in the
presence of a strong CW (continuous wave) blocker signal 3MHz away from the carrier at the
high band (1.9GHz) is failing the spec., (Version A does not have this specific problem). So the
goal of this study is to: use the substrate noise coupling design flow developed and calibrated in
chapters two and three and the design guide developed in chapter four to analyze the VCO and
blocker signals coupling through the substrate for the two versions of the chip, and look for
discrepancies that may explain the different blocker performance on the two designs, then provide
a solution for this problem to pass the system spec.
6.2.1.
Background
The phase noise “PN” performance of an LO signal plays a key role for the overall
performance of the wireless system by determining how closely channels can be placed in
narrow-band systems and how closely constellation points can be placed in the I/Q plane in
digital modulated systems. The first PN specification dictates the phase noise power level with
respect to carrier at a given offset frequency from the carrier (dBc/Hz). This specification is
usually important in narrow-band systems such as cellular systems. The cellular standards strictly
define the radio performance parameters in great details for efficient use of the licensed RF bands
to accommodate more users. The second PN specification dictates the integrated phase noise
performance over the signal bandwidth. The second specification is usually more important in
broadband systems (WLAN) where high data rate is transmitted to a short distance using a wide
bandwidth channel [44]. The PN specification of a frequency synthesizer at a given offset
frequency can be determined from the wireless standard specified blocker performance [38]. The
undesired sideband energy from the LO phase noise reciprocal mixes with the in-band or out-of109
band undesired signals to generate the interfering signal, I, within the desired signal band. The
power levels for blockers along with the desired signal and the required BER “bit error rate”,
which translates to a minimum C/I at the receiver output, are given by the RF standards. It is
assumed that a system noise floor, N, which include receiver front end noise (from antenna to
mixer output) is present at the mixer output. The interfering signal I generated by reciprocal
mixing of blocker with the phase noise at the mixer output will add up to the receiver noise in the
desired band as shown in Figure 6.2. The total undesired signal level at the mixer output will be
the sum of the front-end system noise and interfering signal caused by reciprocal mixing N+I.
The phase noise specification for given blocker levels and C/I at specified frequency can be
calculated using the equation [44].
PN(fspec)<Pd -Pb(fspec) -10log(BW)-C/I………..(6.1)
Where:
PN(fspec) in dbc/Hz is the phase noise specification of the LO signal at the frequency offset, fspec
Pd in dbm is the desired signal power level.
Pb(fspec) in dbm is the blocker power level at the frequency offset, fspec
BW in Hz is the signal bandwidth.
C/I in db is the required minimum carrier-to-interference level.
It should be noted that blockers degrade the receiver performance in three different
mechanisms; reciprocal mixing (local oscillator phase noise), gain desensitization (compression
of amplifier, 1-dB compression point), and inter-modulation (IM) distortion. Reciprocal mixing
effect has been discussed above. The gain desensitization and IM distortion have implications on
the front-end linearity. Furthermore, there will be other interfering signals falling into the desired
band in addition to the interferer caused by the blockers. The other interferer will come from
image signals, second-order distortion (IP2), and spurious mixing products (2RF-3LO, etc.). The
input IP2 performance is of particular significance in a direct-conversion (zero IF) receiver since
110
second order nonlinearity effects can down-convert continuous wave (CW) as well as AM
modulated blockers to DC or near DC. The image signal is more of a concern for low IF and
wide-band IF receiver architectures. The spurious mixing products appear in wide-band IF
receivers. These should be taken into consideration in the calculation receiver specification [44].
6.2.2. Design Data
Figure 6.3 and table 6.1 shows the design data for this case study.
With no blocker & 80kHz BW,
Cout=-99 + 12+10 = -77 dBm,
Nout1= thermal noise power + 10 log (BW) + Gain1 + Gain2 +NF1 +NF2/Gain1
Nout1 = -174 +10log(80k) +12+10+2+12/10 = -99 dBm
Thus C/N (no blocker)= 22 dB
With Pb= -26 dBm, PN = -135 dBc/Hz
Nout2 = PN + 10log(BW)+Pb*Gain1*Gain2 + Nout1
Nout2 = -135 + 49 + -26 + 12 +10 + Nout1 = -90 dBm + Nout1
= -90 dBm – 99 dBm = -89.5 dBm
Thus C/N (with blocker)= 12.5 dB
Table 6.1 C/N calculations for the receiver chain
The specs of the high band (1.9GHz) C/N is 9 dB, while the design calculations assumes 12.5 dB,
which is 3.5 dB better than the spec. Per silicon measurement data, of the breakouts, each block
was meeting its spec specially the VCO phase noise, yet the carrier to noise ratio in the presence
of a strong CW blocker signal 3MHz away from the carrier was failing spec by 1 to 2 dB. Since
all the block specs were met, the focus is shifted to the top level block interaction namely the
interconnect parasitics that may couple undesirable noise between blocks as well as the
111
underlying substrate as a media that propagate noise, which may add to the output noise and
degrades the C/N ratio. As shown in figure 6.3, the phase noise of the local oscillator (1.9GHz) at
3MHz mixes with the 3MHz blocker and produces noise at the carrier that decrease the carrier to
noise ratio. The model for the extra noise that may cause the C/N to degrade further is shown in
figure 6.4. The signal of the VCO core that is running at 3.8GHz can mix with the 2nd harmonic
of the high band blocker and produce extra in band noise. Both these signals can make their way
to the mixer inputs via substrate coupling as well as coupling through the interconnect parasitics.
The following section studies the noise coupling according to the above model, through the
substrate and interconnects, and modifies the design to increase the C/N above the spec limit,
without impacting other specs.
After being fed by the process information and after tuning the runsets not to double
count the substrate network found in the device models. The substrate design flow extracts the
substrate model as an R-C mesh extracted at a specific frequency of interest. The flow then based
on the above information attach the substrate R-C mesh to the design netlist (with routing
interconnect parasitics included) where the substrate access ports are defined, and where the
devices are connected to the substrate as described in chapter two. Perturbing and sensitive nodes
are defined. A small signal analysis is performed on the system netlist to view noise contours and
noise distribution levels at various locations on the chip due to a noise source. Design is altered to
add substrate noise isolation structures and there effect is simulated.
The perturbing nodes are set to be the local oscillator ground (3.8GHz) this is at the
output of the VCO buffer, and LNA ground (3.8GHz, 2nd harmonic of the blocker)
Noise contours using small signal AC analysis is calculated based on these two sources, one at a
time and combined (superposition as it is a small signal analysis). Package/bond wire parasitics
are also accounted for.
112
Figure 6.2 LO phase noise specification
Figure 6.3 LO phase noise mixing data
113
Figure 6.4 substrate noise coupling model
Figure 6.5 shows the layout of the VCO, LO and the mixer of both versions of the chip
and the perturbation node for the sake of simulating the substrate noise coupling of the 3.8GHz
signal of the VCO core to the mixer input. Figure 6.6 shows the noise distribution assuming a
unity noise source at the perturbation node (0 dB level at the ground connection of the VCO
core). The color code that shows the noise contour levels relative to the noise source is also
shown. The coupled noise level at the mixer input is also shown at the victim node.
Figure 6.5 layout of the VCO, LO and mixer
114
Figure 6.6 substrate noise coupling distribution (case of vco perturbation)
Figure 6.7 substrate noise coupling distribution (case of blocker perturbation)
Figure 6.7 shows the noise contours for the case of a perturbation noise source at the input of the
chain (LNA ground connection) to represent the 3.8GHz signal of the blocker 2nd harmonic of the
high band. The level of the coupled noise at the mixer input is shown. Table 6.2 summarizes the
data for the above cases, for all cases the interconnect parasitics are included in the simulation
model along with the substrate model.
Version A
Version B
VCO core perturbation VCO core perturbation
-68 dBc
-65.4 dBc
Version A
Blk 2nd Harm.
Perturbation
-32.6 dBc
Version B
Blk 2nd Harm.
perturbation
-32 dBc
Table 6.2 substrate noise coupling level at mixer input relative to the noise source
115
Version A shows better Substrate noise isolation than Version B by approx ~ 2.6 dB from the
3.8GHz of the VCO. Studying the two layouts, this is found to be due to less substrate taps in the
mixer connected to the mixer ground as shown in figure 6.8. The distance between VCO buffer
and first div is larger in Version A than Version B by ~ 40um. The distance between VCO output
and the mixer assembly is larger in Version A than Version B by ~ 25um.
Figure 6.8 layout comparison of both versions
The action taken to decrease Version B noise coupling with no changes to the design that can
affect other specs is to isolate the VCO block further without changing the grounding schemes,
package, and pad frame. This is done by adding double deep trenches in and around the VCO
block as shown in figure 6.9. Deep trenches are regions in the substrate with oxide trench that
goes deep into the substrate. Double deep trenches are added around each divider, around each
buffer and around the entire LO block. The noise distribution levels before and after this
modification is shown in figures 6.10. The noise level around the dividers and at the boundary of
the block seams to be “cooler” in the plot on the right. Table 6.3 summaries the noise levels at the
victim points in figure 6.9; with and without adding the deep trenches.
116
Figure 6.9 Adding deep trenches in and around the VCO.
Figure 6.10 Noise levels without deep trenches added (left), and with deep trenches added (right)
Probe points
1
With DT (dBc)
-54.6
Without DT (dBc)
-38
2
-53
-36
3
4
-52
-48
-27.8
-18
5
-39
-10
Table 6.3 substrate noise coupling level at victim points with and without deep trenches
117
The noise levels in the VCO block after adding the DT is much less than the original case without
the deep trenches. The modified VCO with DT added is placed on the top level and its noise
coupling to the mixer input is re-simulated and compared to versions A and B.
Figure 6.11 Noise aggressor and victim points using the modified VCO (left), noise levels (right)
Figure 6.11 shows the modified VCO and mixer layout and the locations of the aggressor and the
victim points, (points 1, 2, 3 are at the mixer input), together with the substrate noise level
contours. Table 6.4 summaries the noise level at these victim points for the three cases under
study, version A, version B and the modified version B. It is clear that adding the isolation
structures in the modified version B enhances the substrate noise isolation between the vco core
and the mixer if compared to both version A and B. Note that this is done with no change to the
design what so ever, so it is considered a low risk edit. Doing so reduced the extra noise that
couples to the output of the mixer and increase C/N to pass the spec limit. Figure 6.12 shows a
die photo of the VCO, mixer, LO and LNA assembly.
118
Victim Version Version
points
A
B
1
-68
-65.4
Modified
version B
-71.8
2
-68.1
-66.2
-70.6
3
-68.4
-66.3
-70.3
4
-41.9
-37.8
-54.8
5
-41.7
-37.7
-54.7
6
-41.6
-36.3
-53.6
7
-41.1
-27.8
-52.4
8
-41.1
-27.9
-52.3
9
-40.9
-18.8
-50.4
10
-40.9
-18.8
-50.3
11
-16
-10
-41.4
Table 6.4 substrate noise coupling level at victim points for all three versions
Figure 6.12 A die photograph showing the VCO mixer section.
119
6.3.
Block Level Case study
In the previous section, the substrate noise interaction between circuit blocks in a system is
studied. In this section the substrate noise within a block is studied. The test case at hand is a
transmit buffer. A transmit buffer is a pre power amplifier voltage buffer for the high band
cellular application 1.9GHz. The buffer is designed to isolate the output of the transmit chain
VCO from the input of the PA. This is done to prevent VCO pulling by the PA by introducing a
high reverse isolation block that will separate the VCO and the PA. As this buffer is in the phase
path of the phase modulation in the transmit path, its amplitude response is not important and it is
designed to operate in saturation “above the P1dB” at the power levels that are being supplied
from the transmit chain for better power efficiency. As this buffer is used in the transmit path and
this path does not have sharp filtering, the phase noise contribution of this buffer must be kept to
an absolute minimum not to affect the phase noise of the transmit VCO, and its reverse isolation
must be kept at the absolute maximum to prevent transmit VCO pulling. The buffer is put on a
separate power domain than the TX VCO. The buffer is designed for a typical saturated output
power of +6dBm the high band, while the input power is specified between 0dBm to +7 dBm.
One of the most important specs is the reverse isolation, S12, for this reason, cascode transmit
buffer was chosen for the high band due to its high reverse isolation.
6.3.1. Design details
As shown in figure 6.13, a cascode high band buffer is designed to have a high reverse
isolation. The phase noise spec for the high band (is -140 dBc/Hz @ 20MHz offset). The buffer is
resistively loaded on the collector. The input and output are capacitively coupled on the PCB. The
bias circuit is a current mirror with a beta enhancer and an RC filter to stabilize the bias point.
The reference current is generated by a resistor to a regulated power supply of 2.75V. A nominal
dc current of 11mA biases the cascode topology. An RC feedback from the collector of the CE
transistor to its base is designed to establish negative feedback for stabilization and for input and
120
output matching. The whole package model is used during the design to utilize the package
parasitic in the input and output matching. The design is simulated with and without the substrate
model. The phase noise and reverse isolation simulation data in both cases are compared to
silicon data.
Figure 6.13 Transmit buffer schematic without substrate network.
Figure 6.14 Transmit buffer schematic with substrate network.
121
As shown in figure 6.14, the collectors of both transistors Q1 and Q2 have capacitance to
substrate C3 and C1 respectively. The base of Q2 is connected to a bond pad that has a bond pad
capacitance to the substrate C2, the resistors R1 to R5 represent a simplified substrate resistive
network. If the substrate model is not included in the circuit simulator, then the collector-tosubstrate capacitors will be connected to the ground. With the substrate model included, a
feedback path between the collector of Q1 “output of the buffer” and the base of Q2 “input of the
buffer” is established. This feedback will decrease the reverse isolation ‘S12” as the output signal
can be coupled back to the input through this feedback path, especially at high output power
level. The feedback loop will also impact the power gain and power output level. Figure 6.15
shows the power output and power gain as a function of the input power, simulation data with and
without the substrate model is plotted together with the silicon data. It is obvious that adding the
substrate model to the simulation is a better prediction of the silicon behavior.
Pout simulation w/ subst model
Power Gain simulation w/ subt model
Pout measurement
Power Gain measurement
Pout simulation w/o subst model
Power Gain simulation w/o subst model
20
15
10
5
0
-5
-20
-17.5
-15
-12.5
-10
-7.5
-5
-2.5
0
2.5
5
7.5
Pin in dBm
Figure 6.15 Pout and Pgain vs. Pin with and without substrate model vs. silicon data @ 1.9GHz
122
S12 measurment vs. simulation @ 1900MHz
-30
-32
S12 in db
-34
S12_measurement
S12 simulation w/o subst model
S12 simulation w/ subst model
-36
-38
-40
-42
-44
-20
-15
-10
-5
0
5
10
input power in dbm
Figure 6.16 S12 measured vs. simulation with and without substrate model @ 1.9GHz
Figure 6.16 shows the S12 simulation and measurement data, the simulation results
without the substrate model gives a more optimistic isolation value. It is also shown that the
substrate model decreases the isolation and matches the silicon behavior within 2dB. Appendix B
explains the measurement details.
Next the phase noise of the transmit buffer is analyzed. The phase noise of the buffer is
simulated with and without the substrate model. The thermal noise [57] of the substrate resistive
network acts as a white noise source and adds to the buffer phase noise. Figure 6.17 shows the
initial layout of the buffer Without any modification to the layout, the phase noise simulation
results with the substrate model added shows a significant degradation in the phase noise that was
not meeting the phase noise spec (-140 dBc/Hz @ 20MHz offset). Figure 6.19 shows the phase
noise simulation data with and without the substrate model. Since the result is not meeting the
spec, the substrate behavior is modified by editing the layout to increase the value of resistors R1
123
to R5. Figure 6.18 shows the addition of deep trenches under and around the transistors. This has
the effect of increasing the distance between the devices and the substrate bulk; hence it increases
the effective substrate resistance. In addition a guard ring is added around each transistor that will
sink the substrate noise current and reduce the bulk current which in effect increases the value of
the resistors bulk. Figure 6.19 compares the phase noise simulation data, with substrate model of
the unmodified layout, without the substrate model, with the substrate model of the modified
layout and finally the measured phase noise of the modified layout.
Figure 6.17 transmit buffer layout
Figure 6.18 transmit buffer layout
124
Transmit Buffer Phase Noise at (Carrier ~1.9GHz)
PN (dBc/Hz)
-80
-60
PN measured
-80
PN sim w/ subst model
modified layout
PN (dBc/Hz)
-60
Transmit Buffer Phase Noise at (Carrier ~1.9GHz)
-100
-120
PN sim w/ subst model unmod. layout
PN sim w/o subst model unmod layout
-100
-120
-140
-140
-160
1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07 1.00E+08
-160
1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07 1.00E+08
Offset freq (Hz)
Offset freq (Hz)
Figure 6.19 transmit buffer PN unmodified layout (right) modified layout and measurement (left)
It is clear from figure 6.19 (right) that the simulation results of the buffer phase noise,
without the substrate model meets the -140 dBc/Hz at 20MHz offset, while including the
substrate network of the unmodified layout, raises the thermal noise floor due to the thermal noise
associated with the substrate resistive network and shifts the phase noise at 20MHz offset
marginally above the specs. This indicates the importance of including the substrate network
during circuit simulation, without such effect, tapping out the buffer as is would render a part that
is marginally functional and hence its yield will be badly impacted. The layout is modified as
mentioned above to increase the substrate resistance and hence decrease the substrate thermal
current noise associated with the substrate resistive network. The phase noise simulation result is
shown in figure 6.19 (left), together with the measurement data of the phase noise of the modified
block. The phase noise meets the -140 dBc/Hz spec at 20MHz frequency offset. An overall good
match is achieved between simulation and measurement. The thermal noise floor is accurately
predicted by the simulator as shown by the good match of the phase noise measurement and
simulation at high frequency offset, while the flicker noise contribution of the phase noise is off
from the measurement data as shown at low frequency offset (usually the transistors flicker noise
model is on the optimistic side).
125
6.4.
Device Level Case study
As shown in the previous chapter, the performance of on chip inductors at RF frequencies
depends mainly on the substrate resistivity. As the substrate resistivity gets lower, the eddy
currents that can circulate in the substrate at these frequencies gets larger and causes energy
losses in the substrate. Such energy losses will lower the inductor quality factor, which impacts
lots of noise implications in RF systems. Guard rings are placed around on chip inductors to
isolate the substrate noise current generated by the inductor in the substrate from other noise
sensitive parts in the circuits. A very common example is a tuned low noise amplifier that uses
inductors as source (emitter) degeneration. In this case study the impact of the substrate isolation
structure “guard rings” placed around the inductor is studied. Guard rings placed around the
inductors can either improve or degrade the inductance and the quality factor depending on how
these rings are designed.
An inductor is used as a demonstration vehicle; a commercial electromagnetic 3D field
solver that is calibrated to silicon [50] as shown in the previous chapter is used to extract the
scattering parameters. The scattering parameters are then converted to Z parameters. The Z
parameters are used to calculate the inductance and the quality factor of the inductor as function
of frequency. Four cases are studied and compared in this case study. First, an inductor with no
guard ring around it. Second, the inductor with a closed loop guard ring around it (30um away
from the inductor body). Third, the inductor with a broken “open” guard ring around it (30um
away from the inductor body). Fourth, the inductor with a closed guard ring very close to the
inductor body (10um away from the inductor body). For the above cases the inductance and the
quality factor are compared and recommendations are concluded regarding the guard ring design
and its distance from the inductor. The parameters of the designed inductor together with the
relevant process technology parameters are listed in table 6.5. The inductor is a differential
inductor with a center tap. The cross unders and center tap are using lower metal level.
126
Square inductor 150um per side
Number of turns = 3
Width of coil = 18.5um
Spacing between the turns = 2.4um
Inductor metal has a sheet rho = 10mΩ/□,
Distance to substrate is 7um,
Substrate resistivity is 10Ω.cm
Table 6.5 inductor parameters
Figure 6.20 inductor test cases
Figure 6.20 shows the layout of the inductor with the above mentioned four scenarios. While
Figure 6.21 and figure 6.22 show the simulation results of L and Q respectively. It can be seen
from figure 6.21 that the most degradation in the inductance is caused for closed guard rings,
127
especially when the guard ring is closer to the inductor body. Substrate guard closed rings will act
as a closed loop that have a finite inductance and will have a negative “Lenz’s law” mutual
coupling with the differential inductor that gets bigger as the distance between the ring and the
inductor gets closer. Such negative mutual coupling will decrease the effective inductance of the
designed inductor as compared to the inductance without the guard ring altogether; as shown by
the two bottom plots in figure 6.21. It is also clear that such degradation is not present for the case
of a broken guard ring, where the guard ring loop is not complete and the mutual inductance is
not any more present. As the frequency increases towards the self resonance frequency the
inductor capacitance to the guard ring raises the total capacitance to the substrate by adding a
parallel capacitance to the inductor-substrate cap. This parallel cap is the inductor to guard ring
cap. This decreases the self resonance frequency. This is shown by the case of the broken guard
ring inductance increasing faster than the no guard ring at high frequencies. This is a minor
impact and can be neglected if compared to the benefit of the guard ring in sinking the substrate
noise current around the inductor.
Differential inductance vs. freq
1.1E-09
Inductance (H)
1.0E-09
tighter closed guard ring
closed guard ring
broken guard ring
no guard ring
9.0E-10
8.0E-10
7.0E-10
6.0E-10
5.0E-10
0.00E+00
5.00E+09
1.00E+10
1.50E+10
2.00E+10
Freq (Hz)
Figure 6.21 inductance vs. freq for the four test cases
128
Examining the quality factor plot in figure 6.22, shows that closed guards ring will lower the
inductor quality factor due to the lower inductance. As the ring gets closer to the inductor; the
quality factor is reduced more. The broken guard ring does not cause the quality factor to
degrade, and hence the recommendation is to place a broken guard ring around the inductor, or if
this is not allowed by the routing constraints it is highly recommended to place the guard ring at a
large distance away from the inductor body.
Q vs. freq
10
9
8
7
Q
6
5
4
3
2
1
5E-10
0.00E+00
closed guard ring
tighter closed gurad ring
broken guard ring
no guard ring
5.00E+09
1.00E+10
1.50E+10
2.00E+10
Freq (Hz)
Figure 6.22 Quality factor vs. freq for the four test cases
6.5.
Conclusion
In this chapter three case studies are presented to explore the substrate noise coupling on the
system level where the different blocks are interacting, within a block where the noise coupling is
generated and coupled within a block and finally on the device level where the substrate isolation
structure may affect the device performance. In all three cases, the design flow that is developed
129
in this research is utilized to debug and pin point the problem. This is an important step before
applying the learning of the substrate isolation guide that is developed to minimize or eliminate
the coupling the hence solve the problem at hand. It was shown that in some cases the substrate
noise coupling may cause the yield to degrade or even the design to fail the specifications.
Uncovering and fixing such issues before tape out is an invaluable saving to time to market,
resources and gross margins.
130
CHAPTER 7
CONCLUSION AND FUTURE WORK
The challenge of overcoming the substrate noise coupling in deep submicron
technologies is becoming an increasing problem that faces designers and system architects. In this
research a substrate aware design flow is designed and calibrated and used in the design phase as
part of the design and validation methodology. The design flow is used to develop a design guide
to minimize the substrate noise coupling and assist the floor planning, power and ground routing.
The design of the different isolation structures is studied in details, their geometries, topologies
and bias are presented. Package parasitics and the frequency of operation were also accounted for
in the set of parameters that impact the signal isolation level. Industrial case studies are presented
where the substrate noise coupling manifests itself as a problem that causes a device, a block or a
system to malfunction. The cases are studied using the developed design flow and its simulation
infrastructure. In every step along the way simulation is validated by silicon measurement and
solid recommendations and remedies are provided. An inductor design flow is developed and
used to design high quality factor inductors, while taking into consideration design for
manufacturing effects that are not any more second order effects that can be neglected. The
substrate parameters and parasitics that impact the inductor performance are studied and
recommendation for placing the substrate isolation structures around the inductors is presented as
a conclusion.
131
The CAD tools found in the industry that are dedicated for such analysis are extremely
few, literally there is only one tool [58] that is commercially available and by all means is not
something that you can plug and play in the design environment, lots of calibration work needs to
be done before the results out of this tool can be trusted. More research is needed to come up with
other algorithms that can evolve to commercial tools that can be used as part of the design flow
and validation methodologies. Tools that take into consideration the complexity and number of
transistors in today’s “SOC”.
The magnitude of substrate coupling depends strongly on the type of the package used in
the IC. This dependence can be caused by the value of the bond-wire inductances or the
availability of good backplane contacts in a package which will influence the degree of coupling.
A comparison of substrate noise coupling in new packaging technologies such as multi chip
modules and flip chip packages and high end sockets need to be performed.
A more productive approach to handle the substrate noise issue is to model the noise
created by the aggressor circuitry that is injected in the substrate and include it in the analog
circuit simulators similar to device thermal and flicker noise that are now a main part of the
device models needed for RF and high speed designs. In a large design, the digital noise sources
cannot be explicitly identified. Noise is generated across the chip by the large number of gates
transitioning. If the chip is fabricated on a lightly doped bulk substrate, the locations of the noise
sources are needed. This is a more difficult problem, and an estimation of the switching
capacitance to the substrate would be necessary for each area of the chip. An experimental chip
may be necessary to prove the validity of any digital noise source models.
132
APPENDIX A
SCATTERING PARAMETERS
133
A.1 General Definition
At low frequencies two-port systems are described in impedance or admittance
representation. The impedance and admittance parameters relate port voltages to port currents
(Fig. A.1).
Figure A.1: Low-frequency description of two-port.
The description of the above system in impedance parameters is:
V1 = Z11I1 + Z12I2
V2 = Z21I1 + Z22I2
(A.1)
To experimentally determine the various parameters it is best to successively open-circuit
the ports. Then several terms become zero. Similarly the determination of admittance parameters
is easiest with short circuit conditions. At high frequencies it is difficult to provide adequate
shorts and opens. Thus different two-port parameters are necessary, the scattering parameters, Sparameters [28]. The port variables for S-parameter representation are defined in terms of
incident (E1i, E2i) and reflected = scattered (E1r, E2r) voltage waves
a1 =
E1i
b1 =
E1r
a2 =
E 2i
b2 =
E2r
Zo
Zo
Zo
Zo
(A.2)
Thus a1, b1, a2, b2 are normalized voltage waves. The normalization is chosen to make the square
of the magnitude of a variable equal to the power of the corresponding wave.
134
Figure A.2: High-frequency description of twoport. Z0 is the characteristic impedance of the lines
The complex S-parameters describe the relationship between the normalized voltage waves by
b1 = S11a1 + S12a2
b2 = S21b1 + S22a2
(A.3)
Determination of the parameters is based on the fact that terminating a line in its characteristic
impedance (here Z0) gives rise to no reflections. E.g. driving port 1 with port 2 terminated in Z0
yields a2 = 0 and
S11 =
b1 E1r
=
a 1 E 1i
S 21 =
b2 E 2 r
=
a 1 E 1i
(A.4)
Similarly S21 and S22 can be obtained, when driving port 2 and terminating port 1. S11 is the input,
S22 the output reflection coefficient. S21 is some kind of gain and S12 is the reverse transmission.
135
The transmission coefficients S12 and S21 are usually depicted in polar diagrams. For the
reflection parameters S11 and S22 a new type of diagram, the Smith-plot has been introduced [28].
A.2 Transformation to Y- and Z-parameters
Measured S-parameters can be transformed to Y-(admittance)-parameters and Z-(impedance)
parameters. This is important especially for de-embedding measurement results.
136
APPENDIX B
MEASUREMENTS SETUP
137
B.1 S-parameters measurements for substrate isolation structures and on chip
inductors
The measurement has been performed in setup system with two single ended ports E8364B
PNA series network analyzer in the frequency range of 0.1-40GHz, with 0 dbm port power.
Cascade ground-signal-ground (GSG) probes with 100µm pitch have been used for on wafer
probing. The measurement steps performed to measure the isolation level S12 of the different
DUT structures are as follows:
1) Calibration: use standard calibration kit to calibrate the setup up to the probe tips [59]
2) Measure 2port single ended S-parameters of DUT
3) Measure 2port single ended S-parameters for short and open calibration structures
4) Apply De-embedding technique studied in Section 3.8
Figure B.1 VNA setup to measure S-parameters
For the case of on chip inductors the following calculations are performed to come up with the
inductor differential L and differential Q.
138
1) After performing the de-embedding calculations as shown in section 3.8, the ZDUT
calculated in step 4 represents the 2 port single ended impedance parameters
ZDUT =
Z 11
Z 12
Z 21
Z 22
(B.1)
2) Differential impedance parameters Zdiff is calculated as follows
Zdiff = Z11+Z22-2Z12
(B.2)
3) Differential Q and differential L are calculated as follows
Q = imag(Zdiff)/real(Zdiff)
(B.3)
L = imag(Zdiff)/2*π*freq
(B.4)
Figure B.2 Layout of the measured differential inductors
139
Figure B.3 Layout of the measured differential inductors with all de embedding structures
B.2 Transmit buffer Pout and Pgain measurement
The measurement setup of the output power vs. input power as well as the power gain of the
transmit buffer is shown in figure B.3. the measurement steps are as follows
1) Cable power losses are calculated before connecting the DUT
2) Signal Generated power is varied and recorded
3) At each step spec. analyzer reading is recorded
140
4) Cable losses are de-embedded and DUT Pin, Pout and Pgain is recorded.
Test Configuration
Sig Gen
Pwr Sply
C2
C1
calculated loss
of cable C1 is
1.13dBm
Sig Gen Pwr
Reading dBm
Spec AN
DUT
Calculated loss of
the cable C2 is
1.13dBm
Calculated
Dut P in
dBm
Spec An PWR
reading dBm
Calculated Dut P
out dBm
Part
Gain
dBm
DUT I
mA
Figure B.4 Transmit buffer measurement setup and calibration steps
The S-parameters of the transmit buffer is measured using the 2port VNA described above.
141
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