Download POINT OF LOAD CONVERTERS - The Topologies

Presented at PCIM Conference, May 14-16, 2002, Nuremburg, Germany
POINT OF LOAD CONVERTERS - The Topologies,
Converters, and Switching Devices Required for Efficient
Conversion
Jess Brown, Vishay Siliconix, UK
e -mail: [email protected]
Abstract
Point of load (POL) or point of use (POU)
converters are emerging as the popular solution
for applications in which circuits require low
voltages of 3.3 V and below. The demand for
these types of voltage levels stems from the
requirement for lower core voltages, and it is
obvious that the current capability for these
converters will increase even if the power
capability stays the same. This has several
implications for the power-supply circuitry,
including the need to route low -voltage high
current around a printed circuit board. This leads
to relatively large voltage drops, higher power
consumption, and large PCB tracks, and could
result in poor output regulation. Furthermore,
converting the voltage from 48 V to 0.9 V
requires a very low duty cycle, which in turn
results in low efficiency. Typically, there will be
several voltage levels required across a PCB
card, and these could range from 5 V down to
0.9 V, resulting in the need for multi-output
converters or several POL converters.
Introduction
POL has many different topologies or
configurations, and as of yet there appears to be
no fixed conversion strategy for stepping down
from 48 V to values that could be as low as 0.9
V. Figure 1 shows a typical architecture for
supplying all the required voltage levels from a
single “front-end” converter. This has a typical
input voltage of 48 V, which is then stepped
down, with transformer isolation to several
outputs, to various voltage levels. These
voltages then must be distributed to the part of
the circuit that requires the power, which could
be hundreds of millimeters distant. Figure 2
shows the schematic of the architecture for a
distributed bus with a two-step conversion
process. The second-step, or POL, converter
takes the distributed bus voltage and converts it
to the required voltage level at the point at which
the circuit consumes the highest power. With this
two-step approach, the front-end converter
usually steps down to a fixed output voltage of
either 8 V or 12 V. However, a new trend has
been to convert the distributed bus down to a
value of 3.3 V. This voltage is then distributed
around the PCB, or card, to a point of load
converter, which is then used to supply the final
voltage. Another option is to use a fixed duty
cycle, typically resulting in a fixed ratio converter
of 6:1, which is reportedly optimized to give a
higher efficiency (for specified conditions) at a
fixed duty cycle. However, that topology is
beyond the scope of this paper.
48V
3V3
Primary controller,
including isolation.
2V5
1V8
0V9
Figure 1. Block diagram showing typical
architecture of a single front-end converter
supplying all the voltage levels.
48V
POL
3V3
Primary controller,
including isolation.
Fixed output or
fixed ratio
6V to 12V distributed bus
6V to 12V
distributed
bus
2V5
POL
3V3
POL
1V8
POL
0V9
POL
Figure 2. Block diagram showing typical
architecture of a point of load (POL)
distributed bus power system.
This paper explores front-end converter
topologies, along with point of load converters,
synchronous rectification, and the appropriate
controllers and devices necessary to implement
these converters. Using various semiconductor
switches specifically designed for these
topologies, efficiency measurements are made
and an objective assessment for these
topologies in several applications and power
ranges is given.
Background
Recent years have seen a move away from
centralized
ac-to-dc
power
supplies
to
decentralized (distributed) power systems that
use dc -to-dc converters near their point of use.
The major driving force has been the decrease in
1
core voltages, and it can be seen from Table 1
that this trend is set to continue over the next
decade. These low voltages at high currents are
forcing the power conversion industry to reevaluate
conventional
circuit
topologies,
component selection, and packaging concepts.
The point of load requirement has arisen from
computer hardware developments, but it is being
seen throughout the semiconductor industry
wherever DSPs are implemented, and it is
present especially in telecom base stations and
network infrastructure.
Process
technology
[µ m]
Clock
frequency
[GHz]
Power
consumption
[W]
Static current
requirement
[A]
Min. voltage
[V]
Year
‘05
‘01
‘02
‘03
‘04
‘08
‘11
‘14
0.15
0.15
0.15
0.12
0.12
0.09
0.06
0.06
1.8
2.1
2.5
2.9
3.5
7
11
15
130
140
150
160
170
171
177
186
87
93
100
133
142
190
295
310
1.51.2
1.5 1.2
1.51.2
1.2 0.9
1.20.9
0.90.6
0.60.5
0.6 0.3
Table 1. Improvement in process technology
1
and power requirements.
Before the point of load converter may be
considered, it is necessary to investigate the
converter that provides the distributed bus.
Historically, the front-end converter has always
stepped down to a fixed output to supply the
majority of voltages needed by the sub-system.
However, with a distributed architecture, the idea
is to step down to a voltage between 6 V and
12 V. This ensures that the current is large
enough to necessitate the need for large busbars
around the system. Now a new trend is being
seen in which the distributed bus voltage is to be
stepped down to 3.3 V, thus providing the 3.3-V
voltage requirement directly from the front-end
converter and allowing the low voltages of 2.5 V
and below to be provided by a POL.
The front-end controller performs several
functions, including establishing a large stepdown ratio and galvanic isolation. The entire
power throughput will have to pass through the
front- end converter and conversely through the
isolating transformer. In some circumstances this
may be an off-the-shelf voltage regulator module
(VRM), a custom module, or a discrete version
designed in-house. Regardless of the route the
manufacturer takes, the topology is usually
determined by the power requirement of the
system. The front-end converter must be highly
efficient beca use all the power for the subsystem passes through it, and any inefficiency
will be transferred through to the end output. For
example, with a POL converter of 95% and a
front- end converter of 75%, the resulting
efficiency will be 71%. Therefore, great care
must be taken to improve the front-end converter
efficiency as much as possible.
There are several available topologies that could
be considered for implementation, and Table 2
outlines
several
of
them.
Taking
into
consideration the power -requirement levels from
Table 1, it is apparent that the forward converter,
ignoring resonant topologies, is at present the
most suitable topology. However, future power
requirements may dictate the use of the halfbridge converter, which becomes more viable at
higher power levels. This paper describes briefly
both the half-bridge and forward converters,
available from Vishay Siliconix, and presents
efficiency results for the forward converter.
Topology
Flyback
Forward
Push-Pull
Half Bridge
Full Bridge
Power
Level
[W]
5 -150
10 - 250
15 -150
50 -400
200-2 k
Common Characteristics
Voltage
Output
Max.
Stress
Ripple Freq
Duty
[V]
[Hz]
Cycle
Vin+(Np / Ns )Vo u t
fs
<0.5
2×Vin
fs
<0.5
2×Vin
2×fs
<1.0
Vin
2×fs
<1.0
Vin
2×fs
<1.0
Table
2.
Characteristics
1
converters.
of
Relative
Cost
Low
Low
Med
Med
High
common
The Half-Bridge Converter 2
The half-bridge dc-to-dc converter configuration
consists of two large, equal capacitors connected
in series across the dc input, providing a
constant potential of ½ Vi n at their junction, as
shown in Figure 3. The MOSFET switches SW1
and SW2 are turned on alternatively and are
subjected to a voltage stress equal to that of the
input voltage. Because the capacitors provide a
mid-voltage point, the transformer sees a
positive and negative voltage during switching.
This results in twice the desired peak flux value
of the core because the transformer core is
operated in the first and third quadrants off the BH loop, and it experiences twice the flux
excursion of a similar forward-converter core.
Vi n
ND
2
the scope of this paper – and as such may
contribute to higher losses than normally would
be expected.
SW1
*
T1
D3A
L P E - 7 4 6 6 MBRB
-A389
1545CT
8, 7, 6
1
C
1/2Vin
GND
Synchronous
Drivers
+
Si9122
SW2
D1
15V
ZMM5245BCT
C2
1uF
25V, TAN
ND
2
Isolation
SW2
L1
LPT-4545
-A081
3
P5
2
1
C4
C3
150uF + 150uF +
15V
15V
OS-CON
OS-CON
SA
SA
68uF
160V, ELEC
R2
JP1
1
51
1
3
2
1
C12
0.1uF
2
3
R12
4
300
5
7
6
7
R10
27K
8
+Vin
Vcc
PWM/PSM D R
Vref
-Vin
NI
DMAX
FB
SYNC/Vsc
COMP
SS/EN
ICS
Ilimit
Cosc
GND
Rosc
14
R8
0
U1
Q3
Primary Switch
C11
D4
100uF +
SMBJ130
10V
R17
51
3
Results: 12-V Output
Initially, two devices were chosen for the primary
switch comparison, these being the Si9422DY
and the Si4490DY. These gave a good trade-off
between rDS(on) and gate charge (Q g), with the
Si9422DY having higher on-resistance and the
Si4490DY having slower switching times. Table
3 shows the measured efficiencies of the
converter using these two devices. It should be
noted that the transformer has not been
designed for the 12-V output – as this is beyond
C7
0.1uF
C8
100pF
P3
1
1
13
12
11
10
1
R4
100K
R3
R7
130K
R15
U2A
TPS5904A*
R6
5.90K
9
91K
1%
180pF
100
R5
0.3
1W
R18
3.0K
WSL
U2B
TPS5904A*
3
C6
0.1uF
TP1
TP
1, 2, 3
Q2
2N4403
2
C10
0.047uF
2
6
SI9118/19
R14
100
5, 6, 7, 8
4
16
15
R11
51
10T
3
C9
U2C
TPS5904A*
R9
100K
P6
1
3, 4, 5
Q1
2
2N4401
2
R13
1M
PWM
1
Interface
VOUT
+5V, 5A
C1
+
-PSM
The Forward Converter
The forward converter is very similar to the stepdown dc-to-dc converter, with the transformer
providing galvanic isolation and not being used
to store energy. For the topology investigated in
this paper, a simple reset winding is included to
reset the magnetizing current in the transformer
and prevent core saturation. The circuit used is a
self-resonant reset circuit, which resets the
magnetizing current and also recovers this
magnetizing energy by charging it back to the
input. This topology also allows for large ratio of
input-to -output voltages.
The controller used is a Vishay Siliconix
Si9118DY, and for simplicity the readily available
4
25-W demo baord is used to evaluate a range of
devices with varying parameters. Although the
target requirement would be 100 W (from Table
1), the circuit investigated gives a valid
comparison of switching devices. This demo
board is used to determine the per formance of
two distributed buses, one with an output voltage
of 12 V and anothe r with an output voltage of
3.3 V. To obtain the 12 -V output, the demo
3&4
baord
was altered slightly. This included
altering the number of turns on the transformer to
10 from 21, changing the feedback resistors, and
using higher-voltage-output capacitors. The
schematic of the circuit is shown in Figure 4. For
the 3.3 -V output, the only change to the demo
board was to the feedback resistors.
C5
1uF
9
P2
PGND
Figure 3. Schematic of the half-bridge dc-to2
dc converter.
1
*
D3B
3
MBRB1545
BYS10
1
C
7T
10
100
4
2
4
7T
D2
R1
VCC
P1
30 - 80V
1
2
SW1
Error
amplifier
1
Isolation
4
R16
24.9K
1%
AGND
1
P4
SYNC
Figure 4. Schematic showing the circuit used
3&4
to provide a 12-V, 2.5 -A output.
The results in Table 3 show that increasing the
switching frequency from 500 kHz to 1 MHz
increases the efficiency in some conditions by
6%. However, increasing the switching frequency
of the converter increases the switching losses of
the primary MOSFET. Therefore, the losses in
the transformer, in this instance, must contribute
more to the total losses of the converter than the
MOSFET, as increasing the switching frequency
reduces the energy requirement or size of the
core.
Table 3 also shows that the converter operated
with a lower input voltage of 36 V is more
efficient than when it is operated with a higher
input voltage of 48 V or 60 V. This demonstrates
that the switching losses are the dominant factor
in the primary device. Using the equations in
Table 5 and the idealized waveforms in Figure 6,
it can be shown that by decreasing the input
voltage from 60 V to 36 V, the switching losses
will increase by approximately 40%, whereas the
2
increase in conduction losses (due to the I
relationship) is approximately 70%. Therefore, if
the losses were equally distributed, then
changing the input voltage would have more of
an impact on the conduction losses. Because
this is not the case, the switching losses must be
considerably more than the conduction losses.
The efficiency results also show the trade-off
between conduction losses and switching losses
for the comparison of the two MOSFETs. At the
higher current levels, the lower rDS(on) device
becomes more efficient, especially at the lower
input voltage where the current will also be larger
(36 Vin, 2.5A, 1 MHz). However, at the slightly
lower current levels (60 Vi n, 1,5 A, 1MHz), the
75
70
67
77
75
71
78
76
75
80
75
71
82
78
75
83
81
77
81
76
72
83
79
76
78
75
72
80
77
75
80
75
70
83
79
74
84
81
77
81
76
71
83
80
76
85
80
78
Device
Vd s
[V]
Qg typ
[nC ]
200V
rds(on)
max
[Ω ]
1
Si9420DY
Si9422DY
Si4490DY
Si4488DY
Si4848DY
200V
200V
150V
150V
0.42
0.08
0.05
0.085
13
34
30
17
8.6
Switching frequency
500kHz
750kHz
1MHz
72% @
2A
76%
77%
78%
77%
76%
2A
81%
81%
81%
81%
@
77%
@ 2A
81%
80%
80%
82%
Table 4. Efficiencies at 48 -V input, 12-V
output, and load current of 2.5 A.
500kHz
750kHz
1MHz
85.0
80.0
75.0
70.0
65.0
60.0
55.0
50.0
45.0
1.7
1.9
2.1
2.3
2.5
2.7
Load current [A]
Figure 5. Efficiency for the 12 -V converter,
with 48 -V input and with the Si4848DY
MOSFET as the primary switch.
Irms =1.0A
1.20
1.00
0.80
0.60
I rms =1.2A
0.40
10
0
δ=0.29
δ=0.29
0.20
0.00
δ=0.36
δ=0.36
δ=0.48
δ=0.48
c) Secondary Voltage
50
77
71
67
I rms =0.9A
1.40
Current [A]
30
84
81
78
Three more devices were added to the
comparison, and the efficiency results are shown
in Table 4. The best efficiencies are achieved
with the 1-MHz switching frequencies and with
the Si4848DY. Again, this shows that the major
losses are associated with the transformer. To
obtain lower losses, the switching frequency
must be increased. However, it is the
combination of the fast switching times and low
rDS(on) of the Si4848DY that provides the most
efficient converter for a 48-V input and 1-MHz
switching frequency. However, at the lower
switching frequencies, the part with even-lower
rDS(on) , the Si4488DY, is more efficient.
Efficiency [%]
V rms =25V
40
1.60
20
1MHz
Load current [A]
1.5
2
2.5
Table 3. Efficiency of the Si9118DY 12-V
converter using two different MOSFETs as
the primary switch.
40.0
1.5
50
b) Primary Current
1.80
3
Vrms =22V
45
2.5
Vrms=20V
40
35
d) Secondary
Current
Irms =1.3A
2
Vrms =17V
30
25
20
Current [A]
500kHz
Load current [A]
1.5
2
2.5
2.00
V rms =32V
V rms =29V
60
Voltage [V]
DC input
[V]
9
36
4
48
2
60
2
4
36
4
48
9
60
0
Switching Frequency
750kHz
Load current [A]
1.5
2
2.5
a) Primary Voltage
70
Voltage [V]
higher rDS(on) device is more efficient. This is due
to the fact that reducing the rDS(on) at higher load
currents counteracts the penalty of increased
switching losses associated with higher Qg .
I rms =1.5A
1.5
I rms =1.7A
1
15
10
5
0
δ =0.29
δ=0.36
δ =0.48
0.5
δ=0.29
0
δ=0.36
δ=0.48
Figure 6. Idealized current and voltage
waveforms for 12-V and 2.5-A output.
Key δ=0.29 Vin 60V; δ=0.36 Vin 48V; δ=0.48 Vin 32V
Loss equations
Primary
Switch
D1
D2
D1+ D2
Pcon = Rds(on) I 2δ
1
Psw = VI(t f + t r ) f s
2
Pgate = QgVg f sw
Pcon = Vsat I (δ )
Pcon = V sat I (1 − δ )
I

Prr = Vt rr  rr + I  f s
 2

Table 5. Generic loss equations for the active
devices in a forward converter.
Results: 3.3-V Output
As with the example of the 12-V converter, two
devices initially were chosen for the primary
switch comparison. Table 6 shows the measured
efficiencies of the converter using the Si9422DY
and the Si4490DY.
The highest efficiency occurs at a load current of
between 2 A and 3 A, a range that ties in with the
efficiencies of the 12-V output converter and the
4
demo baord , which also had their highest
efficiencies at 2.5 A. The efficiency appears to be
dependent on current rather than power
throughput, which may be due to the losses in
the secondary-side Schottky diodes.
With the 3.3-V converter, the efficiency does not
always improve with a lower input voltage. This
means that the trade-off between switching
losses and conduction losses is not as definitive
as it was in the 12-V output case. Figure 8 shows
the current and voltage waveforms for the 3.3-V
converter, and it is seen that even though the
rms values of the voltage will be lower, the peak
values of the voltage will be the same for the 3.3V output converter as for the 12-V converter. The
primary current peak will be higher for the 3.3-V
converter with the same power throughput,
resulting in higher switching losses for the same
power. The conduction losses will also be higher
because the rms current is higher for the same
output power. Therefore, the losses for the 3.3-V
converter will be greater than those for the 12-V
converter for a given power output. This is not
necessarily the case in this paper, due to the
dominance of the modified transformer in the
12-V converter.
4490DY
[500kHz]
4490DY
[750kHz]
4490DY
[1MHz]
78
77
75
76
75
73
72
71
69
75
71
69
76
68
65
75
61
80
82
81
81
80
80
79
78
77
78
79
78
79
76
74
74
72
Efficiency [%] @ Load current [A]
3
4
5
6
7
81
81
82
79
82
81
81
80
79
80
79
80
80
79
77
76
75
80
80
80
79
79
81
78
80
80
80
79
78
80
80
78
76
77
79
80
79
78
79
78
77
77
77
80
79
79
79
78
77
76
77
78
79
79
77
78
78
76
77
76
79
79
78
78
77
77
76
75
77
78
77
76
77
77
75
76
75
78
78
78
77
77
76
75
75
Efficiency [%]
65.0
60.0
55.0
50.0
45.0
40.0
1
2
75
76
76
74
75
75
74
74
74
77
77
76
76
76
75
73
74
Again, as with the 12-V converter test, three
more devices were added for comparison (Table
7). In these tests the most efficient circuit has a
750-kHz switching frequency, which means that
the transformer losses are not dominant, as they
were with the 12-V output converter. In the 3.3-V
converter, it is obvious that the switching losses
of the primary device dominate the losses
because the Si9422DY, with the lowest Qg, is the
most efficient device. However, at the higher
loads (8 A, 750 kHz), it is the combination of the
low switching and rDS(on) of the Si4848DY that
provides the most efficient converter with an
efficiency measurement of 79%.
Switching frequency [kHz]
Si9420
DY
Si9422
DY
Si4490
DY
Si4488
DY
Si4848
DY
rds(on)
max
[Ω ]
1
Qg
typ
[nC ]
8.6
200V
0.42
13
200V
0.08
34
150V
0.05
30
150V
0.085
17
Load
[A]
3
8
3
8
3
8
3
8
3
8
500
81
76
79
77
79
77
80
73
750
80
73 (@7)
82
75
79
76
77
76
79
77
7
8
Figure 7. Efficiency for the 3.3-V converter
a) Primary Voltage
3.00
70
V rms=26V
60
Vrms=20V
40
1000
78
67(@7)
80
74
76
73
76
74
77
75
Table 7. Efficiencies using five different
primary switches with a 48 -V input and 3.3-V
output.
b) Primary Current
2.50
Vrms=23V
50
30
2.00
Irms=1.1A
Irms=1.2A
1.50
Irms=1.4A
1.00
20
0.50
10
0
δ=0.18
0.00
δ =0.18
δ=0.23
δ=0.23
δ=0.31
δ=0.31
d) Secondary Current
c) Secondary Voltage
9
25
Vrms=8.2V
8
20
7
V rms=7.3V
V rms =6.3V
15
10
Irms =3.4A
6
Irms =3.8A
5
4
Irms=4.4A
3
2
5
0
δ=0.18
δ=0.23
δ=0.31
Vds
[V]
200V
6
Load Current [A]
8
Table 6. Efficiency of the Si9118DY 3.3-V
converter using two different MOSFETs as
the primary switch.
Device
3
Current [A]
2
5
70.0
Current [A]
9422DY
[1MHz]
1
4
1MHz
75.0
Voltage [V]
9422DY
[750kHz]
Vin
[V]
36
48
60
36
48
60
36
48
60
36
48
60
36
48
60
36
48
60
750kHz
80.0
Voltage [V]
Device
[Freq]
9422DY
[500kHz]
500kHz
85.0
1
0
δ=0.18
δ=0.23
δ =0.31
Figure 8. Idealized current and voltage
waveforms for 3.3 -V and 8 -A output.
Key δ=0.18 Vin 60V; δ=0.23 Vin 48V; δ=0.31 Vin 32V
Secondary Synchronous Rectification
One of the factors that affects the efficiency of
the 3.3-V converter at the higher load currents
necessary to obtain the same power output is the
IV losses in the rectifier diodes (D3A and D3B in
Figure 4). Therefore, these diodes were can be
replaced with MOSFETS to reduce conduction
losses.
Self-driven secondary synchronous rectification
is relatively simple to achieve with forward
converters and is shown in Figure 9. However,
care must be taken with the voltage levels that
appear on the secondary-side transformer. For
example, in considering the ideal voltage across
the secondary transformer (Figure 8) for the 12-V
converter, the minimum voltage is 25 V.
However, with voltage overshoots this voltage
often exceeds 30 V. Therefore, synchronous
rectification was not considered for the 12-V
converter due to the maximum gate-source
voltages, which are typically 20 V. Furthermore,
because the current levels in the 12-V converter
are considerably lower than in the 3.3-V
converter,
the
benefits
of
introducing
synchronous rectification are not as great.
With an input voltage of 36 V, the 3.3-V
converter secondary-side voltage was below
20 V (the maximum gate source voltage allowed
for these devices). Therefore, the Si4888DY,
which offers a good combination of Q g and rDS(on) ,
was used as the MOSFET for synchronous
rectification. For an input of 48-V, the secondaryside voltage reached values higher than 20 V, so
a capacitor was used in series with the gate of
the MOSFET. This reduces the gate source
voltage appearing on the MOSFET, but it has the
disadvantage of slowing the device and
increasing the gate losses (Figure 10).
Another option is to use a Schottky diode in
parallel with the synchronous MOSFET to
improve the reverse recovery characteristics. An
advantage of this method is that the Schottky
can have a greatly reduced current capability, as
it will only be conducting for a small amount of
the time.
Reset
Circuit
Vin
Optional
Vout
Si9118DY
Controller
Si488DY
Primary
Switch
OptoIsolation
Figure 9. Schematic of the self-driven
synchronous rectification.
36V with schottky 500kHz
48V no synch 750kHz
36V without schottky 500kHz
36V no synch 500kHz
48V with gate cap 750kHz
90.0
Efficiency [%]
85.0
80.0
75.0
70.0
65.0
60.0
0
1
2
3
4
5
6
7
8
be synchronous buck or synchronous boost to
provide the greatest efficiency. Finally, the
controllers can also be simple to allow for the
smallest size.
For the MOSFET devices used for these
synchronous converters, there are also desirable
characteristics, such as shoot-through protection
to prevent spurious turn -on of the low -side
switch. This has come about due to the need for
increased switching times and hence smaller
dead-times. Also, for the synchronous MOSFET
(lower -side switch in buck), the rDS(on)
characteristics are more important, and with
higher power levels, the packages are becoming
more critical in increasing the power density.
Conclusion
These results have shown that it is very difficult
to predict the performance of a MOSFET in a
switching converter. In some circumstances the
major factor contributing to losses may be the
rDS(on) , and for another load point, the switching
transients will be more important. Therefore, in
some circumstances it may be more desirable to
fix the parameters of the converter by fixing the
output current rather than the output voltage.
With the need to bus an intermediate voltage
around the board, the voltage regulation can be
accounted for with the point of load converter. In
this case, the distributed intermediate voltage
does not necessarily need to be a fixed voltage.
Another issue is the requirement for the
distributed bus voltage level. Lower voltage
outputs mean higher load currents and more
losses for the same power levels, but a 3.3-V
distributed bus does have the advantage of
having the 3.3 -V output available when required.
The efficiency can be improved dramatically with
synchronous rectification, which may not be the
case with the higher-output-voltage converter.
Therefore, care must be taken in choosing the
correct topology and MOSFET for a given
application, and in some circumstances the
devices and circuits should be chosen via
practical testing.
9
Load Current [A]
Figure 10. Synchronous rectification with 3.3V output.
The Point of Load Converter
Although not considered in detail in this paper,
the actual point of load converter has several
important characteristics. First, it does not need
to be isolated because the fr ont-end converter
has achieved this. Second, depending on the
required voltage levels, the POL converters can
References
1 Semiconductor Industry Association (SIA),
www.edmag.co.uk/artesyn
2 ‘High efficiency half-bridge DC-to-DC converter with
secondary synchronous rectification’, Brown, Davies,
Williams, Bernacchi, PCIM 2001, June 19-21, Nurenberg,
Germany
3 ‘Designing a high-frequency, self-resonant reset forward
DC/DC for telecom using Si9118/9 PWM/PSM controller’,
AN724, http://www.vishay.com/docs/70824/70824.pdf .
4 ‘Si9118/9 demonstration board’,
http://www.vishay.com/docs/70875/70875.pdf.