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JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 22, NO. 9,
SEPTEMBER 2004
Min-Hyeong Kim
High-Speed Circuits and Systems Laboratory
E.E. Engineering at YONSEI UNIVERITY
2011. 6. 2.
[ Contents ]
1. Abstract
2. Structure
3. Optical Devices
4. Electronic Devices
5. Measurement Results
6. Conclusion
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1. Abstract
A parallel-optical interconnect with 12 channels operating at 8.5 Gb/s
giving an aggregate data rate of 102 Gb/s is demonstrated.
A BER<10^-13 was measured on a single channel after transmission
through 100m of multimode fiber at a data rate of 8.5 Gb/s with all
12 channels operating simultaneously.
How to demonstrate this structure?
[ Optoelectronics(OEs) + Integrated Circuit(IC) of TXRX ]
 POSH(Parallel Optics for Super-Highways) package design
 Flip-Chip Bonding, Link Budget.
 990nm Bottom-Emitting VCSELs / PIN PhotoDetector
with Laser Driver / differential TIA
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2. Structure
 POSH(Parallel Optics for Super-Highways) package design
[ CME ] (Chip-Mounted Enclosure)
: OE + IC block
by flip-chip bonding and Wall.
[ BGA interface ] (ball-grid-array)
: Provides an electrical turn
while maintaining a low-loss,
high-bandwidth 50Ω signal
transmission path.
[ AlN stiffener ]
: For a high thermal conductivity
path to the heat sink isolating
the CME block electrically.
RX module illustration
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2. Structure
 Flip-Chip Bonding
 The loop inductance and capacitance are reduced by this bonding.
 This will result in performance advantages including larger bandwidth,
less overshoot and ringing, and lower EMI.
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2.
3.
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4.
5.
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Integrated circuits which pads are
metalized are created on the wafer.
Solder dots are deposited on each of
the pads.
Chips are flipped and positioned so
that the solder balls are facing the
connectors on the external circuitry.
Solder balls are then remelted.
(typically using hot air reflow)
Mounted chip is “underfilled” using an
electrically-insulating adhesive.
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2. Structure
 Link Budget
Link Budget?
A link budget is the accounting of all of the gains and losses from the transmitter, through the
medium (free space, cable, waveguide, fiber, etc.) to the receiver in a telecommunication system.
Ex) Received Power (dBm) = Transmitted Power (dBm) + Gains (dB) − Losses (dB)
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3. Optical Devices
 [LASER] 990nm Bottom-Emitting VCSELs
850nm → 990nm :
• Compatible with flip-chip bonding
• 3.4dB link budget advantage
1)
2)
3)
4)
5)
6)
7)
lower operating voltage;
higher differential gain;
lower threshold current;
higher speed;
improved reliability;
lower photon energy;
lower thermal resistance.
 P cladding : 40 pairs of carbon-doped ptype top AlGaAs DBRs
 Active : one-wave cavity with multiple
InGaAs quantum wells
 N cladding : 27 pairs of Si-doped n-type
bottom AlGaAs DBRs
 Lapped, Polished, and antireflection (AR)
coated.
** DBRs : distributed-Bragg reflectors for VCSELs mirror.
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3. Optical Devices
 [LASER] 990nm Bottom-Emitting VCSELs
 Test input :
NRZ PRBS 2^7-1
 Extinction Ratio(ER) :
6dB




The average threshold current : 434uA
The average threshold voltage : 1.34V
Estimated bond-pad capacitance to be only 35 fF.
The device was biased at an average current of 3 mA and 1.5 mW of
optical output power.
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3. Optical Devices
 [PD] PIN Photo Detector
P : 0.2um n- InGaAs
I : 1.8um InGaAs as the absorber layer
N : 1um n+ Si-doped InP
BW 
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2 RDCpd
 2x12 arrays for the differential input of the
RX IC front end
 Approximately 180fF capacitance to open
10Gb/s eye diagram.
 For a conventional 50Ω RX interface, the RX
BW would be about 18GHz. It is enough.
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3. Optical Devices
 MicroOptics
[ TX optical system illustration ]
50MMF
 A diffractive vortex element is used to minimize back reflection into
the VCSEL ( 0.01%) and to create a restricted-mode launch into the
MMF, increasing the bandwidth–distance of the MMF.
 A high-efficiency refractive surface is designed to achieve a throughput
efficiency of 75%.
 The RX geometry is similar to the TX geometry, with the diffractive
element closest to the fiber replaced with an another refractive lens.
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4. Electronic Devices
 Transmitter & Receiver
 Both TX and RX circuits have been designed for
a conventional 50Ω electrical interface.
 The TX driver and RX input power supplies are
separated for low crosstalk penalties.
 The transition frequency of 45GHz
[ TX ]
 the output connected directly to the n-side of the VCSEL.
 The 12-channel TX IC dissipates 1.5–2 W.
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4. Electronic Devices
 Transmitter & Receiver
2qic 2
4kT
2
2 2
i  2qib f 
(
C

C
)

f

4
kTR

C

f

f
pd

b
pd
g m2
Rf
2
eq
[ RX ]
 Minimizing jitter requires isolating the channels as well as possible,
managing ground planes, and maximizing bandwidth.
 The recommended transition frequency is > 75GHz, where
performance and power dissipation would both be improved.
 A dummy photodiode is connected to the dark side of the input
amplifier so that impedances are balanced.
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5. Measurement Results
1) POSH TX module




Test input : NRZ PRBS 2^7-1
Extinction Ratio : 6.3dB
Average Power : -3.10dBm ~ -4.67dBm
Rise/Fall time : 36/84ps , respectively
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5. Measurement Results
2) POSH RX module
 Test input : NRZ PRBS 2^7-1
 Extinction Ratio : 6dB
 Channel : through 100m of standard 50-um-core MMF ribbon
[ POSH RX eye diagrams at 8.5 Gb/s/ch ]
Eye opening Every Channel.
[ One sample of RX eye diagrams
at 10Gb/s/ch ]
Not yet every channel……
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5. Measurement Results
2) POSH RX module
[ Single channel BER comparison
between 8.5Gb/s and 10Gb/s ]
[ BER comparison between
single and all channel operations ]
at 8.5Gb/s
at 8.5Gb/s
For 10^-12dB BER,
PD sensitivities were
 -15.3dBm at 8.5Gb/s
 -12.4dBm at 10Gb/s
The RX channel crosstalk penalty
is about 1.3dBm
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6. Conclusion
I.
To improve more (exactly say, to get an all eye-opening at
10Gb/s), Design a new version of the RX IC in a Si-Ge BiCMOS
process with an f_t of 75GHz.
II.
Demonstrate 12-channel TX parallel-optic modules operating at
10 Gb/s/ch and RX parallel-optic modules operating at 8.5–10
Gb/s/ch.
III. At 8.5Gb/s, BER<10^-13 was measured on a single channel
with all 12 channels operating simultaneously.\
IV. So, a parallel-optical interconnect with an aggregate data rate
of 102 Gb/s (8.5*12) was demonstrated.
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