Download Imaging Devices Using the Charge-Coupled Concept

PROCEEDINGS
IEEE, OF THE
38
VOL. 63, NO. 1, JANUARY 1975
Imaging Devices Using the Charge-Coupled Concept
Invited Paper
A b c t - A . unified treatment of the basic electrostatic md dynamic
Of dlbuge-coupled d
h (CCD's) b 8 d 011 8PplOXhn8k 8Mlylical analysin is p m n t e d . aoclriqg methods md tndeoffs are dib
cussed Driver power disaiprtion md on-chip power di88ip8tion are
mnlyzed. Roperties of noiae w
c
e
s due to charge input md transfer
are aunmrriaed. Low-nobe methods of si@
extractionare discussed
in detail The state of the art for linear d area a m y 8 is presented.
Ttrdeoffs in 8re&urry performmce from 4 systems point of view and
pexformmce p r e d i c t i o ~are presented in detail, Time d&y urd inte
gration (TDI) md the chargeinjection device (CID) are discussed.
FinrIly,the uses of the chylpcoupled concept in infraredimaging
Pediacussed
ONE CEU
CONDUCTING
ELE$TRODES
OR BIT
O T
TWT
ODE
INP
sw
(a)
+
t
P+
,mk
(b)
I. INTRODUCTION
HARGE COUPLING is a simple but extremely powerful
concept. Basically, a chargecoupled device(CCD) is a
metal-oxide-semiconductor (MOS) structure,as shown
in Fig. 1, which can collect and store minority carrier charge
packets in localized potential wells at theSi-Si02 interface [ 11 .
The CCD can transfer charge packets indiscrete-timeincrements via the controlled movement of-potential wells. The
charge packets can then be detected at.the outputvia capacitive
coupling. Thus a CCD acts as an analog shift register composed
of three sections. 1) The inputsection which contains a diffusion, which is the source of minority carriers, and whose potential can be controlled, and an input gate whichcanbe
turned on and off tocontrolthe
flow of charge fromthe
source diffusion into the first potential well. 2) The transfer
section, containing a series of electrodes which controlthe
potential at the Si-Si02 interface. When the voltages on the
electrodes are properly manipulated, thepotential wells are
moved toward theoutput and the charge packets follow.
3) The output section is a reverse-biased p-n junction capacitance whosevoltageischangedwhen
a charge packet is
transferred into it. The diode is then reset via a reset switch to
prepare for the next packet to be transferred into it. Thisnode
is typically connected to anMOS amplifier.
Charge can be entered into the device in a series manner via
the input diffusion or via the absorption of photons near the
potential wells. Suppose that a charge configuration has been
entered into the device, by one of these methods, as shown in
Fig. l(c). In a device having a planar oxide and uniform substrate doping, three phases are required for unidirectional
charge transfer, i.e., if a barrier is maintained behind the
charge packet while a deeper well is formed in front of the
packet, then charge will flow into the deeper well. The clocking diagram is shown in Fig. l(d). At t = tl , charge resides in
the wells under the @1 electrodes. At t = t 2 , thepotentialon
42 is made positive forming
under the @2 electrodes.
Charge will then flow from the @1 wells into the,@2wells. At
Manuscript received July 16, 1974; revised August 19, 1974.
The author is with
the
u. s.
Research Laboratory,
D.C. 2 0 3 1 5 .
-
1'1,
t'h
t = t3
eee
.
eee
-$A+*
(C)
tat4
+I
11 $'st4
(dl
Fig. 1. Three-phase CCD.(a)Cross-sectional
view showing input section, transfer section, and output section. A primitive electrode structurehaving unprotected gaps is shown for simplicity. (b) Surfacepotential profile showingpotential wells under the
electrodes.
(c) Surface-potential profdes showing progression o f chargetransfer
during one clock period. (d) Clocking waveforms used to drive the
CCD during transfer.
@,
t = t g , the potential on the 41 electrodes is reduced to a low
value and the remaining charge in the @1 wells will be pushed
into the $2 wells. This sequence repeats with the result that
the charge configuration moves from one cell to the nextevery
clock period. Thus the clock rate is equal to the data rate.
Since the charge packets follow the potential wellswhich
are controlled by external voltages, transfer can be achieved in
two dimensions. Information canbe entered inanalog or
digital form. The device can have multiple inputs and multiple
nondestructive outputs via floating gates. The CCD is inherently a low-power device requiring low voltagesfor its operation, and has a highpacking density. As a result, there are
many applications for CCD's in imaging,analog and digital
processing7 and memory.
An attempt is made in this paper t o present a unified treatment of the fundamental design parameters of the device, discuss the technological and design tradeoffs, and consider the
state of the art. Section I1 discusses the electrostatic design
considerations; Section 111, the dynamic design considerations;
Sections IV and
input
V, the
and output design considerations;
BARBE: CHARGECOUPLED IMAGING DEVICES
39
7
Section VI, noise; Section VII, the design and performance of
linear imaging arrays; Section VIII, the tradeoffs in area-array
design; Section IX, radiation effects on CCD’s; and Section X,
the uses of the CCD concept in IR imaging.
vFB
11. ELECTROSTATICS
A. Surface Channel
When a voltage is applied to the conducting electrode of an
MOS capacitor with respect to the substrate, the energy bands
in the semiconductor bend. If the applied field is in the direction to repelmajority camer fromthesurface of the semiconductor, i.e., fromthesemiconductor-insulatorinterface,
the bands in p-type
silicon will bend as shown in Fig. 2(a).
The effective voltage across the capacitor, VG - VFE, will be
divided between the semiconductor, as indicated by the band
bending in the semiconductor, and the oxide, as indicated by
the “tilt” of the energy bands in the oxide. The electron potential at thesemiconductor-insulatorinterfaceunder
the
electrode is lower than that in the bulk of the semiconductor
by amount t$%; thus a “potential well” of depth $h is formed
at the semiconductor-insulator interface under the electrode.
If charge is collected in the potentialwell as a result of photon
absorption, injection from an input diffusion, or thermalgeneration,thepotential
across the insulator and the semiconductor willbe redistributed as shown in Fig. 2(b). Thus the
potential well has been partially filled to 4,. The equation relatihgthe surface potential or potential-welldepth tothe
factors affecting itis discussed in the following paragraphs.
The basic electrostatic design equation for a surface-channel
CCD relating surface potential & to doping densityNA , oxide
thickness d , and gate voltage VG is obtained by solving
Kirchhoff s voltage equation for an MOS capacitor:
VG - VFE = 6, + Vox
WELL
EMPTY
-
MSTANCE
(b)
Energy-band diagram for a surface-c&nnel MOS capacitor.
(a) Band-bendingat deepdepletion and the empty potential-well
representation. (b) Band-bending with mobile charge at the Sisu),
interface and the partidy fUkd potentid-wnrepresentation.
Fa.2.
0
+”
DIFFUSED OR
IMPLANTED
BARRIER
(1)
where VFB is the flatband voltage and Vox is the voltage drop
across the oxide. But
?
+”
1
Vox = - [mobile charge density + fixed charge density]
cox
NA
eN
+NAeW
STEPPED
OXIDE
BARRIER
I
I
Lox
where Cox = e o x / d , e = 1.6 X lO-I9C, and N is the number
of mobile electrons per unitarea.
Using the depletion approximation, the width of the depletion region, W ,is
%
I
I
f
-t
CONDUCTOR
INSULATOR
0 SEMICONDUCTOR
(b)
Method8 of forming fued potential burisrr. (a) Surfacepotential barrier due to nonunifarm doping. (b) Surfacbpotmtial
barrier due to nonuniform oxide thicknmerr.
Fii.3.
where E, is the dielectric constantof the semiconductor.
Combining (11, (2), and (3) gives
VG
-
vFE
eN
1
-= 4, + -( 2 e ~ AEA^)''^.
cox
Solving (4) for #, gives
cox
(4)
Equation (5) shows how barriers can be controlled by proper
choice of gate voltage, dopingdensity, and oxide thickness
[ 2 ] . For example, (5) shows that
decreases when NA is increased and when Cox is decreased. This is illustrated in Fig. 3,
which shows qualitatively the two methods of channel confinement (channel stops)-high doping or thick oxide. These
two methods are also used to build in charge flow directionally
along the channel intwo-phase CCD’s.
Equation (5) can also be used to calculate the maximum
electron density that can be stored on an MOS capacitor, i.e.,
PROCEEDINGS OF THEIEEE, JANUARY 1975
40
I P-TYPE
Si
POLYSILICON
THICK
OXIDE
THIN
OXIDE
(b)
Fig. 5. Implanted-barrier two-phase CCD. (a) Cross-sectional view of
the structure. (b) Surface-potential profde showing built-in potential
barriers due to nonuniform doping.
+2-\+/7I
I
4
I
tI
I
I
'2
(4
Stepped-oxide two-phaseCCD. (a) Crostisectional view of the
structure.(b)Surface-potential
profiles showing charge
transfer.
(c) Clocking waveformsused t o drive the CCD during transfer.
Fig.4.
7
N = Nmaxwhen
= 2 4 =~ 2kTfe In ( N ~ l n i )and
, ni is the intrinsic density of carriers. Solving (5) for Nmax gives
-
where
- 1 r n
ND
NA
W
Fig. 6.
Typically, VFB, 2&, and VB are much smaller than VG ;
therefore,
Thus f o r d = 1000 A and VG = 10 V,
N~~
2 X 1 0 ' ~electron/cm2.
This is the maximum electron density in an inversion layer
with VG = 10 V. In CCD's, the saturation level is usually less
Enetgy-band diagram for a buried-cbnnel MOS capacitor showing the potential minimumin the semiconductor.
An alternativemethodfor
achievingtwo-phase operation,
the implanted barrier technique, is *own in Fig. 5. Basically,
nonuniformdoping is used to achieve therequiredbarrier.
This technique uses planar oxides and only two buses are required. Barriers of about 4 V are typical for both
of these
techniques. The full-well capacity is
Nfull = cox VbarrierAstoragele
thanthis value because thefull well is determined by the
height of a barrier formed by adifferenceinelectrode po- where Astorage is the area of the electrode underwhich charge
is stored.For two-phase stepped-oxide or implanted-barrier
tentials, an implanted barrier, or oxide step.
Fig. 4 illustrates the stepped-oxide method for
building in designs, Astorage 2: 1/4 Acell. Thus the number of electrons
potential barriers that allow the device to be clocked with two at saturation is approximately2 X 1o6 electron/ceU.
phases. In a typical device, the thin oxide is 1000 A. Doped
B. Buried Channel
and patterned polysilicon provides the set of electrodes on the
Theprofile of potential versus distance into silicon for a
thin oxide. Subsequent oxidation provides the thick (2400 A)
oxide onto which aluminum electrodes are formed. This oxi- buriedchannel CCD element is shown inFig. 6. As for the
dation also isolates the polysilicon and aluminum electrodes surface-channel CCD, the basic electrostatic design equation
from each other. Thus the oxide steps
(1400 A) formed in relating the minimum electron potential in the channel, 4min;
this way provide barriers that prevent charge from spilling to the doping density of the substrate, NA ; doping density of
backward. Theelectrodesareconnectedas
shown sche- the channel, N,; oxide thickness d ; thickness of the donor
matically in Fig. *a) to form a two-phase CCD. The electrode layer, I ; and gate voltage VG is calculatedfrom Kirchhoff's
interconnectionsforthisstepped-oxide
device are made off equation [ 31 :
chip, thus four onchip buses are required. Surface-potential
4s + VG - VFB + vox = '$/ i4~(8)
profiles illustrating charge transfer are shown in Fig. 4(b), and
the clocking waveforms are shown in Fig. 4(c).
Since Vox = l/Cox X (mobile charge density + futed charge
-
41
BARBE: CHARGECOUPLED IMAGINGDEVICES
density), it follows that
20
I
I
'
I
I
O
N& = 2 x 10'' cm-'
N o = 3 a Io'' cm-3
eND(t - A t - N / N D )
vox =
1
eoxld
16-
d
t
-
Using the depletion approximation gives
VI
I
,
0.2
=0.18MlcmN
=0.3 MICRON
~ 9 . 5 6VOLTS
0.4
0.6
12-
0.8
-I
1.0
0
f
s
8
6
4
and
0
-6
Combining these six equations gives
-4
-2
0
2
4
V,
6
8
- VFB ( VOLTS)
Fa. 7.
IO
12
14
16
18
Minimum potential versus effective gate voltage, with density
of carriers in the potential well, N,as a parameter. Curves are calculated from (16).
the electrical field due to a nonuniform distribution of electrons under two electrodes at the same potential, or by a field
due to thepotentialdifferencebetweenelectrodes.
These
processes are called self-induced drift and fringefielddrift,
respectively. The detailed solution of these equations for real
device structuresrequires numerical calculations [4]. However, insight can be gained from approximate analytical solutions [5I . Theapproximateequationforthefraction
of
charge remaining in a given position after transfer time t due
to self-induced drift is
where
and VI is the voltage that must be applied across the p n junction to deplete the channel. The quadratic formula gives the
solution:
(17)
NO
with
tSI =
x2Ceff
-
(18)
WneNo
where
charge remaining aftertime t ,
center-to-center-electrodespacing,
pn electron
mobility,
No number of electrons per unit area in the packet to be
transferred at t = 0,
Ceff effective storage capacitance per unit area.
N,
L
. (L+ L - ""))]112}2.
€ox
2%
ES
Fig. 7 shows @min versus VG - VFB, with N/NDt as a parameterfora
shallow buriedchannel device. Fora voltage
(VG - VFB) swing from - 2 V to +5 V, a full well corresponds
to N/NDt % 0.75, which gives N 6.75 X 10'' cm-2. Assuming that the area of the well is lod cm', the number of electrons in the full well is approximately 6.75 X 10'.
111. DYNAMICS
The approximate equation for the fractionof charge remaining
in a given positionaftertransfertime
t due to fringe-field
drift is
N,o-- exp (-t/TFF)
NO
with
A . Free-ChargeTransfer
The dynamics ofcharge transfer are governed by the continuity equation and Poisson's equation with the appropriate
boundary conditions. In general, both drift and diffusion contribute to charge transfer; however, in welldesigned devices,
drift processes are dominant. Drift current is caused either by
(19)
TFF
L
<CcnEmin
and
2 AV m,
Ed,.,=--3 L' Ceft
(20)
IEEE,PROCEEDINGS OF THE
42
JANUARY 1975
where A V is the voltage differencebetweentheelectrode
under which charge was stored and the receiving electrode, and
es is the dielectric constantof the semiconductor.
From ( 5 ) , it follows that for a surface-channeldevice,
Ceff = cox= d
and from (la), it follows that for a shallow buried-channel
device,
€0,
4
f
4
BURIED
CHANNEL
-40
Self-induced drift is the dominant mechanism in the initial
part of the transfer process and fringefield drift
is dominant in
the final part of the transfer process. Therefore, for shallow
buried-channel structures, it is appropriate to use N = NO
in (18):
andN=Oin(21):
teff=
( d
.~~
-+-
\€ox
r\-’
Ea/
.
According to (la), (20), and (2 l), it follows that the transfer
time for a shallow buried-channel device (0.5 p m ) is not significantly smaller than that of a surfacechannel device with
relatively thick oxide ( d N 0.2 pm). However, deep buriedchannel devices ( 5 pm) have significantly shorter transfer times
because Ceff is much smaller and, as a result,the fringe field is
larger. The physical reason for the fringe fields being larger in
a deep buried-channel device can be seen from Fig. 8. Because
the interface is close to the electrodes, the surface potential
under a given electrode is determined almost totally by the
potential of that electrode, except near the edges. Because the
minimum potentialinadeep.
buried-channel device is relatively far from the plane of the electrodes, the potential under
a given electrode is influenced not only by the potential of
that electrode but also by the potential.of adjacent electrodes.
Therefore, in a deep buried-channel device, the potential proFie has more slope under the transferring electrode, i.e., the
fringe field is larger. Deep buried-channel deviceshave been
operated at data rates up to 130 MHz [61.
B. Interface-State Trapping in Surface-Channel Devices
Another mechanism thatlimits the efficiency of charge
transfer is trapping at the semiconductor-insulator interface.
The distribution of interface states in the silicon energy gap is
shown in Fig. 9 [71. The emission time of interface states is
proportional to exp [(E, - E,)/kT]. The particular states that
contribute to charge-transfer inefficiency depend on the clock
frequency. States near the conduction-band edge emit trapped
electrons quickly after the charge-transfer process is initiated
and theseelectrons rejoin the main packet;therefore,traps
with emission times << l/fcdonotcontribute
tocharge
transfer inefficiency. States having emission times >> l/fc resultin an almost permanenttrappingandthusdonotcontribute to charge-transfer inefficiency on a steady-state basis.
Therefore, it is states havingemission times l/f, which trap
charge fromapacket and emit charge into trailingpackets,
thus contributing to charge-transfer inefficiency. The transfer
inefficiency due to interface-state trapping can be minimized
t I
ii
by f i g each well to a fixed level, typically 10-20 percent of
saturation [ 81. This effectively sets a bias charge level such
thata ZERO inthe digital sense is not an empty well but
rather a well that is 10-20 percent filled; thus the term “fat
zero” is used for this bias charge. The effect of the fat zero is
to keep the interface states under the gates filled so they do
nottrap signal charge, and each charge packet will receive
about the same number of electrons from preceding packets as
it loses to trailing packets. The transfer inefficiency due
to
interface-state trappingcan be written as [91
where
ns,o
ns
number of fat-zero electrons per unit area,
number of signal electronsperunitarea,
nFIS fast interface-state density in cm-’ (eV)-’,
f,
clock frequency,
kl
aconstantparameterthatdepends
onthe
cross section (kl
lo-’ cm2/s).
trapping
Interface states atthe edges of the electrodes arenot “covered”
by the fat-zero charge because the edges of the potential wells
are not vertical [ 101. In these regions, the trapping is not reduced by the fat zero. This is called the “edge effect.’’
43
BARBE:CHARGE-COUPLEDIMAGINGDEVICES
(a)
(b)
Fig. 10. Oscilloscope traces showing output voltage versus time. (a) Output voltage when a cell w a s illuminated near the
output diode. (b) Output voltage when a cell was illuminated far from the output diode. The number of transfers between
the two illuminated cells is 126.
m
A typical curve of E versus clock frequency has two sections.
1) At low frequencies, E is limited by trapping and is nearly
independent of clock frequency. 2) At high frequencies, E is
limited by
free-charge
transfer mechanisms and increases
sharply with increasing f,.
0
I
2
3
4
5
6
N=O
C. Transfer Inefficiency Measurement
Fig. 10 shows an example of transfer inefficiency measurement for a shift register. The shift register is clocked to provide an integration period with subsequent readout via shiftregister transfer. Charge is entered into a cell by means of a
small light spot. The trace on theleft side of Fig. 10 shows the
output voltage VN when the light spot is near the output end,
and the trace on the right side shows the output voltage VF
when the light spot is far from the output end. If these two
cellsare n transfers apart,thenthe
transfer inefficiency is
N=I
I
l
l
a
D ( ~ , N ) ; I;
N!(
Q
lN-i)!l!
~ - ~.N-i
) l
Fig. 11. Schematic diagram of dispersion in a single-charge packet
(impulse) as it is transferred through a CCD.
the charge packet after N cell transfers is given by 1 - D ( N , N ) :
For the example shown, VN = 465 mV, ’V = 435 mV, and
n = 126; therefore,E 2: 5 * lo4.
D. Effect ofTransfer Inefficiency on an Impulse
In the discussion of the effects of transfer inefficiency on
waveforms, the following definitions will be used:
E fractional loss per elemental transfer,
n number of elemental transfers,
P number of clocking phases,
N number of cell or bit transfers,
a fractional loss incurred by a charge packet in moving
from one cell to the next.
Then it follows that n = PN and a = P E .
If a single Packet of charge containing charge Q Placed into
a CCDwell ( i = 0), then after N cell transfers, the distribution
ofchargeinthecellsi=O, 1,2;*.isgivenby[llI
loss= 1 - (1 - a>N-Na,
(29)
The equation D(N, N) = D(N - 1, N ) gives the value of N for
which the first trailing packetand the leading packet have
equal amounts of charge. The solution is N = l/a. It can be
shown in general that for every l / a cell transfers, the peak of
the charge distribution shifts back by one unit, e.g., after 2/a
transfers, the second trailing packet contains the largest fraction of the charge. This constitutes a delay in addition to the
delay time N/fc required to clock a packet out of a CCD, i.e.,
the total delay is
7=N/fC(l + a ) .
(30)
E. Effect ofTransfer Inefficiency on Sinusoids
The
effect of transfer inefficiency on a sinusoid of frequency
f transferred though n elemental transfers at frequency f , is
characterized by a gain G and a
shift A#, where [ 101
The dispersion caused by the transfer inefficiency is shown
for the
few transfers in Fig. 11. The fractional loss from The
f
&
forNa<< 1.
G = exp { - n e [ 1 - cos(27rf/fc)] }
(31)
A# = -nE [2nflfC - sin (27rf/fc)l.
sampling frequency is equal to the clock frequency; there-
44
PROCEEDINGS OF THEIEEE, JANUARY 1975
z
0.6
0.2
‘0
0.l
0.20.3
f/f,
04 05
f/f,
Fig. 12. Effect o f transfer inefficiency on the propagation o f sinusoids through a CCD shift register. Left curves show gain versus
signal frequency (normalized toclock
frequency). Right curves
show phase shift versus signal frequency. The parameter is the
product o f number of transfers and transfer inefficiency.
fore, the Nyquist limit is fc/2. In Fig. 12, the gain and phase
shift are plotted versus frequencyup to the Nyquist limit,
with ne as a parameter. From Fig. 12, it should be noted that
if ne Q 0.1, then 0.8 < G < 1.0 and 0 < A4 < ~ 1 1 0 .These
limits are acceptable for most applications.
F. DarkCurrent
Since a CCD operates by controlling depletion volumes,
there is a continual generation of hole-electron pairs due to the
thermal vibration of the silicon lattice, and minority carriers
tend to flow to thepoint of minimum potential where they are
collected. The three components of dark current are thermal
generation at the~Si-SiO2 interface, thermal generation in the
depleted volume, and thermal generation in the neutral bulk
within a diffusion length of the interface.
The dark current imposes three limitations on the operating
characteristics of a CCD-finite storage time,fixed-pattern
“noise,” and temporal noise. Each of these effects will be discussed in the following paragraphs.
The length of time required for thedark current to fill a well
is called the storage time T,, and is given by
(33)
where Ceff is the effective storage capacitance per unit area of
the well, Jd is the dark current density, and AV is the height
of the barrier isolating the wells. Storage times of 1 0 0 s have
been achieved in some devices; however; values of 0.1-1 0 s are
more typical.
Thedarkcurrent is not completelyuniformthroughout a
device. The darkcurrent signature of a device is obtained by
integrating in the dark. A darkcurrent signature for a short
linear device is shown in Fig. 13. Theeffect of this darkcurrent nonuniformity is to impose a fixed-pattern “noise” on
the signal. If the element-to-element nonuniformity is m d ,
then the minimum signal that can be detected will be limited
to N’ = m d . If the element-to-element variation of Nd is
10 percent, then at room temperature this will limit the minimum detectable signal to about 1000 electrons.
Since the generation process is random,there is temporal
noise associated with it. Since the process obeys Poisson statistics, the temporal noise is the square root of the mean. This
noise source will also limit the imagery at room temperature.
Since the states that contribute to
thermal generation are
near the center of theforbidden gap, thetemperature de-
Fig. 13. Oscilloscope trace of a CCD after integration in the dark,
showing nonuniformity in the dark current from cell t o cell.
pendence of the dark current is
-
Jd(-Eg/2kT)
exp
(34)
where E, is the energy gap. Thus the dark current is a strong
function of temperature, decreasing by a factor of 2 for every
10°Cdecrease in T. The dark-current spikes have the same
temperature dependence as the average dark current. If a d e
vice having Jo = 10 nA/cm2 at 2OoC is cooled to -50°C, then
the number of electrons per cell due to the dark current is approximately 80. A 10-percent nonuniformity will impose a
detectionlimit of 8 electronsand the temporal noise is 9
electrons.
G. Square-Wave Driver Power Dissipation
The equivalent circuit of a square-wave clock driver is simply
a series RC circuit, where R is the internal resistance of the
clock driver and C is the capacitance on a clock line. Assume
that the voltageswingisV and the clock frequency is fc. i f
f;’ >> R C , the energy dissipated in R during charging or discharging C is
Each CCD bit is charged and discharged once per cycle. Thus
the average power dissipated in thedriver per CCD bit is
Pavg = Chit v2fc.
(36)
H. SinusoidalDrivers
The power dissipated in a sinusoidal driver per CCD phase is
(37)
where V is the peak voltage at the CCD electrodes, and fc is
thefrequency
of the driver. For practical cases, R <<
(2nfcC)-’, and the averagepowerdissipated
per CCD bit is
where Q is the quality factor of the circuit: Q = 2nfPC.
BARBE: CHARGECOUPLED IMAGINGDEVICES
45
e
-D
d
10-4
t
m
4
TWO-PHASE
U
Y
z
0
I-
2
m
0
n
e 10-6
:
%
0
BI
3
POLYPHASE
Fig. 14.
Potential profie illustrating power dissipation in a two-phase
device.
lo-’,
10
100
CLOCK FREPUENCY (MHz)
Fig. 15. On-chip power dissipation versus clockfrequency
For tuned sinusoidal drivers, Q can be quite large thereby
reducing the driver power requirements considerably.
I. On-Chip Power Dissipation
For any CCD there is power dissipated on the chip per CCD
bit due to the current flow [ 121 :
P=(J*&)V=(pu*b)V
=pV(u. &)=pVuZ/p
(39)
for two-
phase and polyphase CCD’s.
Therefore, the total averagepower
two-phase CCD is
dissipation perbit
for a
Fig. 15 shows typical power dissipation curves for two-phase
and polyphase CCD’s at saturation.
From (36) and Fig. 15, it can be shown that for a two-phase
device at saturation drivenby a 10-MHz square-wavedriver,
the driver power dissipation per bit is about a factor of 30
greater than the on-chip power dissipation per bit.
J current density along the channel,
8 electric field along the channel,
bit volume,
average bit velocity,
effective mobility,
bitlength,
number of electrons per bit,
f , clock rate.
V
u
p
L
n
For two-phase CCD’s that have built-in barriers, there is an
additional power dissipation term resulting from the need to
“lift” the charge packets over the built-in barriers to allow
transfer to occur [ 131. This is illustrated in Fig. 14.The
energy required to lift a charge packet containing n electrons
over a potential barrier AV is the neAV. This is done twice
per clock period; thus theaverage power dissipated per bit due
to themechanism is
P = 2neAVf,.
(40)
Thefactor AV can be calculated with reference to Fig. 14,
whichshows thepotential profile for a two-phase steppedoxide device. V, is the built-in barrier. V l 2 is the surface
potentialdifferencebetween the polysilicon electrode when
the clock is low and the aluminum electrode when the clock
is high. The average potential of the charge packet is $6 V =
ne/Cp, where C p is the capacitance of the polysilicpn MOS
capacitor. From Fig. 14, it then follows that
J. ClockingTradeoffs
Fig: 16 shows a four-phase CCD structure.Thereare
two
methods for clocking four-phase devices-normal clocking and
double clocking-as shown in Fig. 17(a) and (b), respectively.
In the normal-clocking mode, charge is stored under only one
electrode, asshown in Fig. 17(c). In the double-clocking
mode, charge is stored undertwo adjacent electrodes, as shown
in Fig. 17(d) [ 141.
From stability and speed considerations, practical CCD
structures have overlapping electrodes. Table I compares the
characteristics of two-, three-, and four-phase CCD’s having
overlapping electrodes.
It is assumed that the minimum geometry along the channel
(electrode length or implantation dimension) is L; therefore,
the cell or bit length of two-phase and four-phase devicesis
4L while the cell length of a three-phase device is 3L. Recall
that each time a capacitance C (corresponding to one electrode
of length L ) is charged or discharged, the power dissipation in
a square-wave driver is $ C V 2 . To move a charge packet from
one cell to the next in two-phase and four-phase devices, electrodes have to be charged or discharged a total of eight times
in f i l s. Thus the driver power dissipation is 83CV’fbit =
4CV2f,. To move a charge packet from one cell to thenext in
a three-phase device, electrodes have to be charged or discharged a total of six times in f;’ s. Thus the driverpower
dissipation is 3CV2f,. Since the capacitance of two- and fourphase cells is 4C and the capacitance of a three-phase cell is
3C, the general expression for square-wavedriver dissipation
is CcellV’fc.
The two-phase and four-phase double-clocking schemes have
an inherent charge pushing action, whereas this must be built
into the three-phase clocking pulses, as shown in Fig. 1.
PROCEEDINGSOFTHEIEEE,JANUARY
46
3
Fig. 16. Croglaectiond view of a four-phase CCD.
1975
signal-handlingcapacity is equivalent to that of a device storing
charge under a single electrode having a 12-V barrier.
Typical two- and four-phase CCD's with overlapping gates
utilize polysilicon-aluminum oranodized
aluminum technology. Overlapping-gate, three-phase devices utilizetriplelayer polysilicon technology. All three designs can be selfaligned.
In summary, thetwo-phase CCD requires thefewest transfers,
the three-phase CCD has the highest packing density, and the
four-phase CCD operated in the double-clocking mode has the
largest signal-handlingcapability.
IV. LOW-NOISEINPUT CIRCUITS
U
4
1
2
3
L
4
1
Fig. 17. Four-phaae clocking. (a) Normalfour-phase clocking waveforms. (b) Double-clocking waveforms. (c) Length o f potential wells
with normal clocking. (d) Length of potential w
e
b withdouble
clocking.
TABLE I
CLOCKINGTRADEQFFS
Z-PHASE
C P W
3-w#€
r
CELL LENGTH
3L
4L
4L
A means of introducinga low-noise charge packet into a
CCD is illustrated in Fig. 18 [ 151. The receiving well is filled
with electrons to a level higher than the largest expected signal. This can be accomplished by pulsing the input diode to a
low voltage. With the receiving well full, the input gate is set
to the desired level, andtheinputdiode
is pulsed positive.
This removes electrons from the receivingwell until the POtential of the receiving well increases to the point where the
channel pinches off. This process can be modeled as that of
charging acapacitorthrough
%resistorhaving
aJohnsonNyquist spectral noise density V,(f) = 4kTR Vz/Hz. If the
charge Q on the capacitor CRW is treated as a random variable,
the variance of is kTCRw (C)', where CRWis the capacitance
of the receiving well. For CRW 0.1 pF, the noise in a charge
packetintroduced intothe receivingwell is approximately
130 electrons.
This technique can be extended to further reduce the input
noise by presetting a small floating diffusion and then transferringthe charge fromthefloatingdiffusion
intothe first
CCD well [ 15 I . The structure and the timing diagram for this
technique are shown in Fig. 19(a) and (b), respectively. The
advantage of this technique over that of injecting from asource
diffusion into thereceiving wellvia a gateis that the capacitance
of the floating diffusion can be made smaller than CRW. Thus
the noise is less.
In surfacechannel area arrays, it is necessary to insert a fat
zero into each column. The techniques described in the f o r e
going can be used to insert the fat zerowith low temporal
noise; however, the charge entered from column to column is
not uniform due to geometrical tolerances. For example, due
to photolithographictolerances,theuncertaintyin
the capacitance of a receivingwell orfloatingdiffusion
is about
onepercent.Thus,for
a ten-percentfatzero,
the nonuniformity in fatzerofromcolumn
to column is about
500 electrons. This imposes an obviouslimitationin
lowlight-level imaging applications.
v. LOW-NOISEOUTPUT CIRCUITS
Typical built-in barriers in two-phase devices have heights of
4 V, whereas about 6 V can beachieved with barriers controlled by gate voltages. Therefore,the signal-handling capacity(interms
of barrier height) of two-phase devicesis
about 4 V, and for three-phase devices it is 6 V. Since the
four-phase device operated in the doubleclocking mode stores
charge under two electrodes and has barriers of about 6 V,its
A , Correlated Double Sampling
Consider a capacitor C with an initial charge Q o and cone
sponding voltage Vo. At t = 0, a noiseless idealswitch is
closed, charging the capacitor to the voltage VDR through a
resistor as shown in Fig. 20. The mean charge on the capacitor,
Q m , is
Q , ( t ) = C V ~ R(1 - e-'DC)
It is shown in the Appendix that the
from the mean value of Q(r) is
-
+ eo.
(44)
mean-square deviation
( Q ( t )- Qm(r))z E Q(t)z = kTC (1 - e-2tflc)
(45)
41
BARBE: CHARGECOUPLED IMAGING DEVICES
I
Vln
T
VDR
-
t = o A
INPUTDIODE
Fig. 18. Input structure.
t
INPUT
GATE
'ID
'16
?
P
/
- T
INPUT
DIODE
+2
+3
+I
P
P
P
t
(a)
K
T
R
k
IC
-
Fs.20.
FLOATING
DIFFUSION
R 4
z
Nob-equivalent circuit for the charging of a capacitor through
a resistor h a w thermal noise.
vml---m;*
v't)
v,
t
--t
RESET
SWITCH
TURNED
ON
RESET
SWITCH
TURNED
OFF
Fig. 21. Curve of lwulvoltage and noise voltage across a capacitor as a
function of timewhenthe
apadtor k chuged through a resistor
having thermal no&.
c,
DIODE ACTS'AS DRAIN
0)
Fig. 19. Low-noise input structure utilizing a low-aprcitance fIoathg
diffusion.
MOS
PREAMP
OUTPUT
DIODE
?;
------
or in terms of voltage
-
I
Fa.22.
The complete charging curve is shown in Fig. 2 1, Thus, when
chusing a Capacitor througharesistor,the
variance ofthe
voltage across the capacitor is small for t << 4RC and is
kT/C for t >> RC. The sisnificanceof this is that the correlation time for Vc(t) is i R C , which forms the basis for comehted double sampling.
The conventional CCD output circuit is shown in Fig. 22,
m d the voltage across C is shown in Fig. 23. The readout sequence is as follows. The output diode is reset to some large
reversebias voltage VDR through a MOSFET switch. The RC
time constant is
RonC= (lo4 S2 X
F) =
'
Conventional reset amplifier output circuit for a CCD.
MEAN-SWARE
NOISE VOLTAGE
RESET CLOCK
FEEDTHROUGH
kT/A
w
8
s.
When the switch is turned off, there will be a droop in the
voltage waveform across C due t o resetclockfeedthrough
(Miller effect) in thereset transistor.
~ e R C ~ e c o n ~ a n t i s R o f f C = ( 1 0 1 2 10-13F)=10-1s.
S2X
Next, the charge packet is clocked into the output diode, red u a its reverse bias. The cycle then repeats itself. Typically,
the voltage is sampled at B with respect to some fmed referma. In this case, the noise voltage in this sample is
INTERVAL
'
'
LCHAROE
PACKET aomm
INTOOUTPUTDIFFUSION
Fig. 23. Output voltage waveformof reset amplifier output circuit.
(kT/C)'12. However, if two samples are taken, one at A just
after the reset switch is turned off and the other atB after the
signal charge has been clocked into the output diode, and if
the time between A and B is << :R&fC, then the noise on
48
IEEE.
PROCEEDINGS OF THE
these time samples is correlated and can be removed by subtracting VA from V’ [ 161.This is called correlated double
sampling. The subtraction process is achieved by inverting
and storing the reset voltage for subsequent comparison with
the signal voltage.
Since the RTC noise is removedby correlated double sampling, the remaining noise is due to the amplifiers. The noise
in theon-chip MOS preamplifier referred to theCCD channel is
JANUARY 1975
I N P U T CCD LINE
m
A
L
OUTPUT
Fig. 24. Schematic diagram of charge-coupled distributedampW1er.
INWT
CCD
where CO-N isthe CCD output-node capacitance, B is the
bandwidth, and ,g is the transconductance of the MOS preamplifier. For CO-N = 0.1 pF, B = 4 MHz, and ,g = 250
pmho, N:, = 7 0 (electron)2.
At the output of the preamplifier, the signal is still at a low
level. If an off-chip amplifier having an equivalent input noise
current in (amperes per root hertz) is used, this noise referred
to theCCD channel is
I I
OUTPUT CCD
ELECTRODE
CHANNEL
STOP
Nt SOURCE
For in = 1 pA/(Hz)’12, N& = 250 (electron)2. Therefore, the
total noise referred to the CCD channel is N, 5 18 electrons.
B. Dism’buted Floating-Gate Amplifier(DFGA)
The distributed floating-gate amplifier (DFGA), shown schematically in Fig. 24, makesuseof
repeated nondestructive
sensing of charge packets by floating gates that are over the
CCD channel [ 171. A schematic diagram of a floating-gate
amplifier stage is shown in Fig. 25. The floating gate is biased
to the desired operating point via capacitive coupling to a bias
electrode (not shown) above the floating gate. When a charge
packet containing Si electrons transferringalong the DFGA
input register moves under a floating gate, a potential change
AVFG is induced on the floating gate.
The floating-gate responsivity 61 is defined as
OUTPUT CCD
CHANNEL
Fig. 25. Schematic diagram of a single distributed floatinggate amplifier (DFGA) stage.
Channel
stop (Cs1
/
/
I
LCCD
Channel
“ O S Channel
Fig. 26. Capacitance equivalent circuit of a single floating-gate amplifier stage.
Theoperation of the DFGA is as follows. When a charge
packet Si in the DFGA input register is transferred under the
F i t floating gate, an amplified chargepacket [ ( 0 . 4 / f c )Io - GSi]
(49) is injected into the first cellof the DFGA output register,
where Io is the bias current. The two registersare clocked
The calculation of 61 follows directly from the capacitance synchronously so that when Si is under the second floating
equivalent circuit shown in Fig. 26, and 61 is
gate, [ ( 0 . 4 / f c )Io -. CSil is in the second cell of the DFGA
output register, and another amplifiedcharge packet is ineC1
61=
. (50) jected into the second cell of the DFGA output register. Thus,
C1(C2 + CGSUB+ C c s ) + C3 (CI + C2 + CGSUB+ ccs
after M DFGA stages, the charge at the outputof the DFGA is
The voltage on the floating gate modulates the flow of elec- M [ ( 0 . 4 / f c )Zo - GSil, and the output signal So is So = MGSi.
trons from a source diffusion into the adjacent potential well The noise in the charge packets in the DFGA input register,
of the DFGA output CCD register. The charge gain G between Ni, is amplifiedand added inthe sameway. Furthermore,
a position in the .DFGA input register and the corresponding noise is introduced at each DFGA stage due to the amplificaposition in the DFGA output register depends on the amount tion and injection processes; let NA denote the noisecharge
of time r that the charge packet is under the floating gate and introduced at each stage referred to the DFGA input register.
The noise charges introduced at each stage, (NA) I , (NA )2, and
also on 61:
(NA)M,are uncorrelated. Therefore, the total noise (in numG = 61g, r / e
(51) ber of electrons) at the outputof the DFGA, N o , is
where ,g is the amplifier transconductance. It is important to
N, = ( M ~ G +
~ MN N~ ~~ ~ 1 ’ 1 ~ .
clock the DFGA in such a way that r is maximized. Clocking
Then the output signal-to-noise ratio is
schemes havebeen used which give
(52)
r
(53)
0.4/fc
where f , is the clocking frequency. If ,g = 10 pmho, 61 = 5
pV/electron, and f , = 8 MHz, then G 5 16.
Thus the condition required to preserve the signal-to-noise
DEVICES
BARBE:
ratioinherent
register is
IMAGING
in the charge packets in the DFGA input
49
3 ) Output
Resetnoise: A commontechniquefor CCD readout involves the charging of a capacitance through a switch (reset).
Unless special techniques are used, e.g., correlated double sampling, the noise in this reset process which is due to thermal
Analysis of the noise sources in the DFGA indicates that the noise in the reset circuit is directly reflected in theoutput
dominantnoise is shotnoise in the floating-gate amplifiers. signal. Thus the resetlevel is a random variablewhose stanThe number ofnoise electrons referred to the DFGA input dard deviationis the reset noise.
MOS amplifier noise: Due to various noise sources in an
CCD channel is
MOS amplifier, the output voltage is a random variable. The
standard deviation of the output voltage referred back to the
input (as a charge onthe gate) is the amplifier noise. By
characterizing the noise as a charge on the gate of the MOS
For f , = 8 MHz, Io =
A, g , = lo-’ mho, 61 = 5 * l o m 6 preamplifier, it canbe directly comparedwith other noise
V/electron, and Si = 0, NA = 36 electrons. For Ni = 20 elec- sources in the CCD.
trons, the required number of stages to preserve the signal-toSignal processing noise: It is assumed that any appreciable
noise ratio in the DFGA input CCD channel accordingto (55) noise introducedby off-chip signalprocessing should bereisM = 16.
ferred back to the gate of the preamplifier and includedin the
At the outputof the DFGA, the signal has been amplifiedby noise analysis.
the factor M G ;thus the signal is at a high level when it is taken
off the chip. Theobvious way to reducethe noise of the 8 . Bulk-Trapping Noise
DFGA is to increase 61 and g , .
Models exist for all of the noise sources except bulkstate
trapping. Therefore, it is appropriate to discuss a model for
VI. NOISE
bulk-state trapping in some detail. Bulk-trappingstates are
A.Types
characterized by discrete energylevels.According
to the
The types of noise expected to be present in a CCD can be Shockley-Read theory, the emission time characteristic of a
separated into threecategories: those associated with the
input, bulk-trapping state at energy A E below the conduction-band
those associated with integration and transfer, and those asso- edge is proportional to exp (AEIkT). If a charge packet is
located in a volume V for time T and the emission time of the
ciated with theoutput.Thetypes
ofnoise expectedfrom
bulk stateis re, then the probability of occupation is
these three operationsare defined as follows.
1 ) Input
P = l - e +e .
Photon noise: The emission of photons from any sourceis
(57)
a random process. The number of photoelectrons collected in
a potential well in time A t is therefore a random variable. The Since the random variable of interest is the density of traps
standard deviation of this random variable is the photon noise. occupied at time 7 , the mean value of nt is
Since the statistics for the emissionprocess are Poisson, the
nt = PNt
(58)
standard deviation equalsthe square root of the mean.
ElectTical inputnoise: The injection of charge from a and the variance is
source diffusion into a potential well is a random process ben: = ( 1 - P ) P N t .
(59)
cause of thermal noise in the resistance of the input circuit.
The number of electrons injected into a potential well from a Consider a buried-channel area imager. The operation can be
source diffusion is therefore a random variable whose standard separated into three distinct steps: 1) integration, with effecdeviation is the electrical input noise. When a bias charge is in- tivevolume VI and integration time 71; 2) vertical transfer,
jected in this way, the noise is sometimes called fat-zero noise. with effective volume Vu,time r,, andnumber of transfers
2 ) Integration and Transfer
M,; and 3 ) horizontal transfer, with effective volume VH,
Fast interface-state noise [ 181, slow interface-state noise time TH,and number of horizontal transfers MH. It follows
[ 191, and bulk-state noise: The transfer of electrons from one that the variance of the complete sensing and readout operasite to another is a random process because of trapping and tion is
emission by fast interface states, slow interface states (oxide
- N V (1 - e-7r/7e) (e-7r/7e
1
states), and bulk states. The standard deviation of the number
n:t r
of electrons transferred from one well to the next is the noise
+ N t V & , ( l - e -7dre (.-Tu Ire 1
associated with each of the trapping processes. Fast interfacestate noise should be present in surface-channel CCD’s during
+ N t VHMH ( 1 - e-7H1Te) (e-TH’Te). (60)
transfer, slow interface-state noise may be present in surfacechannel CCD’s during integration, andonly bulk-state noise The effective volume is calculated as follows.
should be present in buried-channel CCD’s.
V = (area occupied by the charge packet under an electrode)
Dark-current
noise:
Thethermalgeneration
of holeX (thickness of theregion occupied by thecharge packet)
electron pairs in the semiconductor is a random process that
= A X t.
contributes charge to the CCD potential wells. Therefore, the
number of electrons in a charge packet due to thermal genera- At high signal levels, the thickness from( 9 ) is
tion is a random variable whose standard deviation is the darkt = -N
= - nlA
current noise. Like photon emission, this is a Poisson process;
thus the standard deviationis the square root of the mean.
50
PROCEEDINGS OF THEIEEE, JANUARY 1975
I
I"
N, = 2 x I O "
TABLE I1
SUMMARY
OF CCD NOISES ~ U R C F S
I
ern-'
No =3x10mem-'
0.11
10'
I
1
1
10'
10'
n INWBER OF ELECTRONS 1
IO'
Fig. 27. Bulk
trapping noise (in number of ekctrom) per transfer
versus number of ekctrom in a charge packet for ahallow buriedchaMd d d m .
where n is the number of electrons in the charge packet. Thus
v"-?Z/ND.
Then the number of noise electrons duet o bulk trapping can
be written as
+ M H ( ~- e7H1re) e-TH''el
1
.
(62)
lh
3
Thefactor (1 e-""
has a maximum valueof
when
r = 7e In ( 2 ) and drops off exponentially when 7 increases or
becrcases.
Equation ( 6 2 ) does not apply for n small enough t o make
n/ND es LD ,where LD is the extrinsic Debye length. For small
n, the formulation is as follows [ 201. According to (10),
Using the conservative criterionthat most of the electrons
have energies < 6kT, then it follows that when (A&b)nux =
4We,
The effective area is the area within which electrons having
energy less than 6kT are confined. Due to thecurvature of the
potential well, this area is clearly less than the area of the
zero uniformly into each cell. The basic problem arises from
thenonuniformcapacitance
of eachsource providing each
column with a fat zero. If the variation is 1 percent, then the
fured-pattern noise for a 10-percent fat zerois -500 electrow
Thus, without special off-chip processing, the surfacechannel
area imager will be limited to a noiseequivalent signal (NES)
of about 5 0 0 electrons.Nonuniform
dark current has the
same effect; however, it can be reduced substantially by coding the array.
rtomgeelectrode.
An accuratedetermination of thisarea
would require the precise knowledge of the shape of the potential wells from computer calculations. Using the quadratic
approximation for the potential well gives Aeff Y 8.8 X lo-'
U s i n g , L ~= 4 X 10" cm gives Veff = 8.4 X
cm3.
Using N, = 2 X 10" tm-' gives 0 . 2 8 4 electrons as the
VI.IMAGINGARRAYS WITH MECHANICAL Scm
womt case noise level at low signal levels. The bulk-state noise
A . Linear Arrays
versus signal level is plotted in Fig. 27.
Linear imaging arrays can be designed in three ways. 1) A
Table I1 gives expressions and numerical estimates for the
wirncea of the processes which contribute to noise in surface- simple CCD shift register can be used if it is clocked in such 8
channel CCD's at room temperatureand in buriedchannel way that the shiftout time is very much less than the integn&D's at roomtemperature and at -5OOC. Fromthis noise tion time. This conditionreduces image smear caused by
analysis, it is concluded that the number of noise electrons at shifting pixels through light-sensitive regions. 2 ) An imager
the output of a cooled buriedchannel CCD could be as low as can also be designed with separatesensors and shielded readout
register as shown in Fig. 28. After integration in the #mom,
10 electrons.
An additional limitationon surfacechannel area arraysis the the charge configuration is shifted into the shift register, Le., I
"fixed-pattern" noise arising from the inability to insert a fat porallel-tweries transformation is effected. The line of video
&'.
51
BARBE: CHARGECOUPLED IMAGING DEVICES
OUTPUT
DICDE
'E
I
LATERAL TRANSFER
ELECTRODES 6 p 6
W TRANSFER
f'z's
ELECTROOES
Fig. 28. Linear CCD imaging array with single readout register.
J
a
E 0010~
-M
a
v)
TRANSFER
GATE
IMAGING
GATE
-
/
-
FAIRCHILD 5 0 0 x I
CCLID *8 (?-UP)
AX=lOOA
0.001
0.4
Fig. 30. Spectral
I
I
0.6
0.8
I
I
1.0
1.2
WAVELENGTH (&
I
I
1.4
1.6
reaponsivity veraus wavelength
illuminated linear array.
for
I3
frontside-
MOS
REGISTER
PREAMP
ALUMINUM
LIGHT
SHIELD
PHOSPHOROUS
DOPED
POLYSILICON
UNDOPED
THERMAL
PHOSPHOROUS
IMPLANTED
N -LAYER
P-TYPE
SILICON
SiOp
(b)
Fig. 29. Linear CCD imaging array with double readout register.
is then shifted out via the shift register while a new line is
being integrated. This design effectively eliminates the image
smear problem. 3) The third design, shown in Fig. 29, uses a
line of sensors and two shielded readout registers. After integration,odd-numbered pixels are shifted intoone readout
register and even-numbered pixels are shifted into the other
readout register. The information in the two vertical registers
.is clocked into atwo-bithorizontal register thus reforming
the pixels in the order in which they were formed. The number of bits in each verticalregister is half the total number of
pixels. Thus, for two-phase vertical registers, thenumber of
transfers required to clock out the pixel farthest from the output is equal to the number of pixels. The primary advantages
of 3) are higher sensor packing density and fewer transfers to
read out a given pixel.
Linear arrays can be excited through frontside illumination
if polysilicon, which is nearly transparent, is used forthe
electrodes. Fig. 30 shows the spectral responsivity versus
wavelength for a 500clement linear frontside-illuminated device [ 2 l l . The structure in the response is caused by inter-
1
t
WAVELENGTH (
p
u
n
)
Fig. 31. Spectral rcsponsivity vmus wavelength for thinned bacbldoilluminated linear a m y .
ferenceeffectsat
the layer boundariesshownin
the croa
section of Fig. 29. If the device is thinned in the sensor a m
toabout half thecenter-tocenter pixel spacing, and if tIw
backside is accumulated to minimize recombination at the
back surface,thearray can be backside illuminated. In thit
case, losses due to multiplereflectionsatlayer
bowwhich occurinfrontside-illuminated devices are eliminatd;
also, thestructureinthe
response curve is eliminated. "be
spectral response curve for a thinned backside-illuminated device is shown in Fig. 31 1221.
Table I11 gives the parameters of linear imagers which hrva
been fabricated. The primary application of long linear m
i y
ing chips is "reading" printed pages.
Fig. 32 shows the noise-equivakmt power (NEP) v
a
m
power for a buriedchannel frontside-illuminated 5OCWemat
PROCEEDINGS OF THEIEEE, JANUARY 1975
52
TABLE I11
LINEARIMAGING CHIP PARAMETERS
OUTPUT SERIAL REGISTER &
Fig. 34. Schematic diagram of
a multicolumn time delay and integration (TDI) chip.
5
'""1
'
10-11
Io+
I
NEAR
I
}
END OF ARRAY
(REFERENCED
TO OUTPUT1
POWER (watts 2854.K)
I 1 1 1 1 1 1
10-0
I
I
I I 1 1 1 1 1
I
I
lo-'
, 1 1 1 1 1 1
I
,
1
1
1
1
1
10-6
INPUT POWER (WATTS)
Fig. 32.Noiseequivalent power (NEP) versus input power for 500element linear buried-channel array.
0
PIXELS
Fig. 35. Plot of peak relative signal versus number of TDI pixels.
array [ 2 11. This array produced the first CCD imaging which
was limited by temporal noise. At low light levels, the noise
per pixel per frame is 250 electrons, due to a noise levelof
approximately200electronsin
the reset amplifier and 150
electrons of shot noise in the dark current. Fig. 33 shows an
example of
imaging
from a1728element
high-resolution
buried-channel arrayto be used in facsimile applications.
Fig. 33. Image of facsimile chart using a 1728element linear CCD.
B . Time Delay and Integration (TDI) Arrays
In applications where the CCD imaging chip has a velocity
relative to the object to be imaged, the CCD can be used in the
time delay and integration (TDI) mode to enhance the signalto-noise ratio. In such applications which lend themselves to
this mode of operation, a CCD composed of N , columns each
containing N,, bits is oriented in such a direction and clocked
at such a rate that the transfer of pixels down the CCD columns
compensates for the movement of the imagealong the CCD
columns due t o the relative velocity of the chip and the object.
The array organization for this mode of operation is shown in
Fig. 34. Fig. 35 presents a plot of the relative signal achieved
experimentally versus thenumber of pixels integrated[231.
After N,, bits of TDI, the signal is N,,Sp, where S, is the signal
representing a single bit without TDI. The noise accumulated
during transfer, i.e., shot noise in the dark current and trapping
noise, adds incoherently, and after Ny bits of TDI, the noise is
(N,,)112Ns. Thus the signal-to-noise ratio with TDI is greater
than that without TDI by the factor
BARBE: CHARGECOUPLED IMAGING DEVICES
53
n
VIII. AREAARRAYS
A . Tradeoffs
There are two basicdesigns for CCD low-light-level-imaging
chips-backside-illuminated
frame transfer (BIFT) and
frontside-illuminated interline transfer (FIIT).
To obtain the best possible performance from a CCD array,
it is necessary to maximize the signal-to-noise ratio. The noise
is basically determined by thetechnology used (surface channel
and buried channel) and by the noise characteristics of the
amplifier. On the other hand, the responsivity is largelydetermined by array design.
The purpose of this section is to provide a framework for
comparing CCD arrays of different design and to compare the
BIFT and FIIT designs in detail. To make the comparison, we
assume that the same CCD technology and amplifier technology are used for bothdesigns.
The general framework for comparison is formulated in
terms of the overall system responsivity as a function of spatial
frequency. The CCD chip design parameters that affect system
responsivity are then used to calculate the system responsivity
for the BIFT and FIIT designs. Finally, curves of system responsivity versus spatial frequency are plotted for comparison.
I ) System Considerations
a ) Chip responsivity at zero spatial frequency: The sensor
chip responsivity at zero spatial frequency, Rchip, is defied as
Rchip =
Fig. 36.
Schematic diagram of imaging system.
The wide-band irradiance is
H=
l:
H i dh.
Combining (as), (67),and (68) gives
The ratio
peak signal current out of sensor chip I,
= - (65)
irradiance incident chip
on
H
where the units of H are W/m2.
i ) Narrow-band excitation: For narrow-band excitation
between the wavelengths h and h + d h , the signal current is
is the responsivity of the sensor resolution element, i.e., the
chargecollectedper joule of incident energy. Then the chip
responsivity can be written as
I,(X) = (incident irradiance per unit wavelength)
Rchip =
X (incremental width of the excitation band)
X (active area of resolution element)
X (integration time)
X (energy per photon)-'
X (number of electrons collected per incident photon)
X (charge per electron)
X (output current per electron collected)
= H i d h A X A Y tint% (hclW-' V ( N e ( g m l C )
(66)
where
irradiance per unit wavelength,
of resolution element,
Aarea
x A y active
integration time,
tinteg
photon energy,
hclh
no. of electrons collected in a resolution element
1)
no. of photons incident on a resolution element '
e
electronic charge,
transconductance of onship preamplifier,
gm
C
effective capacitance at preamplifier input node.
Hk
gm
c AxAY tinteg Relement
(71)
b ) System responsivity at zero spatial frequency: In practical applications, a lens must be used with the sensor chip,
and it isthe performance of the overall.system which is important. The lens-sensor system is shown in Fig. 36, in which the
symbols used are defined as follows:
W
h
D
f *
8,
width of the chip,
height of the photosensitive part of the chip,
absolute lens aperture,
lens focal length,
vertical field ofview.
The focal ratio is defined as
F =f * / D
(72)
and the relation between chip height, focal length, andoffield
view is
tan (0,/2) = i-h / f *.
(73)
The system responsivity at zero spatial frequency Rwstem is
defined as
ii) Wide-band excitation: For wide-band excitation,
the
Rsystem =IslN
(74)
signal current is obtained from (66) by integrating from 11 whereN is the Scene radiance in W/m2 . ST.
to hz :
The sensor irradiance
scene and
radiance are related by
gm
I, = - A x A y tinteg
c
eHi s(X)
x
dh.
(67)
H = NTn/4F2
where T is the lens transmission.
PROCEEDINGS OF THE IEEE, JANUARY 1975
54
TRANSFER
FRAME
INTERLINE
TRANSFER
Combining (72)-(75) gives the system responsivity
Y'
Equation (76) can be written more explicitly by considering
the narrow-field-of-viewcase and the wide-field-of-viewcase
separately.
i) Narrowfield-ofview case: For narrow fields of view,
the limiting factor is the absolute lens aperture; thus the focal
ratio used in (76) is set by the field of view and the maximum
practical lens aperture. Combining (72), (73), and (76) gives
u
...............................
X
..
........ ........
X'
Fig. 37. Operation o f frame-transfer and interline-transfer chips with
2: 1 interlace in the vertical direction.
BACKSIDE-ILLUMINATEDFRAMETRANSFER
ii) Wide-field-ofview case: For wide fields of view, the
focal ratio is the limiting factor; thus the focal ratio is chosen
as the minimum value determinedbypractical lens design.
The systemresponsivity for wide fields of view is given by (76).
c) System response at nonzero spatial frequencies: Since
most of the informationcontentina
scene is containedin
high spatial frequencies, the system response should include a
factor which takes into account the rolloff of system response
with increasing spatial frequencies. This is accomplished by
multiplying (76) by the modulation transfer function (MTF)
of the sensor chip and the MTF of the lens:
FIELD B
_L
FRONTSIDE-ILLUMINATEDINTERLINETRANSFER
EE
d ) Basis for comparing sensor chips: The basic f i i of
merit of a sensor chip is the signal-to-noise ratio. In chargecoupled imagers, the noise can be attributed broadly to two
sources-noise sources within the CCD proper, and noise due
to the preamplifier. The output noise current is then
In =
[t)2
+I;pa]i'2
(79)
where qn 1s rms noise charge per chip resolution element due
to noise sources in front of the preamplifier, and Inm
is rms
noise current due to preamplifier noise sources.
The basic figure of merit of a chip is the signal-to-noiseratio
If noise sources in frontof the preamplifier dominate, then the
signal-to-noise ratio is independent of g,,,/C. If the preamplifier dominates, then a large g m / C ratio is desirable. Another
common way
of
specifying noise performance is noiseequivalent irradiance (NEI), i.e., NE1 is that value of H which
givesIsIIn = 1.
2 ) Chip Considerations
In this subsection we will discuss chip desigh parameters in
terms of their effect on the figure of merit.
a ) Verticalinterlace-integrationtime:
Fig. 37 illustrates
the operation of the backsideilluminated frame-transfer
(BIFT)
-L-r
k-+AX*1/2P
FU. 38. Basic integration cells for backaidailluminated frame-transfer
(BIFT) and fiontside-illuminated interline-transfer (FIIT) chips.
structure and the frontside-illuminated interlinetransfer (FIIT)
structure. In both cases, two-phase structures are shown with
2: 1 interlace in the vertical direction. In the frame-transfer
structure, the top half of the chip is photosensitive. If a frame
rate of 30 frames persecond is assumed, then field A is formed
by collecting photoelectrons under the 4-1 electrodes for s.
This charge configuration is shifted into the shielded storage
register in typically
s. Field A is then read out a line at a
time while field B is being formed by collecting photoelectrons
under the 4-2 electrodes.
In the interline-transfer structure, the shielded vertical readout registers are interdigitated with the photosensitive linerr.
Potential wells areformed in the photosensitive regions by
applying voltages to the vertical polysilicon stripes. The horizontal polysilicon stripes areused to clock the vertical shielded
register. Because the integrating cells and shift-out cells are
separate, the effective integration timefor bothfields A and B
is
s. The operation is as follows. After collecting phot*
electrons in field A for s, the charge configuration is shifted
into the shielded registers and down, a line at a time, into the
horizontal output register. When field A has been completely
read out
s), field B is shifted into the shielded registers and
out. It is important to note that theeffective integration time
for the interlinetransfer structure is twice that of the f r a m e
transfer structure.
&
&
&
(A
BARBE: CHARGECOUPLED IMAGING DEVICES
I
I
l
I
I
l
l
l
l
l
l
55
I .o
l
i
0.8
kz
i
\
0 6
0.6
0.4
0.2
'
G
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
WRMALIZED SPATIAL FREWNCY flf,
Fie. 40. Transfer MTF versus normalized spatial frequency.
FRAME TRANSFER
MAX
l
l
l
I
1
P
1
1
1
0.5
1
1
1
IO
NORMALIZED SPATIAL FREQUENCY
INTERLHE TRANSFER
NX
1
1
f/fMAX
Flg. 39. Integration MTF versus norrmlired spatial frequency for
Ax=#andAx=p.
Using 2 : 1 interlace inboth structureseffectively doublesthe
vertical spatial sampling frequency, and the resulting Nyquist
limit is llp, where p is the center-to-anter distance betwan
adjacentresolutionelementsina
given field on the chip
(pitch), as shown in Fig. 38.
b ) Modulationtransferfunction
(MTF): The MTF describes the rolloff of imager response with increaainp spatial
frequency. The overall MTF of the chip is composed of three
Fig. 41. Frame-transferand interline-transfer chips, with points labeled
to indicate all poaitions relative to output diode.
oid along a CCD shift register,a fraction of the charge e is lost
from each of the samples at each transfer, and this charge is
added to trailing samples. The effect of this dispersion effect
on MTF is given by
l/p. Also, the sampling in any one field occurs at spatial frequency l/p. If the signal to be sampled is at spatial frequency
f, then the frequency canied in the field is f for f < i p . However, if i p f < l / ~the
, frequency carried in the field [24]
is (l/p) - f. Thus the maximum frequency carried in a field is
i p , and the minimum frequency carried in a field occurs when
f = 0 and f = l/p.
Fig. 41 shows the frame-transfer and interline-transferchips.
N, and Ny are the number of geometrical resolution cells in
the x and y directions. Points are marked to denote cells-the
farthest from the outputdiode ( f 1, the center of the photosensitive a m y (c), and the nearest to the outputdiode (n).
Table N gives the number of transfers required to read out
the f, c , and n cells and the rates at which the charge is transferred. The number of transfers in the x direction is the same
for bothframe-transfer and interline-transfer arrays. Therefore,
the horizontal MTF degradation due to transfer would be the
same for both arrays. The number of transfers in they direction is greater for the frame-transfer chip by the amountPN,,,
where P is the number of phases. Therefore, the verticalMTF
for the frametransfer chip is less than that for the interlinetransfer chipas given by (82).
iii) D q f w i o n MTF: If photons are absorbed within the
depletion regions, then we assume that the collection is 100
percent efficient. However, if photons are absorbed away from
the depletion regions, then the charge configuration will sprerd
as it diffuses toward the depletion regions with a resultingdecxease in MTF.
If photons are absorbed a distance d from the depletion rn
gions and if the diffusion length in the silicon is Lo ,then
MTF due to thediffusion of charge is given by [25] ,[26]
Fig. 40 shows the transfer MTFversus normalized spatial
frequencywiththe ne product as the parameter.The symmetry of the curves about f/fm, = 0.5 can be explained as
follows. In a 2: 1 interlaced array, the Nyquist frequency is
Fig. 42 shows thediffusion MTF versus norp.ttl
frequency with d as the parameter.
c) Photoelement responsivity (Relemcnt):
ment responsivity is determined by the effideacy rfth rm
factors: 1) the loss of frequency response due to thegeometry
of the integrating cell (MTFbtq), 2) the loss of frequency response due to transfer inefficiency (biTFmsfa), and 3) the
loss of frequency response due to the diffusion of charge bctween photon
absorption
and
photoelectron
collection
(MTFm).Each of these factors will be discussed separately.
i ) IntegrationMTF: The integration MTF is given by
the Fourier transform of the basic integration cell. For a rectmgular cell of length A x repeated with periodicity p , the
MTF is
mFinteg =
fmu
P
where f m u = l/p for 2 : 1 interlace. For Ax = p, the F i t zero
in the MTF occurs at f = f m u = l/p. For AX =p/2, the first
zero occurs at f m m = 2/p. Fig. 39 gives the integration M T F
versus normalized spatialfrequency.
As shownin Fig. 38,
Ax = A y = p for the BIFT chip and Ax = Ay = p/2 for the
FIIT chip.
ii) Transfer MTF: During the transfer of a sampled sinus-
<
56
PROCEEDINGS OF THE IEEE, JANUARY 1975
NUMBERO F TRANSFERS
m
R
TABLE IV
FRAME-TRANSFER
AND
FRAME
AREA ARRAYS
INTERLINE
f
C
ATVIDEORATE
PNX
1/2PN,
ATLINERATE
PNY
1/2PNy
ATINTERMEDIATE
RATE
P(N, + ZN,)
TOTAL
P = NUMBER OF PHASES
INTERLINE-TRANSFER
n
f
C
n
-
PNX
1/2PN,
PNY
1/2PNy
-
-
-
PNY PNY PNY
1/2P(N,
+
3Ny)
PN,
P(N, + N y )
1/2F'(Nx
+
Ny)
-
(n3rr-0,
%h=%kr+~
TABLE V
TRADEOFFEXAMPLE
ASSUMPTIONS USED IN
1
I
I
I
PARAMETER
!,yf:g:i
TOTALAREA
CHIP
I
NcRMALlZEO SPLLTIAL FREWENCY f / f w x
Fig. 42. Diffuaion MTF versus normalized spatial frequency (p = 1.2
mils b assumed).
VERTICAL
FIELD
VIEW
.
OF
I
FRAME
TRANSFER
XY = A
X'Y' = A
I
r
I
I
rI
SAMPUNC DISTANCE
IN
OBJECT
PLANE
I
RANGE
I
R
I
R
I
I
FOCAL
I
F
I
F
I
RATIO
photons are absorbed and the resulting photoelectrons are collected. Basically four mechanisms act to reduce Relement: 1)
reflectionat layer interfacesbeforethephotonsreach
the
silicon, 2) absorption in these layers before the photons reach
the silicon, 3) recombination at the Si-SiOZ interfaceafter
hole-electron generation, and 4) absorption too far away from
potential wells for the photoelectrons to be collected. Mechanisms 2) and 3) cause a reduction in Relement in the blue,
mechanism 4) causes a reduction in Relement in the infrared,
and mechanism 1) causes interference fringes throughout the
spectrum. Mechanism 1) is mainly responsible for Reiement
being different for BIFT and FIIT structures. Computer analysis [271 indicates that if the layer thicknessesarechosen
properly, 50 percent of the incident photons inthe 0.4-1 .O PITI
band are transmitted into the silicon for the F I R structure.
Therefore, Relement, averaged over the 0.4-1.0-pm band, for
the FIIT structure is one-half that for theBIFT structure.
3) Example
Suppose that an area array for a wide-fieldaf-viewlow-lightlevel application is to bedesigned with the following constraints. 1) Square elements are assumed, i.e., p x = p y = p ; 2)
the distance from the object plane to the image plane, R , is
specified; 3) the vertical field ofview Bv is specified; 4) the
sampling distance inthe object plane, G ~ D is, to be minimized;
5 ) the aspect ratio is specified; and 6) the minimum practical
focal ratio is to be used. The problem is to determine the relative performance of the BIFT and the FIIT chips designed for
theserequirements. We assume that 7) the largest practical
chip for either design has total area A , and that 8) the number
of elements for either chip is N x N y . Table V summarizes,the
assumptions. The image format for the BIFT chips is X by
Y'/2 and the image forma? for the FIIT chip is X by Y. From
7) and 5), it follows that Y = 1.414Y and X' = 0.707X. From
ASPECT RATIO
I
I
%Ll
I
GSD
I
(73), it follows that f*' = 0.707f*. From the magnification
relation
it follows that p' = 0 . 7 0 7 ~ . From (72) and constraint 6), it
follows that D = 1.4140'.
To compare the performance of the BIFT and FIlT chips,
we assume equal-noise performance. Therefore, the figure of
merit reduces to the system response gimn by (78). We also
assume equal-lens MTF's. Table VI summarizes the values used
in (78) and (81). The results of the comparison are given in
Fig. 43. At zero spatial frequency, the response of the BIFT
chip is twice that of the FIIT chip. However, the response of
the BIFT chip rolls off sharply and crosses the response of
the FIIT chip at approximately 0 . 6 / G s ~ .
4 ) Altermte Formulation of Rsysrcm
An alternate definitionof system responsivity is [2 1 1
where S is time amage current out of the CCD per watt input,
and
A = total image format area of the chip
= XY for FIlT
= X'Y '/2for BIFT.
If a CCD array is uniformly illuminated so that every charge
packet contains n electrons, the average current out of the de-
57
BARBE: CHARGECOUPLED IMAGINGDEVICES
___ F l l T
BlFT
MXMALIZED SF’ATIPL FREQUENCY
IN THE CBJECT PLANE
Fig.43.
Relative systems response versus normalized spatial frequency
for strongly absorbed light.
NORMALIZED SPATIAL FREOUENCY ‘/f MAX
CHIP
TABLE VI
PARAMETERSUSED
IN
TRADEOFFEXAMPLE
Fig. 44. Relative response versus spatial frequency in the vertical direction for BIFT and FIIT designs showing aliased spectra(2:l interlace
is assumed).
cluded that the zero spatial-frequency response of the BIFT
chip is twice that of the FIIT chip of equal total size.
5 ) Aliasing versus MTF
Fig. 44 shbws the relative response curves using only the integration MTF curves. The curves are reflectedabout
the
Nyquist frequency fmax to show the amplitude of the aliased
RELATIVE
spectra. Using the criterion that aliasing occurs when the re2
Rflected branch equalshalf of the fundamental branch, itcan be
shown that for boththe FIIT and the BIFT chips aliasing in the
vertical direction occursat frequencies >0.87 fmX. Thus both
TABLE VI1
S Y ~ E RESPONSIVITY
M
TRADEOFFS
designs are equally susceptible to aliasing in the vertical direction.
In the horizontaldirection,the MTF is quite high at
RELATIVE
RELATIVE
RELATIVE
S(mlpi,
qA
?‘
FORMAT AREA
L n t
Qfmax for the FIIT design, and such chips arehighly susceptible
to aliasing.However, in cases where aliasing is an important
1
2
BIIT 1
1
90
1
consideration, two FIIT chips can be boresighted with a $ P
ASSUMPTIONS: A = A’, F F’,T = T’
offset. This doubles the horizontal sampling frequency and effectively eliminates aliasing in the horizontal direction.
Fig. 45 illustrates the tradeoffbetween aliasing and MTF
vice (no amplification or signal processing) is
[281. For the
conditions shown in Fig. 45(a)4c), the horiN , N yn e
zontal and vertical MTF’s [MTFH and MTFv1 at the respecZwg = tfield
tive Nyquist frequencies were [ 50 and 25 percent]for Fig.
where tfieid is the field time. The peak currentout of the 45(a), [35 and 15 percent] for Fig. 45(b), and [ 5 and 0 percent] for Fig. 4 % ~ ) .These conditions were achieved by using
device with onchip preamplifier is
an FIIT array with high MTF [Fig. 45(a)l and defocusing the
lens to simulate the prefiltered conditions [Fig. 45(b)and (c)] .
zp = negm
In Fig. 45(a),there is considerable high-frequency detail;
c
however, moire can be seen in the flag. It should be noted that
where gm is the transconductance of the onchip preamplifier, the moire in the flag has no effect on the remainder of the
C is the capacitanceon the output node of the CCD, and image, i.e., the effects of aliasing are limited to the extent of
NJVy is the number of elements read out in a field time. Then the object causing the aliasing. In Fig. 45(c) much of the highit follows that
frequency detail is lost; however, the moird is also not present.
These
pictures illustrate the nature
of the tradeoff between
c
zavg = NxNy
-MTF and aliasing. From this simulation, it is concluded that
ZP
tfield gm
the effects of aliasing are not as severe as might be predicted
from frequencydomain analysis. Since Fig. 45(a) corresponds
Combining (85), (88), and (76)gives
roughly to the FIIT design and Fig. 45(c) corresponds roughly
to the BIFT design, the results of the simulation provide some
qualitative insight into the tradeoffs between FIIT and BIFT
designs.
-
a
Thus S is the product of the area utilization faetor T)A,the
time
utilization
factor
qr, and the element
responsivity
Relement-
Table VI1 summarizes the FIIT versus BIFT tradeoffsin
terms of the “average-current” formulation. Again it is con-
B. The Charge-Injection Device (CID)
The charge-injection device (CID) is an MOS structurein
which surface-potential wells are created by means of external
voltages applied to anarray of gate electrodes1291. When
photons are absorbednear the potential wells, minority carriers
58
PROCEEDINGS OF THEIEEE, JANUARY 1975
(a)
(b)
(4
Fig. 45. Photographs showing CCD imagery. (a)Noncontiguoushorizontalintegrationcells.
(b) Simulated
contiguous horizontal integration cells. (c) Simulated overlapping horizontal integration cells.
v, = 0
P
;
0 0 0
----_---/'
1
DEPLETW REGION
0 e+
N-TYPE
P
--
Is ~INDICATKYIOF ELECTRON FLOW)
Fig. 46. Integration cell for charge-injection device (CID) showing the
collection of photon-generated holesin the potential well.
are collected in the wells, as shown in Fig. 46. The charge conconfiguration in the potential wells is a point-by-pointsampling
of the light falling on the image plane. Thus the integration
process in a CID is the same as that in a CCD.
For video signal readout, the charge stored in a potential well
is injected into the bulk at the end of the integration time by
removing the gate voltage, as shown in Fig. 47. These minority
carriers recombine at the substrate contact thereby causing a
current flow in the external circuit. The details of the current
flow during integration and readout are described in the following paragraphs.
As a drive voltage pulse is applied to thegate, a depletion region is formed, creating majority carriers, electrons in this
case,
flowing through the substrate. Becauseof capacitance coupling both positive and negative pulses of substrate current will
result in the waveform, shown in Fig. 48. During integration,
photongenerated minority carriers, holes in this case, will be
collected at the surface in the potential well and stored as
shown in Fig. 46, while the photongenerated electrons will
continuously flow through the substrate, as shown by the negative shaded area of the substrate current curve in Fig. 48. At
the end of the frame time, the injection of the stored charges
wiU increase the positive pulse height, as shown in the second
Fig. 47. Injection of the collected charge from the integration cell into
the substrateby collapsing the potential well.
I
No
VIDEO SIGNAL
VIDEO
SIGNAL
Fig. 48. CID output-currentwaveforms during integrationand W e
tion. Negative shaded area = positive shaded area = video d g d .
pulses of Fig. 48, which constitutes the desired video information. The integration of this current waveform results in a net
signal proportional to the injected video charge. The net voltage is sampled to provide the video output signal.
For two-dimensional CID arrays, the structure requires two
separate metal electrodes per unit cell, in order to scan the array elements in the x-y direction. The two-dimensional operation of this device is illustrated in Fig. 49. Each sensor element
consists of two separate electrodes for two storage capacitors.
BARBE:CHARGECOUPLED IMAGINGDEVICES
59
I
N-TYPE
Fig. 50.
Relative response versus wavelength for an FIIT area array.
TABLE VI11
AREA IMAGINGCHIPPARAMETERS
p”””
voy= 0
P
? ? %
N-TYPE
I
(4
Fig. 49. Basic cell of a CID areaarray. (a) Chargestorage. (b) Charge
transfer. (c) Charge injection.
One of the electrodes is connected to a horizontal access line,
the other toa vertical line.
Fig. 49(a) shows the normal charge storage in the potential
well; as the oneelectrode in the particular cell shown is turned
off, the stored charges under that electrode are transferred to
the other potential well, as shown in Fig. 49(b). The injection
of the stored charge in the particular sensor cell will occur only
when both electrode voltages are switched off, as demonstrated
in Fig. 49(c); therefore, asensor element is sampled only when
both the electrode voltages are removed from the sampling
cell.
The CID is simpler to fabricate than the CCD. The CID is
x-y addressed and therefore lends itself to random access. The
CCD readout is serial. The output capacitance of a CID is the
capacitance of one row and one column if all other rows and
columns are floated during the readout
of a givencell. The
output capacitance of a CCD is the capacitance of a reversebiased diode. Therefore, the process of reading out a CID is
noisier than that of reading out a CCD.
C. Further ZYadeoffs and State of the Art
Thereare other comparisons that can be made between
BIFT, F I R , and CID imaging a r r a y s . A thinned and backsidepassivated frame-transfer chip can be operated in the electronbombarded inducedanductivity (EBIC) mode. This provides
a preintegration gain; however, high voltages (in the kilovolt
range) are required. Also, it is not clear that a CCD can withstand bakeout in vacuum and long-tenn operation in vacuum
withoutdegradation.Theinterline-transfer
design is incompatible with backside-illumination or EBIC mode operation. It
isnot clear whether the CID will be efficient inthe EBIC mode
of operation dueto theconflicting constraints that high recombination is required at the backside of the chip for efficient
CID readout whereas low recombination is required for efficient collection of carriers generated by photoelectron absorption. The non-EBIC approach to low-light-levelimaging is
cooled buried-channel photonexcited arrayswith low-noise
amplifiers.
Another factor in comparing area arrays is the spectral response. The response of a backside photon-illuminated linear
device is shown in Fig. 31. The response of afrontsideilluminated interline-transfer area array is shown in Fig. 50.
The structure is caused by interference effects in the layered
frontside structure. The shape of the response can be altered
in the frontside-illuminated case by choice of layer thicknesses
during fabrication.
Most of the area arrays that have been fabricated are frontside illuminated, although Texas Instruments has imaged with
a backside-illuminated 64 by 64 array. Table VI11 summarizes
the area arraysthat have been fabricated.
D. Performance Predictions
In the noise-limited region, the noise-limited resolution R is
proportional to the elemental signal-to-noise ratio. Using the
“average-current” formulation,the signal is CHSA rinteg/e,
where C is the contrast. The photon noise is (HSA tinteg/e)1/2
and the total CCD noise is N . Then [2 1 I
R =K
CHSA tinteg/e
(HSA tinteg/e
+N2)lI2
*
It has been shown empirically with low-light-level imaging
tubes that patterns having barlengthsextending
over onethird of the picture height can be resolved at mean photoelec-
PROCEEDINGS OF THE IEEE, JANUARY 1975
60
CCI S = I5 mA/W
(FAIRCHILD
CCAID)
(CALCULATED)
lo-’
{R
* IO ELECTRONS
PHOTON LIMIT
0-5
----
Io4
0-3
2
Fig. 5 1. Calculated resolution versus irradiance for FITT array based on (91).
TA.4 25mm DIAGONALSENSOR;
2854
OK
{4 MA/W, I-SIT
RESPONSE 2 0 M A / W , CCI
INTENSIFIED SITCAMERA
Ti. 52. Actual
I-SITimagery versus simulated CCD imagery (with noisequivalent charge per pixel per frame = 10 electrons) at quarter-moon,
no moon (starlight). and overcast starlight conditions.
tron rates lower than 30 per second in a square resolutioncell
defined by the bar width.
Using this fact, together with the
condition that R = Rgeom when N = 0 and C = 1, gives K =
Rgeom. Thus (90) becomes
where Rgeom is the maximum resolution determined by the
geometry of the device. This equation can be used to predict
resolution versus irradiance curves for CCD’s. Using the values
S = 15 mAjW,
t b t e g = 1/30
S,
A = 6.45 * 10-lo m2
Rgeom = 20 line pairs (lp)/mm
gives the curves shown in Fig. 5 1 forcontrasts of 100,25, and
10 percent. The solid curves correspond to a total CCD noise
of 10 electrons per pixel per frame and the dashed curves correspond to photoelectron noise-limited performance] i.e., N =
0. This model is verified qualitatively by the CCD simulation
shownin Fig. 52. In the simdation, thesignaldo-noise ratio of
an I-SIT camera tube was controlled by adjusting the input irradiance and the gain to simulate a CCD having S = 20 mA/W
and N = 10. The upper three pictures of Fig. 5 2 show actual
ISIT imagery and the lower threepicturesshow
the CCD
simulation.
61
BARBE: CHARGECOUPLED IMAGINGDEVICES
IX.
RADIATION
EFFECTS
The effects of space radiation on CCD's are important because the CCD is ideal in terms of size, weight, and power for
space applications.
The CCD structures that have been evaluated include:1)
three-phase surface-channel structures with planar aluminum
electrodes [301; 2) two-phase stepped-oxide surface-channel
structures with polysilicon and aluminum electrodes [ 3 1 ] ;and
3) three-phaseburied-channelstructureswith
planar doped
polysilicon electrodes and undoped polysilicon interelectrode
isolation [32]. Device 1) is a 500element shift register, 2) is
64element shift register, and 3) is composed of 60 photosensitive cells and 2 readout registers. Each structure was evaluated
by irradiation with cobalt 60 gamma radiation and observed
for the effectson charge-transfer inefficiency, dark current,
and charge-handling capacity.
The 500element three-phase surface-channel structures with
planar aluminumelectrodes were irradiated while operating
as shift registers at a 1-MHz clock rate with no intentionally
introduced fat zero. The p-type substratewas held at - 7 V and
the clock-voltage swing was from -5 V to +5 V. The flat-band
voltage shift versus dose is shown in Fig. 53. . At lo3 rad, the
shift in flat-band voltage was sufficient to puse devices operated with an inputgate voltage set for 20-percent preirradiation fat zero to increase the bias charge to 100 percent of fullwell capacity. The transfer inefficiencyversus radiation dose is
shown in Fig. 54. Roughly an order-of-magnitude increase in
the transfer inefficiency was observed at 3 X lo4 rad with no
fat zero and also with 20-percent fat zero. Increasing the fat
zero from 20 to 40 percent at 3 X lo4 rad produced only a
small decrease intheinefficiency(2.8
X
to 2.3 X
The increased transfer inefficiency is attributed to increased
interface trapping. The
CV curves of the electrode-substrate
capacitance show severe distortion in addition to the flat-band
voltage shift.
Thefastinterface-statedensity,
as calculated from the
periodic-pulse technique, and the measured dark-current density are shown as a function of dose in Fig. 55. Note the increase in the fast interface-state density fromthe preirradiation
valueof
cm+(eV)-l to -10" cm+ (eV1-l at 3 X IO4
rad. An order-of-magnitude increase was also observed for the
dark current (14 nA/cmZ + 150 nA/cmZ). The gain of the onchip output amplifier began to degrade for total doses greater
than 10" rad. At lo5 rad,theoutput signal fora full-well
charge packet was <15 percent of its preirradiation value.
The 64element, surface-channel,stepped-oxidestructures
were operated as shift registers with a 1-MHz clock rate and a
fat zero (bias charge) of 20 percent of the full-well capacity.
In these devices, for total dose up to lo5 rad (Si), the primary
cause of changes in the CCD operation was a negative shift in
the flat-band voltage, witha larger shiftfor the polysilicon
gates than for the aluminum gates, as shown in Fig. 56. With
fixed applied voltages, the flat-band shifts cause 1) an increase
in the transfer inefficiency shownin Fig. 57 (from a preirradiation valueof lo4 to a valueof 4 X
after lo5 rad)due to
the cut-off of the fat-zero injection and 2) a
decrease in the
full-well capacity(down to 20 percent of the preirradiation
value after 3 X los rad) due to the modification of the surfacepotential profile shown in Fig. 58. By adjusting the operating
voltages to compensate for the flat-band shifts, preitradiation
transfer inefficiency and most of the preirradiation full-well
capacity were recovered for total doses up to lo5 rad. Improved schemes forfat-zeroinjection
have been devised to
-4-
in
9
-3-
W
a
in-
I
00
lo3
I
lo4
RADIATION DOSE RADS ( S I )
Fig. 53. Shift in flat-band voltage versus radiation dose for 500 X 1
aluminumelectrode n-channel planar-oxide surface-channel CCD
shift register.
.OS0
i
,045 040-
0 NO FAT ZERO
/
0 2 0 % FAT ZERO
0351
I
0
1o3
10'
RADIATION DOSE RADS ( S i )
10'
Fig. 54. Transfer inefficiency versus radiation dose for three-phase
500 X 1 aluminumelectrode n-channel planar-oxide surface-channel
CCD shift register.
12,
1
?
I150
171
0 4 1
0
1
lo3
10'
1
1
3
25
Io
IO'
RADIATION DOSE RADS (Si)
Fig. 55. Interfacestate density (determined from periodic-pulse measurements) and dark currentversus radiation dose for aluminumelectrode nthannel planar-oxide surface-channel CCD shift register.
eliminate the problemof fat-zero cutoff dueto flat-band shifts.
At a total dose of 3 X lo5 rad, however, the formation of
interface states (measured by the periodic-pulse method) results in an increase in the transfer inefficiency and an increase
62
JANUARY 1975
IEEE,
PROCEEDINGS OF THE
90
-
UNIRRAOIATEDVALUES
JD = 3.8 NA/CMz
--9
--8
5
-$
--7
I
--s;
--5 a
5
--4
52
0
--3 f
m
--2
ij
IL
--I
I
RADIATION
Fig. 56. Shift in flat-band voltage u
s n d i r t b n dose for two-phase
64 X 1 steppadoxide p-channdrurface-chumel CCD ahift rag&ter.
Fig. 59. Flat-band voltage shift and dark-current density versus radiationdosefor
three-phase 60clementburied-channel
imager with
doped polysilicon electrodes and undoped polysilicon interelectrode
isolation.
TRANSFER
GATE
VERTICAL
REGISTER GATE
IMAGING GATE
2
4
DOSE
6
X
8
IO
I2
IO-^ RADS
Fig. 57. Transferinefficiency versus radiation dose for stepped-oxide
p c h a n n d surface-channel CCD shift register.
q
(4
Fig. 60. CCD doped polysilicon electrodeandundoped
polysilicon
interelectrode CCD structure
and
potential
profiles. (a) Crosssectional n e w of gate structure. (b) Reirradiation
profileof minimumchannelpotential.(c)Roffieofminimumchannelpotential
after 3 X lo' rad.
TABLE IX
FAILURE
MODES O F CCD's IN
-
s" 12
RADIATION
ENVIRONMENT
64 STAGE TWO-pIIlsE SURFACECHANNEL SHIFT REGISTER
FAT-ZERO CUTOFF
l-+J-lq
wx
( 4 0 ' RADS)
REDUCTION IN NU-WEU
CAPACITY (3 X 10' RADS)
60 STAGE THREE-PHASE BURIEDCHANNEL LINE IMAGER
16
-
1
W S E RADS (Si)
UNDOPEO
PoLYSlLlCoN
0
I
BURIEDCHANNEL DRIVEN
DEpLmow
@I
OVT OF
(>lo4
m
r
$:
RIDS)
C H I l l N E U m i I N THE M
D POLVSIUCDN
INTERELECTROO€ ISOLATION REGIONS
(=-lo' RADS)
$8
500 STAGE lllREL-PlWSESURFACE-CMANNEL SHIFT REGISTER
(4
Fig.58. Stepped-oxide structureandsurface-potential
profiles.
Cross-sectional view ofthestructure.(b)Reirradiationsurfacepotential profile. (c) Surface-potential proffie after 3 X 10' rad.
FAT-ZERO SATURATION
OAMR
(a)
OF MAGNITUDE INCREASE IN c
(<I X 103 RADS)
(3
X
104 RADS)
@D% REDUCTION IN OUTPUT AMPLIFIER
GAIN
1105 RADS)
BARBE: CHARGECOUPLED IMAGING DEVICES
in the dark current which cannot be compensated for by adjusting the operating voltages.
The 60element buried-channel structures, with doped polysilicon electrodes
and
undoped
polysilicon interelectrode
isolation, were operated as optical imagers with a 60-bit photosensitive region, two 30-bit vertical registers, and a 2-bit horizontal register. The device structure is shown in Fig. 29. The
vertical registers were operated at a 250-kHz clock rate and the
horizontal register at a 500-Wz rate.Inthese
devices, for
total dose up to 104 rad, the transferinefficiency remains
nearly constant at the preirradiation value of10".
The dark
current and the flat-band voltage shift are shown as a function
of dose in Fig. 59. At a total dose of 3 X 104 rad, the devices
were inoperative due to two effects. The first effect was that
theflat-band voltage shift became large enough so that the
original buried-chhnel drain biaswas insufficient to deplete
thechannelcompletely.
This problem was corrected by increasing the drain bias voltage. The second effect was a reduction in the resistance of the undoped polysilicon isolating regions by a factor of 20. This drop in the isolation resistance
allowed a mixing of the various clock voltages, the net effect
being that almost no potential barrier could be formed to store
photogenerated charge under the imaging gates. This situation
is shown in Fig. 60. The failure of the isolation was due to induced channeling in the undopedpolysilicon as aresult of
trapped positive chargein the oxide. Altering the applied
voltages could notcorrectthisproblem,
leaving the devices
functionallyinoperativeat3
X 10" rad. Anydevicesusing
undoped polysilicon forisolation regions could potentially
suffer from this failure mechanism. Table IX summarizes the
radiation failure modes determined for the three CCD designs
tested.Recommendationsforahardened
design shouldinclude the following. 1) Use a buried-channel structure, which
eliminates fat zero and interface-state trapping. The n-channel
reduces A VFB. 2) Use a planar insulator and a single gate material. 3) Avoid undoped polysilicon isolation. 4) Control SUIface potential between gates.
63
Fie.61.
Schematic diagram of the uae of a rilicon CCD t o multiplex an
IR detection array.
IMAGE
M
o
m
-u,
CHARGE W S F E R
--.c Va
Fa. 62.
Schematic diagram of the use of a rilicon CCD array to provide
TDI for an IR detector array.
injecting into alternate CCD cells reduces the interchannel
crosstalk at the CCD output by thefactor
[ 2 / ( N - 111
[( 1 - a)/al compared with the interchannel crosstalk when
the signal is iqjected into each cell. For N = 100 and a = 104,
this factor is 200. The larger problem is to introduce charge
intothe CCD in response to low-levelvoltages.
Since the
input signal is a voltage, it is the noise voltage (kT/c~.p~)"'
which must be minimized. This requires that CI-N should be
large.
X. INFRARED DEVICES
Thetime delay andintegration(TDI)implementation
is
There are basically three ways in which the chargecoupled
shownin Fig. 62. TDI is achieved by making a 1:l interconcept can beused ininfrared imaging. 1)A silicon CCD connectionbetween each detectorelement and the correcan be used to multiplex an array of IR detectors, 2) a silicon sponding CCD element via theappropriate low-noise input
CCD can be used to provide time delay and integration for circuits. The charge injected into a CCD cell at a given point
an array of IR detectors, and 3) a CCD or CID can possibly is proportional to the detector output voltage. Thetransfer
be fabricated in IR-sensitive semiconductors to provide mono- of a charge packet along the CCD is synchronous with the
velocity VQ of thecorrespondingpointin
the image plane
lithic infrared chargecoupleddevices (IRCCD's).
Themultiplexerimplementation is shown in Fig. 61. The along the detector column. Thus the effective integration is
output of the detectors is a voltage. Once per line time, the M times longer thanthesingledetectorintegrationtime,
CCD, via the capacitively coupled input circuits, samples the where M is the number of detectors in the column. For an
detectoroutput voltages, obtains charge in each CCD cell N-column by Melement image plane, the number of interproportional tothe correspondingdetector output voltage, connectionsbetweenthedetectorarrayand
the CCD array
and shifts this charge configurationout.Theobject
of this is M times N. Reliable fabrication of this large number of
approach is to performthemultiplexingwithinthe
dewar interconnections is a major concern for this approach [ 341
with the least amount of power dissipation. In this way, the
The third approach is monolithic IRCCD, where the CCD
number of leads from the dewar to the outside world will be or the CID is fabricated in a narrow-bandgap semiconductor.
minimized and the heat load will be minimized. Thereare
The major problems with this approach are that 1) MOS techtwoproblems associated with this approach-crosstalk be- nologies insuitablesemiconductorsare
not well developed,
tween channels at the CCD output due to transfer inefficiency, 2) the high-background photon flux in the IR saturates storand the low-noise injection of charge packets into the CCD age cells quickly, and 3) the combination of high-background
which are proportional in charge to the voltage at the output photonflux and low contrast imposes severe limitsonthe
of the detectors [33]. The crosstalk problem is largely solved tolerableamount of nonuniformity of response (from cell
by injecting into alternate CCD cells instead of injecting to cell). Each of these problems will be discussed more fully
into each CCDcell. Equation (24) can be used to show that in the following paragraphs.
.
IEEE,
PROCEEDINGS OF THE
64
JANUARY 1975
Some progress has been made inthedevelopment
of an
MOS technologyinInSb using deposited silicon oxynitride
as theinsulatorandnichrome
as the metal. Storage times
(withnoexcitation)
of 0.1 s at 77 K andinterface-state
densities of.10'' cm-' (eV)-' have been reported [ 351.
The full-well capacity (in carrierlcm') of an MOS capacitor
is approximately given by
Cox
Vde.
Nmax
SAMPLE PULSE
(92)
Using Cox = 3.5 X lo-' F/cm' and VG = 2 V, Nmax = 2 X
10'' carrierlcm' If the photon flux is 6 X lOI4 photon/cm2
s, then the well will fill in 3 ms. Thus the MOS cell (CCD or
CID) is limited to short integration times for wide-band thermal imaging due to thefinitestoragecapacity.The
most
fundamental problem with the useof
an integrating-type
sensor in the IRis the nonuniformity problem. If the elementtoelement fractionalnonuniformity of response in an integrating array is A R , and if the background flux is FB and
the Scene contrast is C, then the number of carriers NT collected in thecells after integrating fortinteg seconds is
HOLD
-
.
NOSTORACE
CHARGE
STMUQ
Fig. 63. Charge-injection operation of InSb MIS structure.
GATE PULSE
RESET
PULSE
SA"
PULSE
CHOPPER
NT = (R + AR) FB(1 + C ) tinteg
= RFBtinteg
(a)
WAVE
ANALYZER
+ RFBCtintcg + ARFBtinteg.
(b)
(C)
Term (a) is a constant number of carriers in each cell and has
noeffectotherthan
using dynamic range. Term (b) is the
desired signal. Term (c) is the cell-to-cell variationinthe
number of carrierscollecteddue to spatialnonuniformities
in response. When (c) is larger than (b), the signal will not
be detectable. ,For example, in the 3-S-pm range, the contrast is 3.7 percent/K.Thus,inorder
to detectatemperature differential of 1 K, the maximum nonuniformity tolerable is 3.7 percent. This imposes severe constraints on material
homogeneity and photolithographic tolerances.
Figs. 63-69 illustrate recent results from a
singleCID cell
fabricated in InSb [361. Fig. 63 shows the CID readout and
signal
processing
circuit.
The
substrate
current
is fed
into
an integrator and the two current pulses are integrated during
the chargeinjection period. Thefinal value of the signal
voltage is amplified and then sampled and held. Finally, the
integrator is reset to zerofor the nextperiod.Theoptical
measurement setup is shown in Fig. 64. The blackbody temperature is 5 0 0 K representing the signal and the background
temperature is 300 K. Fig. 65 shows the output signal as a
function of integrationtime.The
output voltage is a linear
'function of integration time up to saturation. Fig. 66 shows
the output voltage versus blackbody irradiance, and Fig. 67
g i v e s dataonthe
samedevice with narrow-band excitation
(Xo = 4.5 pm, Ah = 0.2 pm).
The
sensitivity is approximately
a factor of 3 lower than BLIP.
Fig. 68 shows thesaturationcharacteristic
of the device.
The saturation corresponds closely to the calculated value of
2 X 10"cm-'.
Finally, Fig. 69 shows the measured spectral
response of the CID cell.
It is concluded that InSb MOS structures can be operated
in theintegration mode via the CID implementationwith
values of D* approaching the BLIP limit.
A scheme for background charge rejection can be used to
skim offthe signal Q, fromthe background QB anddump
the background charge subsequently by injecting it into the
substrate. Such acircuit is shownin Fig. 70. Theleft well
is photosensitive and collects charge. The barrier
is con-
DEVICE AT 77%
SCOPE
BUCKBODY
0
SOURCE
RWVEO
2
m
wlm
2
-
>
SOURCE
1 mrlDlV
Fig. 64. Block diagram of experimental apparatus to test the InSb CID
structure.
lo3 L_
P
"
IO'
CHARCE INTEGRATIONTIME ISECONDSI
Fig. 65. Output voltage vmus integration time for InSb CID cell with
1.4 X
lo-* W input power from 500 K blackbody.
trolled by the voltage on the center electrode and is set to the
level corresponding to the background charge Q B . Therefore,
any signal charge in exof QB will spill into the right well.
The charge remaining in the left well, Q B , can be extracted
by injecting it into the substrate or by transferring it to a
drain region. The charge remaining in the right well is Q,.
This technique can be used to reduce the dynamic range r e
DEVICES
BARBE: CHARGECOUPLED IMAGING
65
10-1
-
N-TYPE I n 9
-
Y a ° K BLACKBODY
FOV
1c3-
e-
I
I
c
lND= 1013cm-31
-- MO
-
A~ = 2 x 1o-jcm2
-
TI = Bps
I
N-TYPE lnSb
d
NARROW BAND
1
INPUT PHOTON FLUX DENSITY lPHOTOfdS/SEC m 2 1
Fig. 68. Output voltage versus input photonflux
density showing
saturation level.
1o-811
109
I
l
10.8
I
1
l
lo-'
(
I
10-6
1
1
I
J
los5
INPUT SIGNAL IRRADIANCE IWATTSbmZ)
Fig. 66. Output voltage versus wide-band input irradiance for InSb CID
cell.
WAVELENGTH (pml
Fig. 69. Relative spectral response of InSb CID cell.
9s
Fig. 70. Schematic diagram of background rejection or antibloom
circuit.
INPUT SIGNAL IRRADIANCE (WATTSkm21
Fig. 67. Output voltage versus narrow-band (0.2 pm at A, = 4.5 pm)
irradiance for InSb CID cell.
quired of the amplifier. The same structure can be used in a
slightly different way to provide antiblooming and exposure
control.
XI. CONCLUSIONS
From the survey of CCD technology and design presented
here, the following general conclusions can be drawn.
1) Buried-channel CCD's have been shown to be superior
to surface-channel CCD's interms of transferinefficiency,
spatial and temporal noise, and speed. Some sacrifice of
charge-handling capacity is made to achieve speeds in excess
of 20 MHz.
2) The CCD is unique in that signal charge can besensed
nondestructively.This
makes ultralow-noise signal amplification via distributed amplifiers possible.
3) Long linear arrays in excess of 1700 elements have been
fabricated and evaluated. Such devices are viable candidates
for document reading and surveillance applications.
4) Area arrays having approximately halfof conventional
TV resolution have been fabricated. The fabrication of large
arrays having full TV resolution appearsto be feasible.
66
PROCEEDINGS OF THE IEEE, JANUARY 1975
5) The CCD concept is especially useful for the TDI function; the CID concept is especially useful for applications requiring random accessibility.
6) Cooled (- SOOC), frontside-illuminated, photonexcited
area arrays havingNES’sof
Q 10electrons appear to be
achievable. The performance of such arrays would approach
that of photoelectronexcited arrays of equal area.
7) The use of two boresighted interline-transfer area arrays
with 3P horizontaloptical offset and 3 T electrical offset
appears to be a practical technique for increasing the horizontal sampling density in the focal plane, thereby increasing
the responsivity by a factor of 2 and decreasing the susceptibility to aliasing.
8) The useofsiliconCCD’s
at 77 K for focal-plane signal
processing (TDI and multiplexing) of informationfrom IR
detector arrays has been demonstrated. The key problem
in these approaches is associated with the interface between
the IR detector arrays and the CCD arrays.
9) The primary effects of ionizing radiation are the shift
in flat-band voltage and the increase in interface-state density.
Buried-channel CCD’s havingplanar oxides and overlapping
electrodes would appear to be the least susceptible to totaldose ionizing radiation environments.
10) The basic operation of the InSb CID has been demonstrated.The simplicity of this approach makes it attractive
for low-background applications. The key problem with the
useof
this device for high-background applications is the
severe restriction on the allowable nonuniformity of response
from element to element when the device is used in the integrating mode. Therefore, InSb CID arrays are best utilized
when used in a scanned mode.
APPENDIX
NOISE CORRELATIONTIME FOR RC CIRCUIT
Consider an RC circuit with charge Q on the capacitor. The
differential equation (A-1) completely determines the response
of the circuit to any forcing function e ( t ) .
grations, gives
Q(t)’ = kTC( 1 -
and it follows that
Thus the correlation time is 3 R C .
ACKNOWLEDGMENT
Theauthor wishes to thank L. W. Sumney of the Naval
Electronics Systems Command, S. B. Campana of the Naval
Air Development Center, and W. D. Baker, J. M. Killiany,
N. S. Saks, and J. Freeman of the Naval Research Laboratory
for many helpful discussions.
REFERENCES
[9]
[ 101
[ 11 1
[ 121
This equation can be rewrittenas
[ 131
(141
Then
[ 151
[ 161
and
[ 171
1
= Q(t)2 = T e - 2 r / R C
R
( Q ( t )-
[ 181
1‘IT
[ 191
(e(T1) e ( r 2 ) )e(T1+Tl)/RCd r l d r 2 . (A-4)
[20]
If e ( t ) is white noise arising from the thermal fluctuations of
the resistor, then
[Zl ]
*
( e ( r 1 ) e(T2 1) = 2 k T R 6 ( ~-~r21.
(221
(A-5)
Making this substitution into (A*), and performing the inte-
-
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Lett.,
Appliiat’bn of Charge-Coupled Devices to Infrared
Ab;mrret-A review of infrued sensitive chuBpcoupled device8
and semianalog memories, communications
and
signal
processing.
In this paper we explore a relatively new area of applications
the o r i g i d CCD concept into the IR Monolithic IRCCD’r discusaed for CCD’s andconcepts: infrared detectionand imaging. A
include invedon-mode devices (with lurrow budgrp semiconductor variety of infrared CCD’s (IRCCD’s) which have been explored
substrate), rcaunultion-mode devices (extrinsic wide brndlpp semi- or proposed fall intotwo maincategories:
monolithic and
conductor substrate), and Schottky-bauk devices (internal photo- hybrid devices.
miscion). b) Hybrid devices, in whicb the functions of detection and
The monolithic IRCCD concept generally uses the standard
s @ d processing are performed in separate but integmtable comstructure with the substrate consisting of a narrow bandp o n e n t s b y . n . m y o f I R d e t e c ~ s m d a s i l i c o n C C D ~ t CCD
~
unit. Hybrid IRCCD’s discusaed indude both direct injection devices gap or an extrinsic semiconductor sensitive to IRradiation
(in conjunction with photovdbic IR detectors) d indirect injection [ 21, [ 31. Other monolithic IRCCD devices being investigated
deviea (inconjunction with pyroelectric and photoconductive devices). combine a Schottky-barrierinternal
photoemission sensing
array in conjunction with a CCD readout structure [ 4 ] . It is
I. INTRODUCTION
important to note that the extrinsic semiconductor substrate
INCE the invention of chargecoupled devices (CCD’s) by IRCCDis the only one operating in the accumulation mode
Boyle and Smith [ 11 in 1970, the remarkable versatility (AMCCD) and using majority carrier transport, while the other
of this class of devices has led to their application in a monolithic IRCCD’s are depletion-mode devices.
diverse number offields.
These applications include visibleBy contrast to the monolithic IRCCD, the hybrid versions
light imagers (e.g., TV cameras, optical characterreader), digital consist of the coupling of anyone of various types of IR
photodetectors to a silicon CCD shift-register unit. In the
hybrid structure, the functionsof detection and signal processManuscript received August 12, 1974; revised August 15;1974. Portions of this paper were presented at the International Conference on
ing areperformed in distinctbut integratable components.
theTechnologyandApplicationsofChargeCoupled
Devices, EdinThe role of the silicon CCD in this case is that of a signal
burgh, Scotland, September 25-27, 1974.
processor performing appropriate functions, such as multiplexA. I . Steckl, R. D. Neison, B. T. French, and R. A. Gudmundsen are
with Electronics Research Division, Rockwell International, Anaheim,
ing, amplification, correlation,delay-and-add, etc. The category
Calif. 92803.
of hybrid IRCCD’s can be further subdivided into two subD. Schechter is withtheDepartmentofPhysics-Astronomy,
California State University,Long Beach, Calif. 90840.
classes: direct andindirectinjection devices. Intheformer,
(IRCCD) is presented. Opezatiorrrl requirements of typiat IRCCD
rpplicrtionr are briefly introduced IRCCD devices are divided into
two major ategorier: a) Mondithic depias, which easentirtly extend
s