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ARITHMATIC FOR COMPUTERS
The maximum number that a 32 bit register can hold is:
232  1 = 4, 294, 967, 295.
ASCII vs Binary numbers
1. Less bits is needed to represent a number using binary than
ASCII . If ASCII code is used to represent the above number
10 bytes is required, since it has 10 digits and each digit
requires one byte to be coded using ASCII.
2. Easy to handle using binary. This is not the case using
ASCII.
Signed and unsigned numbers
There are two approaches to represent signed numbers:
1. Signed and magnitude approach (old approach). The most
significant bit is reserved for sign (0 for +ive numbers &1
for –ive numbers).
Example
The number -5 is represented using sign and magnitude in
8 bits register as follows:
-5=
1
0
0
0
0
1
0
1
+5=
0
0
0
0
0
1
0
1
2. Two’s complement approach (new approach): The 2’s
complement of a number is achieved by adding 1 to the
1’s complement. The 1’s complement is achieved by
inverting every 0 to 1 and every 1 to 0.
Example
The number -5 is represented using sign and magnitude in
8 bits register as follows:
-5=
1
1
1
1
1
0
1
1
+5=
0
0
0
0
0
1
0
1
5= 00000101
1’s for 5 = 11111010
+
1
11111011= -5 in 2’s complement
The value of a 2’s complement number in expanding
form is:
N  a7 27  a6 26  a5 25  a4 24  a3 23  a2 22  a1 21  a0 20
So, the value of the above 8 bit register is:
N  27  1* 26  1* 25  1* 24  1* 23  0 * 22  1* 21  1* 20
N = -128 + 64 + 32 + 16 + 8 + 8 + 0 + 2 + 1=-128+123=-5
Note: Every computer today use 2’s complement binary
representations for signed numbers, because it simplifies the
hardware design.
C=A-B= A+(-B)=A+[2’s complement(B)]
The subtraction of a number has been changed to addition to
it’s 2’s complement. Therefore, using 2’s complement approach
will eliminate the need for subtraction hardware.
Example:
7-3=7+ (-3) =7+ [2’s complement of 3]
Therefore,
1. Find the 2’s complement for 3:
3 = 00000011
1’s for 3 = 11111100
+
1
11111101 = -3 [2’s comp. for 3]
2. Add it to 7:
00000111
+11111101
00000100 = 4
Remember:
X  X 1  0
X 1   X
Example
let X=3
3
+
-3
0
00000011
+
11111101
00000000
Two’s complement representation
Using 2’s complement approach for signed numbers, the 32
bit registers will hold:
00000000000000000000000000000000
00000000000000000000000000000001
00000000000000000000000000000010
00000000000000000000000000000011
00000000000000000000000000000100
.
.
.
01111111111111111111111111111110
01111111111111111111111111111111
=0
=1
=2
=3
=4
= 231  2
= 231  1 max
10000000000000000000000000000000 =  2
31
min
10000000000000000000000000000001 =  2  1
31
10000000000000000000000000000010 =  2  2
31
10000000000000000000000000000011
.
.
.
11111111111111111111111111111100
11111111111111111111111111111101
11111111111111111111111111111110
11111111111111111111111111111111
=2 3
31
=-4
=-3
=-2
=-1
Load byte (lb)
Lb instruction treats the byte as a signed number. Since there
are 32 bits in the register, sign extension must be applied in order
to save the right value for the signed number.
Example
Lb $t0, 0($s1)
00001111
$s1
10000101
10101010
$t0
11111111
11111111
11111111
10000101
Load byte unsigned (lbu)
Lbu instruction treats the byte as unsigned number.
Example
Lbu $t0, 0($s1)
$t0
00000000
00000000
00000000
10000101
Note
There are slt, slti, sltu, and sltiu instructions in MIPS.
Assume that $s0, and $s1 carry:
$s0
11111111
11111111
11111111
11111111
$s1
00000000
00000000
00000000
11111111
Slt
Sltu
Slti
Sltiu
$t0, $s0, $s1
$t0, $s0, $s1
$t0, $s0, 2
$t0, $s0, 2
$s0= -1 , $s1=255
32
$s0= 2 , $s1=255
$s0= -1 , $s0 < 2
32
$s0= 2 , $s0 > 2
$t0=1
$t0=0
$t0=1
$t0=0
Sign extension
To add the immediate field to a 32 bit register, the machine
must convert that 16-bit number to its 32-bit equivalent. This is
done by replication of the sign bit to fill the new bits of the larger
quantity
Addi $t0, $s1, -5
???
$s1
$t0
1111111111111011
$s1=15
0000000000000000 0000000000001111
-5
1111111111111111 1111111111111011
$t0=10
0000000000000000 0000000000001010
Note: Since the offset field (of the I-type instruction) is 16-bits,
The maximum value the offset field can have is 215  1 =32,767.
The minimum value the offset field can have is  215 = -32,768.
Overflow
Arithmetic operation creates result that is too large to fit in a
fixed word size.
Overflow occurs if:
1. Addition of +ive number to a +ive number and the results
is –ive number. A≥0, and B≥0, while (A+B)<0.
Assume we have a 4-bit register. The maximum
number that the register can hold is 2 3  1 =7, and the
minimum number is  23 =-8. So when the result is out of
the above range we will have overflow.
Example: 2+7 must be 9. But 9 is out of the range of a 4bit register. Therefore overflow will occur.
Paper and pencil
2
7
+ ----
9
Computer 2=
0
0
1
0
7=
0
1
1
1
1
0
0
1
+
=-7
Using 2’s complement to represent a signed number,
1001=-1*8+0*4+0*2+1*1
=-7≠9
since 2>0, and 7>0, while -7<0 overflow will be
detected.
2. Addition of -ive number to a -ive number and the results is
+ive nuber. A<0, and B<0, while (A+B)≥0.
Example: (-2)+(-7) must be -9. But -9 is out of the
range of a 4-bit register. Therefore overflow will occur.
Paper and pencil
-2
-7
+ ---9
Computer
2=
1’s complement
0
0
1
0
1
1
0
1
7=
1’s complement
0
1
1
1
1
0
0
0
1
+
2’s complement
1
+
1
1
1
0
=-2 2’s complement
1
0
0
1
=-7
-2=
1
1
1
0
-7=
1
0
0
1
0
1
1
1
+
=7
3. Subtraction of +ive number from a -ive number and the
results is -ive number. A>0, and B<0, while (A-B)≤0.
Example: 2-(-7) must be 9. But 9 is out of the range of a 4bit register. Therefore overflow will occur.
Paper and pencil
2
-7
- --9
Computer
2-(-7)=2-(2’s comp.7)=2+2’s comp.(2’scomp.7)=2+7=9
Note: 2’complement (X) =-X
2’s complement (2’complement (X)) =X
7=
1’s complement
0
1
1
1
1
0
0
0
-7=
1’s complement
1
1
0
0
0
1
1
1
0
1
1
+
2’s complement
+
1
0
0
0
1
2=
0
0
1
0
7=
0
1
1
1
1
0
0
1
= -7
+
=-7
2’s complement
0
1
1
1
=7
4. Subtraction of -ive number from a +ive number and the
results is +ive number. A<0, and B>0, while (A-B)≥0.
Example: (-2)-7 must be -9. But -9 is out of the range of a
4-bit register. Therefore overflow will occur.
Paper and pencil
-2
7
- --5
Computer
2=
1’s complement
0
1
0
1
1
1
0
0
1
7=
1’s complement
0
1
1
1
1
1
0
0
0
1
1
+
2’s complement
+
1
1
0
1
0
-2=
0
0
1
0
-7=
1
0
0
1
1
0
1
1
= -2
+
=-5
2’s complement
1
0
0
1
= -7
Logical operations
Shift lift logical (sll)
Shift right logical (srl)
These instructions are R-type.
Example:
Sll $t2, $s0,8
???
$s0
0
$t2
8
????
$s0
00000000
00000000
11110000
11001100
$t2
00000000
11110000
11001100
00000000
sll $t2, $t1, 1 # Shifts left logical
When we shift left logically we add zeros to the right
and the leftmost bit drops off the edge.
sllv (shift left logical variable) is the same except
the last operand is a register (shift amount)
instead of an immediate.
Shift Amount is the 5 least significant bits of the
register as an unsigned integer.
srl and srlv (shift right logical) is the same
concept.
sra (shift right arithmetic) is like srl except the left
is filled with the sign extension instead of
zero. There also exists a srav.
Logical and
and $t0, $t1, $t2
The layout of this instruction is:
???
$t1
$t2
$t0
0
????
$t1
00000000
11111111
10101010
01010101
$t2
11111111
11111111
01010101
01010101
$t0
00000000
11111111
00000000
01010101
Logical or
or $t0, $t1, $t2
The layout of this instruction is:
???
$t1
$t2
$t0
0
????
$t1
00000000
11111111
10101010
01010101
$t2
11111111
11111111
01010101
01010101
$t0
11111111
11111111
11111111
10101010
We have also and immediate (andi) & or immediate ( ori):
andi $t0, $t1, 100
ori $t0, $t1, 100
As you know these two instructions are I-type.
Construction an arithmetic logic unit
Firs of all we have to build the full adder. To do this we have
to to do the following steps:
STEP1: Construct the truth table for the full adder from our
knowledge of binary addition:
a
0
0
0
0
1
1
1
1
INPUT
b
Carry in
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
OUTPUT
Sum Carry out
0
0
1
0
1
0
0
1
1
0
0
1
0
1
1
1
STEP2: Derive the Boolian function for Sum and for Carry
out from the above truth table;
Sum  a .b .c  a .b.c  a.b .c  a.b.c
Carry out  a.b.c  a.b c.  a.b.c  a.b.c
Note: c is for carry in
STEP3: Simplify these two functions using Karnoaph map;
a- The sum function;
ab
00
0
0
01
1
1
1
0
c
11
0
10
1
1
0
Unfortunately, it is not possible to simplify the sum
function. So, it will stay as it is.
Sum  a .b .c  a .b.c  a.b .c  a.b.c
b- The carry out function;
ab
ab
00
0
0
01
0
1
0
1
c
bc
11
1
10
0
1
1
ac
So, the carryout function is simplified to;
Carry out  a.b  a.c  b.c
STEP3: Construct the logic circuit for Sum and Carry out
using the simplified Boolian functions;
a
b
c
Su
Sum
m
Carry out
out
Now we will assign a universal symbol for the above
full adder logic circuit to avoid repeat it every time we
assigned to it
a
b
c
+
Sum
Carry out
Now we can add to the circuit the logical “and”, “or”, &
“sub” instructions. The “and”, & “or” instructions are straight
forward, just connect the AND gate & OR gate with the input a &
b. However, Subtractions can be performed using 2's complement
and a 2:1 Mux. To compute 2's complement the carrayIn of the
LSB (Least Significant Bit) is set to 1.
A 1-bit ALU that performs and, or, addition and subtraction
NOTE: Using 2’s complement approach to represent signed
number simplifies the design, since only an inverter and a 2-to-1
multiplexer is needed to use the adder for subtraction instead of
building it as we did for the adder. That is why every computer
nowadays uses 2’s complement approach to represent signed
numbers.
Now we will assign a universal symbol for the above single
bit Arithmetic Logic Unit (1-bit ALU) to avoid repeat it every
time we assigned to it,
a
b
c
One bit
ALU
Result
Carry out
overflow
Tailoring the ALU to the MIPS (A 32-bit ALU)
Up to now we have built a single bit ALU ( that can perform
add, sub, and, & or instructions). Building an ALU with 32-bits is
done simply by tailoring 32 single-bit ALU as follows;