Download BJT Incremental Parameter Equivalent Circuit

BJT Incremental Parameter Equivalent Circuit
ObjectiveThe PWL linearized approximation to device characteristics is
necessarily coarse in many respects, applying as it ordinarily does over a wide
range of device operation. There are circumstances, however, in which only
small (incremental) deviations are made from a steady-state operating point, and
in these circumstances a model can be developed which is more finely
representative of local device operation. The objective here is the description of
the hybrid-π incremental parameter BJT model for operation in the normal
mode. The initial discussion is for the static model; additional components to
include BJT internal dynamics are presented later.
Introduction
The forward-bias portion of a semiconductor diode characteristic is sketched in the figure below (left).
Previously, to simplify (hand) analysis of diode circuits the diode is replaced by a piecewise linear
equivalent circuit. A point to note here is that the PWL diode model approximated diode behavior over
both forward- and reverse-biased ranges of operation. For the present purpose interest is limited to a small
range of forward-bias operation around a specific central operating point Q. This is suggested in the figure
by enclosing the pertinent part of the characteristics within a circle.
Because the operating range is limited the
model we use for the diode within this
limited range need not be particularly
accurate outside this range. We can trade off
inaccuracy of the model outside the specified
range of operation for increased accuracy of
representation within the range. Thus given
I = f(V) expand I in a Taylor series about the
Q point; the linear term is shown on the right
of the figure. To the extent that the range of
variation is small enough the series may be
truncated at the linear term. This
corresponds geometrically to approximating
the actual characteristic by a tangent at the Q
point (see figure).
Use the theoretical diode volt-ampere relation I = Io (e qV/kT - 1), ≈ Io eqV/kT for forward-bias
operation above the 'knee' to evaluate re = ∂ I/∂V at IQ and determine that re = kT/qIQ. The emission
parameter N is omitted for simplicity; this parameter is roughly 1.
Now go one step further. Since the actual diode is to be replaced by the linearized model (valid with a
limited range of operation) then within the range of validity the circuit is linear. Hence superposition may
be applied to separate a diode circuit analysis into two parts; a steady-state calculation to determine the Q
point (IQ, VQ) and an incremental part relating the incremental changes i and v.
Separation of the analysis in this fashion can be quite convenient. Note, for example, that it is not
necessary that the same diode model be used for both parts of the analysis. Indeed the steady-state
analysis need not use a linearized model at all. The only connection between the two in this separation is
the appearance of the Q-point current in the incremental diode circuit parameter re.
Bipolar Transistor Incremental Parameter Model
A sophisticated model for incremental variations of transistor currents and voltages, rather more involved
than the diode model, also can be derived. Here a widely used first-order model, the ‘hybrid π ‘ simply is
asserted and discussed. The model terminal volt-ampere relations simply express the linearization of the
incremental parameter analysis. What is less obvious is the relationship between the model coefficients
Introductory Electronics Notes
The University of Michigan-Dearborn
50-1
Copyright © M H Miller: 2000
revised
and transistor physical phenomena. We do not derive the model here because doing so takes us too far
afield of the purpose of these notes; the objective here is familiarization. The model as it is presented here
actually is incomplete; for example it assumes that carrier transport delays in traveling across the transistor
can be ignored. We will return to this matter latter, adding appropriate components to the model to take
account of the delays.
The hybrid-π model is drawn to the right. Keep in mind that
lower case characters used for the terminal currents and
voltages represent changes in current and voltage from Q
point values. The transistor is assumed to be operating in
normal forward active mode, i.e., emitter junction forwardbiased and collector junction reverse-biased. Although
sophisticated and conceptually helpful in a number of
respects, the model is of limited use. Numerical calculations, even incremental-parameter calculations,
generally are better done on a computer using a more accurate nonlinear model. Hand calculations are
another matter.
Linearized models generally are particularly helpful in two ways. They can for example, provide analytic
relationships usefully describing the relative importance of various circuit parameters. However analysis
of an involved circuit obscures such relations to a point where they are of little use. The resistance rbc, for
example, corresponds to a second order effect which inevitably appears formally in complex algebraic
expressions but rarely has a significant numerical consequence. A second way linearized circuits can be
helpful is in enabling useful estimates of circuit performance, not particularly precise numerically but
sufficiently accurate to lead to a preliminary circuit design that then can be analyzed numerically by
computer. This helpfulness also is limited if complicated hand calculations need to be done.
As we will see the model can be considerably simplified and its usefulness greatly enhanced as a
consequence of this simplification. As part of the process of doing so we consider first the relationship of
the various model elements to the physical operation of the transistor. Keep in mind the presumption that
the Q-point operating point has the transistor biased for normal forward active mode operation.
The equivalent circuit describes the incremental base current as
The first term corresponds to the slope 1/rbe of the exponential current characteristic at the operating point
(expressed in terms of base current rather than incremental emitter current). That slope is
where ICQ is the operating point current. (It is convenient latter to use ib as a dependent variable. The
transistor action makes ic ≈ ßib. Instead of writing veb = ie re as in the earlier discussion of the forwardbiased diode we have substituted ie ≈ ßib and rbe = ß re.) The base resistance term rbe describes the
incremental emitter junction behavior; there is a small junction voltage change for a given current change
which is ignored in the idealized diode model. There is some small influence of the collector junction on
the base current, but in practice it is negligible. (For comparison estimate rbe ≈ 2.6 KΩ for a 1ma
quiescent current, ß = 100, and T ≈ 300K; rbc typically is measured in megohms.
Incidentally a useful value to have in mind is that kT/qe = 26 mv at T = 300K.)
The collector current is described by the model as
Introductory Electronics Notes
The University of Michigan-Dearborn
50-2
Copyright © M H Miller: 2000
revised
where gm = ß/rbe. The controlled current source, the first term, corresponds to the ‘transistor action’,
i.e., the injection of carriers into the base and their capture by collector junction. The other two resistors
are associated with the Early Effect. The resistance rce corresponds to an increase in collector current with
increasing vce because of a decrease in base width; the collector current is modified by the Early
component vce/rce. Associated with this is an increase in the efficiency of carrier transport across the
narrower base; fewer carriers trapped mean a lower base current. The effect is to reduce the base current
by an amount proportional to the voltage across the collector junction.
By and large rbc simply can be neglected, as indicated above. It corresponds to a second-order effect and
typically has a representative value greater than a megohm compared to representative values for rce of the
order of kilohms. In a KCL equation at the base node the current in rbe will be orders of magnitude
greater than the current through rbc. (Of course a nonlinear model used for a computer computation
nevertheless will account, at least in principle, for the Early Effect.) One can imagine pedagogical
circumstances where the neglect may be questionable, but even then transport delay effects (to be
considered later) far overshadow any effect of rbc.
Similarly, in practice, rce (typically 10-50 kilohms) generally may be omitted in using the model for
making estimates. The operation of the transistor is generally designed specifically to accept base current,
produce an amplified copy of the current at the collector and pass as much of this collector current to
circuitry connected at the collector -emitter terminals. For an effective current transfer the input resistance
presented by this circuitry should be small compared to rce. There is thus built into a circuit design an
incentive to reduce the influence of rce. Another reason for the simplification of neglecting rce is the
appropriate use of the transistor model. This circuit is not intended for precision calculations; circuit
analysis programs using nonlinear equations tailored to describe specific devices provide numerical data
faster and more precisely than manual calculations. The circuit model preferably should be used to provide
approximate information with sufficient accuracy to be useful. The model can be used to suggest
relationships between parameters and performance, and to provide rough design estimates of appropriate
element values. For this purpose, and within reason, accuracy should be sacrificed in favor of ease of
calculation. A computer computation can be used once element values are selected to obtain precise
numerical data.
Thus the simplified transistor equivalent circuit drawn to the right
is quite adequate in almost all instances in which it is used
primarily to provide useful design estimates and relationships
rather than precise values. A representative calculation and an
associated computer analysis serve to illustrate the matter.
Representative Incremental Parameter Analysis
The circuit drawn to the right is that of a single-stage CE amplifier. The '∞' symbol adjacent to a
capacitor is used to indicate that the capacitative
reactance has been deliberately made negligible
compared to the resistance with which it is series by a
using an appropriate combination of signal frequency
and capacitance value. Later when we consider
frequency response this simplification is not assumed.
Although not pertinent to the immediate purpose note
the use of the emitter capacitor (between node 8 and
node 4) to change the emitter stabilization. At low
signal frequencies the capacitor reactance is high
enough so that the 100Ω branch can be neglected. As
the signal frequency rises however the 100Ω branch
begins to dominate. The emitter resistance is used to
limit unwanted current changes; these tend to occur
slowly, e.g., changes with temperature. On the other
Introductory Electronics Notes
The University of Michigan-Dearborn
50-3
Copyright © M H Miller: 2000
revised
hand the current should change at frequencies higher than, say, a bass tone to enable amplification. In
another place frequency response will be considered in some detail
There really are two calculations to be made. First we determine the DC operation, in particular the
collector current. In part this is to assure operation in the forward active mode; a not-so-uncommon design
error may inadvertently place the transistor in saturation or cutoff, and for a careful design this should be
checked. After the DC calculation we determine the incremental equivalent circuit (for which knowledge
of ICQ is required) and calculate incremental performance. The capacitors form DC ‘blocks’, i.e., they do
not pass DC current. Hence they effectively disconnect parts of the amplifier circuit from involvement in
the DC biasing, as shown below, left. The value for ß is obtained from the 2N3904 manufacturer’s
specifications. An exact value should not be critical because of the emitter stabilization; the effect of
variations in the value of ß presumably has been reduced greatly by the feedback.
In the circuit below the biasing resistors have been replaced by a Thevenin equivalent as described
elsewhere, and a PWL model has replaced the transistor. The formal analysis of the model is left as an
exercise; nothing particularly different from earlier discussion is involved. Instead, to suggest the sort of
use for which the PWL model is intended we roughly estimate the emitter current as follows. Assume the
circuit design is reasonably well done. Then in the calculation for IE the term involving ß has been made
small compared to RE. That means the voltage drop across RB will be small compared to that across RE.
Hence the base voltage is more or less equal to VBB. Subtract a nominal 0.7 volts to account for the
emitter junction drop to obtain the emitter voltage, and divide this by RE to estimate the emitter current.
The base voltage is about 12(10/(10+33) ≈ 3 volts. Then the emitter current is ≈ 2.3/2.2 ≈ 1ma. A more
formal analysis of the PWL model calculates a current of 0.95 ma, and a PSpice nonlinear analysis (netlist
given below) computes 0.94 ma.
Incidentally the collector voltage is approximately 12 - 1*3.9 ≈ 8.1 volts, and we can conclude that
transistor operation is indeed in the normal forward operating mode.
For the incremental circuit analysis we assume as described before that a signal frequency has been chosen
to make the reactance of the coupling capacitors negligible as described before. The incremental equivalent
circuit is formed as follows. View, say, a node voltage as a superposition of a DC (quiescent point) value
and an AC (incremental voltage difference from the quiescent point.
We have considered the DC analysis separately above. Now consider the incremental (AC) part
separately; to do this turn all independent DC sources off (source magnitude -> 0). Note that this is a
mathematical and not a physical action. We will be considering only part of a node voltage (for example),
using the mathematical concept of superposition to combine the DC and AC analyses to obtain the total
node voltage.
Introductory Electronics Notes
The University of Michigan-Dearborn
50-4
Copyright © M H Miller: 2000
revised
The AC equivalent circuit is shown to the right. The value of rbe @ 300K = (121*26)/0.95 = 3.3 KΩ.
For the incremental circuit R1 and R2 are in
parallel, and the resistance of the parallel
combination is 7.67 KΩ. A representative
calculation is that of the voltage gain, i.e., the
ratio of the output voltage to the input voltage.
Since the ratio does not depend on the actual input
voltage magnitude we choose that to be 1 volt for
convenience. Any method of linear circuit
analysis, e.g., mesh or node equation methods,
may be used to calculate the gain.
However circuits of the type illustrated have a ‘ladder’ form which is conducive to a step-by-step
calculation (particularly using a calculator). The following circuit transformation also is often useful. The
current through the emitter resistor is (ß+1)ib. A current ib produces the same voltage drop across a
resistor ß+1 times larger. Hence the circuits shown are equivalent, i.e., the corresponding terminal voltampere relations are the same. Note that for node 5 it is sufficient to show just the current source.
Make the transformation as shown and verify the following step-by-step calculations (assuming Vin = 1v).
*CE Amplifier Incremental Parameter Analysis
VS
1
RS
1
CIN 2
R1
6
R2
3
Q1
5
RE
4
CE
4
RE2 8
RC
6
COUT 5
0
2
3
3
0
3
0
8
0
5
7
AC
4
1
1K
100UF
33K
10
Q2N3904
2.2K
100UF
100
3.9K
100UF
Introductory Electronics Notes
The University of Michigan-Dearborn
RL
7
0
3.9K
VCC 6
0 DC 12
*
Calculate gain at 1KHz
.AC LIN 1 1K 1.1K
*
Used to plot IC(Q1)
.DC TEMP -50 50 2
.OP
.PLOT AC V(7)
.PROBE
.END
50-5
Copyright © M H Miller: 2000
revised
Node Voltages
(1) 0.0000
(2) 0.0000
(5) 8.3127
(6) 12.0000
NAME
MODEL
IB
IC
VBE
VCE
(3) 2.7416
(7) 0.0000
(4) 2.0941
(8) 0.0000
Q1
Q2N3904
6.40E-06
9.45E-04
6.47E-01
6.22E+00
Voltage Gain (magnitude) = 13.05
As a matter of general interest the variation of quiescent collector current with temperature was computed.
Another Representative Incremental P arameter Analysis (RIPA)
The two-stage amplifier shown below employs DC but not AC feedback. The DC analysis follows that of
previous illustrations; neglect the Q2 base current relative to
the Q1 collector current (verify this subsequently) and write
a KVL equation for VCC following nodes 7->4->5->3->0.
The calculation is summarized below; details are left as an
exercise.
The incremental equivalent circuit is as shown below;
details of its derivation are left for an exercise. Normalizing
the input to 1 volt for simplicity calculate the output voltage
(= voltage gain). Any linear circuit analysis technique may
be used but the ladder development shown below the circuit diagram probably is simplest.
Introductory Electronics Notes
The University of Michigan-Dearborn
50-6
Copyright © M H Miller: 2000
revised
The first factor is the source current. Multiply by the current divider fraction to obtain the incremental base
current, and by the current amplification ß to obtain the Q2 incremental collector current. Continue like
this to calculate Vout = 7646. The computed voltage gain (see below) is 8865. The calculated value is
sufficiently close to the computed value to suggest usefulness of the approximate calculation in evaluating
the relative importance of various circuit elements in establishing the circuit performance.
Node Voltages
1) 0.0000
2) 0.0000
5) 1.3565
6) 6.00500
NAME
MODEL
IB
IC
VBE
VCE
Q1
Q2N3904
1.43E-05
2.10E-03
6.85E-01
2.03E+00
3) .6850
7) 9.0000
4) 2.0290
Q2
Q2N3904
9.43E-06
1.36E-03
6.73E-01
4.65E+00
Voltage Gain = 8865
Yet Another RIPA
In this illustrative circuit a PNP transistor substitutes for the collector load resistor of Q1. Since the bias
voltages are fixed Q2 acts very nearly as a current source. Not quite of course because of the Early Effect,
but the slope of the Q2 collector characteristics corresponds to tens of kilohms. Note however that the DC
voltage drop across Q2 is considerably less than what it would be for a standard resistor of equivalent size.
The PWL calculation of the emitter current of the PNP device (2N3906) is isolated from that for the NPN
(2N3904) device. The current calculations then are done separately, as shown to the right of the circuit
diagram. The PSpice computation gives very similar results. Actually this should be expected, since the
terms involving the uncertainties in junction voltage and ß make relatively small contributions to the
expressions. Ignoring the numerical difference between emitter and collector currents provides an estimate
for the load current of 0.91 - 0.57 - 0.34ma, and a DC load voltage of 2.79 volts; the computed voltage is
2.87 volts.
Introductory Electronics Notes
The University of Michigan-Dearborn
50-7
Copyright © M H Miller: 2000
revised
PSpice Computation Result
NODE VOLTAGE
(1) 2.0000
(2) 2.0000
(5) 2.8704
(6) 7.2303
NAME
MODEL
IB
IC
VBE
VCE
Q1
Q2N3904
5.62E-06
5.87E-04
6.40E-01
1.57E+00
(3) 1.3036
(7) 7.9293
(4) 1.9438
(8) 10.0000
Q2
Q2N3906
-4.25E-06
-9.37E-04
-6.99E-01
-5.06E+00
The incremental equivalent circuit is drawn below. Note that Q2 does not affect (to first order) the signal
amplification since the incremental base current for this stage is zero. The Q2 stage serves as a fixed DC
current source. The calculation of the voltage gain is straightforward; voltage gain = -3.52. The computed
voltage gain is -3.34. Details of the analysis are left as an exercise.
Still Another RIPA
The incremental parameter equivalent circuit for this circuit configuration corresponds to a CE stage (Q1)
whose collector current drives a CB stage (Q2). This combination offers certain advantages in high
frequency amplification, something considered elsewhere. Note however that the DC biasing circuit
directly couples the two stages.
Perhaps the simplest estimate of the DC bias voltages follows on the assumption, subject to verification,
that the transistor base currents may be neglected compared to the main current in the bias resistors, i.e.,
consider the bias resistors to form a simple voltage divider. The current in the resistors then is 10/(68 + 15
+ 18) = 99µa. Estimate the Q 1 base voltage to be 18x99 ->1.78 v, subtract a nominal 0.7 volt junction
voltage, and thus estimate the Q1 emitter current to be 1.08 ma. The base current would be approximately
1.08/121 -> 9 µa. The assumption of neglecting base current appears to be reasonable. (Iteration, using
the estimated base current rather than simply neglecting the current, provides a better estimate. Indeed
Introductory Electronics Notes
The University of Michigan-Dearborn
50-8
Copyright © M H Miller: 2000
revised
repeated iteration will converge rapidly to the result for an exact calculation (PWL model). After all the
circuit includes feedback to stabilize the current against perturbations. One may consider the difference
between an exact value and the estimated value as a perturbation, and the feedback diminishes the effect of
that perturbation! As a practical matter rarely if ever is an iteration necessary, i.e., the initial estimate is
close enough for design purposes. A refined value may then be obtained by a computer computation. In
this case, for example, the computed emitter current for Q1 is 0.90 ma.
The base resistance is estimated to be
121(26/1.08) = 2.9 KΩ. Because of the high ß
both transistors operate at essentially the same
emitter current. The incremental parameter
equivalent circuit is drawn above, to the right of
the circuit diagram. Again note the
reconfiguration of the AC circuit because of the
bypass action of the capacitors. The gain
calculation is straightforward; the calculated gain
is 28.2. This is to be compared to the computed
gain of 24. Providing details is left as an
exercise.
PSpice Computation Results
Voltage Gain = 24
NAME
MODEL
IB
IC
VBE
VCE
Q1
Q2N3904
8.68E-06
9.01E-04
6.51E-01
1.43E+00
Q2
Q2N3904
7.64E-06
8.93E-04
6.48E-01
4.17E+00
A Final RIPA
The single-ended differential circuit configuration illustrates one use of symmetry in circuit design.
Using the simplified PWL model, calculate the Q3 collector current (nominal ß = 120, VBE = 0.7v) to be
9.4 ma. Note that the influence of ß and VBE in the calculation is mitigated by the feedback. Assuming
matched Q1 and Q2 transistors the Q3 collector current splits equally so that the emitter current (and
closely the collector current) of Q1 and Q2 is 4.7 ma. Then r be @ 300K ≈ 121(26/4.7) = 669Ω. The
incremental equivalent circuit is drawn ion the right of the figure. KCL dictates the relative currents as
shown , and ib = 1( 10 + .669 + 10 + .669) and Vout = 5.6 v; this is also the calculated voltage gain.
PSpice Computation Results
NAME
Q1
Q2
MODEL
Q2N3904
Q2N3904
IC
4.70E-03
4.70E-03
VBE
7.06E-01
7.06E-01
VCE
5.29E+00
5.29E+00
Q3
Q2N3904
9.45E-03
7.25E-01
5.92E+00
Voltage Gain = 7.54
Introductory Electronics Notes
The University of Michigan-Dearborn
50-9
Copyright © M H Miller: 2000
revised
PROBLEMS
For each of the following problems assume that the transistors are 2N3904 (NPN) and 2N3906 (PNP)
respectively as appropriate. Use a nominal ß of 120 and VBE = 0.7v. In each case calculate the DC
operating conditions using the PWL transistor model, and apply the simplified incremental parameter
model to calculate the voltage gain for a 1KHz sinusoidal signal input. Compare calculated values to those
obtained from a computer simulation.
Introductory Electronics Notes
The University of Michigan-Dearborn
50-10
Copyright © M H Miller: 2000
revised
6)
Calculate the voltage gain of the amplifier
circuit drawn on the right, omitting the 22 KΩ
resistor connected with dashed lines. Then assume,
as an approximation, that this non-inverting amplifier
can be considered to be an idealized opamp, i.e., the
voltage gain is ‘high’, the input resistance is ‘high’,
etc.. Apply feedback as shown, and compare the
computed voltage gain with the idealized opamp
expectation of a voltage gain of 11. Note: The
capacitor is used to block involvement of the
feedback resistor in the DC biasing.
Introductory Electronics Notes
The University of Michigan-Dearborn
50-11
Copyright © M H Miller: 2000
revised