Download 2.8 - CMOS TECHNOLOGY

CMOS Technology (6/7/00)
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2.8 - CMOS TECHNOLOGY
INTRODUCTION
Objective
The objective of this presentation is:
1.) Illustrate the fabrication sequence for a typical MOS transistor
2.) Show the physical aspects of the MOSFET
Outline
• CMOS technology
• Compatible active devices
• Summary
ECE 4430 - Analog Integrated Circuits and Systems
 P.E. Allen, 2000
CMOS Technology (6/7/00)
Page 2
CMOS TECHNOLOGY
Fabrication
Fabrication involves the implementation of semiconductor processes to build a MOSFET transistor and
compatible passive components as an integrated circuit.
N-Well CMOS Fabrication Major Steps
1.) Implant and diffuse the n-well
2.) Deposition of silicon nitride
3.) n-type field (channel stop) implant
4.) p-type field (channel stop) implant
5.) Grow a thick field oxide (FOX)
6.) Grow a thin oxide and deposit polysilicon
7.) Remove poly and form LDD spacers
8.) Implantation of NMOS S/D and n-material contacts
9.) Remove spacers and implant NMOS LDDs
10.) Repeat steps 8.) and 9.) for PMOS
11.) Anneal to activate the implanted ions
12.) Deposit a thick oxide layer (BPSG - borophosphosilicate glass)
13.) Open contacts, deposit first level metal and etch unwanted metal
14.) Deposit another interlayer dielectric (CVD SiO2), open vias and deposit second level metal
15.) Etch unwanted metal, deposit a passivation layer and open over bonding pads
ECE 4430 - Analog Integrated Circuits and Systems
 P.E. Allen, 2000
CMOS Technology (6/7/00)
Page 3
Major CMOS Process Steps
Step 1 - Implantation and diffusion of the n-wells
n-well implant
SiO2
Photoresist
Photoresist
p- substrate
Step 2 - Growth of thin oxide and deposition of silicon nitride
Si3N4
SiO2
n-well
p-
substrate
Fig. 2.2-1
ECE 4430 - Analog Integrated Circuits and Systems
 P.E. Allen, 2000
CMOS Technology (6/7/00)
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Major CMOS Process Steps - Continued
Step 3.) Implantation of the n-type field channel stop
n- field implant
Photoresist
Si3N4
Photoresist
Pad oxide (SiO2)
n-well
p- substrate
Step 4.) Implantation of the p-type field channel stop
p- field implant
Si3N4
Photoresist
n-well
p-
substrate
Fig. 2.2-2
ECE 4430 - Analog Integrated Circuits and Systems
 P.E. Allen, 2000
CMOS Technology (6/7/00)
Page 5
Major CMOS Process Steps - Continued
Step 5.) Growth of the thick field oxide (LOCOS - localized oxidation of silicon)
Si3N4
FOX
FOX
n-well
p- substrate
,,,,,,,,,,
,,,,,,,,,,
Step 6.) Growth of the gate thin oxide and deposition of polysilicon
Polysilicon
FOX
FOX
n-well
p- substrate
Fig. 2.2-3
ECE 4430 - Analog Integrated Circuits and Systems
 P.E. Allen, 2000
CMOS Technology (6/7/00)
Page 6
Major CMOS Process Steps - Continued
Step 7.) Removal of polysilicon and formation of the sidewall spacers
,,
,,
Polysilicon
FOX
SiO2 spacer
,,
Photoresist
FOX
p- substrate
n-well
FOX
FOX
Step 8.) Implantation of NMOS source and drain and contact to n-well (not shown)
n+ S/D implant
,,
Polysilicon
FOX
p- substrate
,
Photoresist
FOX
FOX
FOX
n-well
Fig. 2.2-4
ECE 4430 - Analog Integrated Circuits and Systems
 P.E. Allen, 2000
CMOS Technology (6/7/00)
Page 7
Major CMOS Process Steps - Continued
Step 9.) Remove sidewall spacers and implant the NMOS lightly doped source/drains
,
n- S/D LDD implant
Polysilicon
FOX
,,
Photoresist
FOX
p- substrate
n-well
FOX
FOX
Step 10.) Implant the PMOS source/drains and contacts to the p- substrate (not shown),
remove the sidewall spacers and implant the PMOS lightly doped source/drains
,
Polysilicon
FOX
p- substrate
,,
,,
LDD Diffusion
FOX
FOX
FOX
n-well
Fig. 2.2-5
ECE 4430 - Analog Integrated Circuits and Systems
 P.E. Allen, 2000
CMOS Technology (6/7/00)
Page 8
Major CMOS Process Steps - Continued
,
,,
Step 11.) Anneal to activate the implanted ions
n+ Diffusion
FOX
p+ Diffusion
FOX
Polysilicon
FOX
n-well
p- substrate
Step 12.) Deposit a thick oxide layer (BPSG - borophosphosilicate glass)
,
n+ Diffusion
FOX
p- substrate
,,
p+ Diffusion
FOX
Polysilicon
BPSG
FOX
n-well
Fig. 2.2-6
ECE 4430 - Analog Integrated Circuits and Systems
 P.E. Allen, 2000
CMOS Technology (6/7/00)
Page 9
Major CMOS Process Steps - Continued
Step 13.) Open contacts, deposit first level metal and etch unwanted metal
CVD oxide, Spin-on glass (SOG)
FOX
p-
,
FOX
,,
Metal 1
BPSG
FOX
n-well
substrate
Step 14.) Deposit another interlayer dielectric (CVD SiO2), open contacts,
deposit second level metall
Metal 2
Metal 1
FOX
,
p- substrate
FOX
,,
BPSG
FOX
n-well
Fig. 2.2-7
ECE 4430 - Analog Integrated Circuits and Systems
 P.E. Allen, 2000
CMOS Technology (6/7/00)
Page 10
Major CMOS Process Steps - Continued
Step 15.) Etch unwanted metal and deposit a passivation layer and open
over bonding pads
Metal 2
FOX
,
Passivation protection layer
p- substrate
FOX
,,
Metal 1
BPSG
FOX
n-well
Fig. 2.2-8
p-well process is similar but starts with a p-well implant rather than an n-well implant.
ECE 4430 - Analog Integrated Circuits and Systems
 P.E. Allen, 2000
CMOS Technology (6/7/00)
Page 11
Approximate Side View of CMOS Fabrication
,,,
,,,
,,,,,,
Passivation
Metal 4
Metal 3
Metal 2
2 microns
,,,,,
,,
Metal 1
Polysilicon
Diffusion
ECE 4430 - Analog Integrated Circuits and Systems
Fig. 2.2-9
 P.E. Allen, 2000
CMOS Technology (6/7/00)
Page 12
Silicide/Salicide Technology
Used to reduce interconnect resistivity by placing a low-resistance silicide such as TiSi2, WSi2, TaSi2, etc.
on top of polysilicon
Salicide technology (self-aligned silicide) provides low resistance source/drain connections as well as lowresistance polysilicon.
Polysilicide
FOX
,
Polysilicide
Metal
Metal
,,
Salicide
FOX
Polycide structure
ECE 4430 - Analog Integrated Circuits and Systems
FOX
Salicide structure
FOX
Fig2.2-10
 P.E. Allen, 2000
CMOS Technology (6/7/00)
Page 13
COMPATIBLE ACTIVE DEVICES
Lateral Bipolar Junction Transistor
P-Well Process
NPN LateralVDD
n+
Base
Emitter
Collector
p+
n+
n+
p-well
n-substrate
ECE 4430 - Analog Integrated Circuits and Systems
 P.E. Allen, 2000
CMOS Technology (6/7/00)
Page 14
Lateral Bipolar Junction Transistor - Continued
Field-aided LateralßF ≈ 50 to 100 depending on the process
Keep channel
from forming
VDD
n+
Emitter VGate Collector
Base
n+
p+
n+
p-well
n-substrate
• Good geometry matching
• Low 1/f noise (if channel doesn’t form)
• Acts like a photodetector with good efficiency
ECE 4430 - Analog Integrated Circuits and Systems
 P.E. Allen, 2000
CMOS Technology (6/7/00)
Page 15
Geometry of the Lateral PNP BJT
Minimum Size layout of a single
emitter dot lateral PNP BJT:
n-well
p-diffusion
contact
40 emitter dot LPNP transistor (total device area
is 0.006mm2 in a 1.2µm CMOS process):
p-substrate
diffusion
Base
n-well
contact
Lateral
Collector
Emitter
31.2
µm
71.4
µm
Base
Gate
V SS
Lateral
Collector
V SS
Emitter
84.0 µm
Gate
(poly)
33.0 µm
ECE 4430 - Analog Integrated Circuits and Systems
 P.E. Allen, 2000
CMOS Technology (6/7/00)
Page 16
Performance of the Lateral PNP BJT
Schematic:
Emitter
Gate
Base
Lateral
Collector
Vertical
Collector
( V SS )
ßL vs ICL for the 40 emitter dot LPNP BJT:
Lateral efficiency versus IE for the 40
emitter dot LPNP BJT:
VCE =
− 4.0 V
150
1.0
130
VCE =
− 4.0 V
Lateral Efficiency
Lateral ß
0.8
110
VCE =
− 0. 4V
90
VCE =
− 0. 4V
0.6
0.4
70
0.2
50
1 nA
10 nA
100 nA
1 µA
10 µA
Lateral Collector Current
100 µA
1 mA
ECE 4430 - Analog Integrated Circuits and Systems
0
1 nA
10 nA
100 nA
1 µA
10 µA
Emitter Current
100 µA
1 mA
 P.E. Allen, 2000
CMOS Technology (6/7/00)
Page 17
Performance of the Lateral PNP BJT - Continued
Typical Performance for the 40 emitter dot LPNP BJT:
Transistor area
0.006 mm2
Lateral ß
90
Lateral efficiency
0.70
Base resistance
150
En @ 5 Hz
2.46 nV / Hz
En (midband)
1.92 nV / Hz
fc (En)
3.2 Hz
In @ 5 Hz
3.53 pA / Hz
In (midband)
0.61 pA / Hz
fc (In)
162 Hz
fT
85 MHz
Early voltage
16 V
ECE 4430 - Analog Integrated Circuits and Systems
 P.E. Allen, 2000
CMOS Technology (6/7/00)
Page 18
High Voltage MOS Transistor
The well can be substituted for the drain giving a lower conductivity drain and therefore higher
breakdown voltage.
NMOS in n-well example:
Source
Oxide
Gate
Drain
Substrate
n+
p+
Polysilicon
n+
Source
Channel
n-well
p-substrate
Fig. 2.6-7A
Drain-substrate/channel can be as large as 20V or more.
ECE 4430 - Analog Integrated Circuits and Systems
 P.E. Allen, 2000
CMOS Technology (6/7/00)
Page 19
Latch-up in CMOS Technology
Latch-up Mechanisms
1. SCR regenerative switching action.
2. Secondary breakdown.
3. Sustaining voltage breakdown.
Parasitic lateral PNP and vertical NPN BJTs in a p-well CMOS technology:
,,
,,
,,
,,
,,
,,
,,,,,,,,,,
,,
,,
,,
,,
,,
,,
,,
,,
,,,,
|,, ,,
{
|,,,,
{
VDD
D
G
S
S
D
G
A
n+
p+
p-well
p+
RN-
n+
B
VSS
p+
n+
RP-
n- substrate
Fig. 2.6-8
Equivalent circuit of the SCR formed from the parasitic BJTs:
VDD
VDD
+
RNA
Vin ≈VSS
B
A
-
Vout
B
RP-
VSS
VSS
ECE 4430 - Analog Integrated Circuits and Systems
Fig. 2.6-9
 P.E. Allen, 2000
CMOS Technology (6/7/00)
Page 20
Preventing Latch-Up in a P-Well Technology
1.) Keep the source/drain of the MOS device not in the well as far away from the well as possible. This
will lower the value of the BJT betas.
2.) Reduce the values of RN- and RP-. This requires more current before latch-up can occur.
3.) Make a p- diffusion around the p-well. This shorts the collector of Q1 to ground.
n+
p-channel transistor
guard bars
VDD
FOX
p+
n-channel transistor
guard bars
VSS
FOX
FOX
FOX
FOX
p-well
FOX
FOX
n- substrate
Figure 2.6-10
For more information see R. Troutman, “CMOS Latchup”, Kluwer Academic Publishers.
ECE 4430 - Analog Integrated Circuits and Systems
 P.E. Allen, 2000
CMOS Technology (6/7/00)
Page 21
Electrostatic Discharge Protection (ESD)
Objective: To prevent large external voltages from destroying the gate oxide.
Electrical equivalent circuit
VDD
p+ to n-well
diode
To internal gates
n+ to p-substrate
diode
p+ resistor
Bonding
Pad
VSS
Implementation in CMOS technology
Metal
FOX
n+
FOX
p+
FOX
n-well
p-substrate
Fig. 2.6-11
ECE 4430 - Analog Integrated Circuits and Systems
 P.E. Allen, 2000
CMOS Technology (6/7/00)
Page 22
Temperature Characteristics of Transistors
Fractional Temperature Coefficient
1 ∂x
Typically in ppm/°C
TCF = x· ∂T
MOS Transistor
V T = V(T0 ) + α(T-T 0 ) + ···, where α ≈ -2.3mV/°C (200°K to 400°K)
µ = KµT-1.5
BJT Transistor
Reverse Current, IS:
1 ∂I S 3 1 VG0
·
= +
IS ∂T T T kT/q
Empirically, IS doubles approximately every 5°C increase
Forward Voltage, vD:
V G0 - v D 3kT/q
∂vD
=
- T ≈ -2mV/°C at vD = 0.6V
∂Τ
T
ECE 4430 - Analog Integrated Circuits and Systems
 P.E. Allen, 2000
CMOS Technology (6/7/00)
Page 23
Noise in Transistors
Shot Noise
i2 = 2qID∆f (amperes2)
where
q = charge of an electron
ID = dc value of iD
∆f = bandwidth in Hz
i2
2
Noise current spectral density =
∆f (amperes /Hz)
Thermal Noise
Resistor:
v2 = 4kTR∆f (volts2)
MOSFET:
iD2 =
8kTgm∆f
(ignoring bottom gate)
3
where
k = Boltzmann’s constant
R = resistor or equivalent resistor in which the thermal noise is occurring.
gm = transconductance of the MOSFET
ECE 4430 - Analog Integrated Circuits and Systems
 P.E. Allen, 2000
CMOS Technology (6/7/00)
Page 24
Noise in Transistors - Continued
Flicker (1/f) Noise
 Ia 
iD2 = Kf b ∆f
f 
where
Kf = constant (10-28 Farad·amperes)
a = constant (0.5 to 2)
b = constant (≈1)
Noise power
spectral density
1/f
log(f)
Fig. 2.6-12
ECE 4430 - Analog Integrated Circuits and Systems
 P.E. Allen, 2000
CMOS Technology (6/7/00)
Page 25
SUMMARY
• CMOS is a fairly simple, technology which is used primarily for digital circuits
• The minimum channel length of CMOS tends to decrease by a factor of 1/ 2 every three years
(Moore’s Law)
• CMOS technology can be used for analog circuits but it would not be the preferred choice if everything
else were equal.
• Active devices compatible with standard CMOS technology are:
- Lateral BJTs
- Vertical BJTs (not shown)
• Other considerations
- Latchup
- Electrostatic Breakdown
ECE 4430 - Analog Integrated Circuits and Systems
 P.E. Allen, 2000