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Transcript

Series Resonant Converter with Output Voltage Doubler Bor-Ren Lin, Senior Member, IEEE, Li-An Lin, Yen-Ju Chiang and Po-Li Chen Department of Electrical Engineering, National Yunlin University of Science and Technology Yunlin 640, Taiwan, ROC Abstract—This paper presents a parallel zero voltage switching (ZVS) dc-dc converter with series connected transformers. In order to increase output power, two transformers connected in series are used in the proposed converter. Two buck-type converters connected in parallel have the same switching devices. The primary windings of series connected transformers can achieve the balanced secondary winding currents. The current doubler rectifiers with ripple current cancellation are connected in parallel at the output side to reduce the current stress of the secondary winding. Thus the current ripple on the output capacitor is reduced and the size of output choke and output capacitor are reduced. Only two switches are used in the proposed circuit instead of four switches in the conventional parallel ZVS converter to achieve zero voltage switching and output current sharing. Therefore, the proposed converter has less power switches. The ZVS turn-on is implemented during the commutation stage of two complementary switches such that the switching losses and thermal stresses on the semiconductors are reduced. Experimental results for a 528W (48V/11A) prototype are presented to prove the theoretical analysis and circuit performance. Keywords- series connected transformers, parallel converters, converters. I. INTRODUCTION To reduce the environmental pollution and save energy waste, EPA (Environment Protection Agency) and CSCI (Climate Saver Computing Initiative) have been proposed the necessary circuit efficiency of modern power supply unit. For consumer power electronics, the small package size and high efficiency of power supply are also demanded. Two ways to achieve high efficiency power converters, there are the singlestage power converters for low power applications and twostage power converters for medium and high power applications. Single-stage power converters are used in the applications of the electronic ballasts and light emitting diodes (LED) street lighting system. For two-stage power converters, the front-end stage with power factor correction (PFC) is normally adopted to reduce current harmonics and reactive power with 93~95% efficiency. Soft switching techniques have been proposed in [1]-[7] to achieve high efficiency dc-dc converter. However, the main drawback of these techniques is high voltage or current stresses on power semiconductors to limit the practical applications in power supply unit. In series resonant converter, the output voltage cannot be properly regulated at no-load condition. The LLC series resonant converter has been drawn attention due to its essential This project is supported by the National Science Council of Taiwan under Grant NSC 99-2221-E-224-083-MY2. advantages of high conversion efficiency and high power density [8]-[14]. The half-bridge or full-bridge converter type is usually adopted at the primary side to realize the zero voltage switching (ZVS) turn-on for all power switches without any auxiliary circuit. If the switching frequency is lower than the series resonant frequency, the secondary side rectifier is operated under zero current switching (ZCS) condition. Then the reverse recovery losses for diode rectifier or the switching losses for synchronous rectifier are reduced. This paper presents a parallel LLC series resonant converter for server/data storage system applications. In the proposed converter, two converter cells are connected in parallel to share the input and load current. The output voltage doubler is adopted in the secondary side to reduce the secondary winding turns and to clamp the voltage stress of the rectifier diodes to output voltage. Thus the low voltage rating schottky diodes can be used in the secondary side. The design switching frequency at full load condition is less than series resonant frequency. Thus the power switches in the primary side are operated at ZVS turn-on and the rectifier diodes in the secondary side are operated at ZCS turn-off. Therefore, the switching losses of power switches and reverse recovery losses of rectifier diodes are reduced. The fundamental frequency approximation technique is adopted to derive the voltage conversion ratio and the circuit parameters. A design procedure of the proposed converter is presented in detail. Experiments based on a 960W prototype for server power supply unit were provided to verify the effectiveness of the proposed converter. II. CIRCUIT CONFIGURATION The circuit configuration of the proposed converter is shown in Fig. 1. Compared with other soft switching converters such as asymmetry half-bridge converters and active clamp converters, the adopted LLC converter can achieve ZVS turn-on of power switches with the wide range of load conditions and input voltage range. The rectifier diodes can be turned off at ZCS if the switching frequency is less than the series resonant frequency. Thus the switching losses are reduced. The output terminal voltage is controlled by variation of switching frequency. Two LLC circuits with output voltage doubler are connected in parallel to share the load current. Thus the current stresses at the secondary windings are reduced. Vin and Vo are input and output terminal voltages, respectively. In circuit 1, switches Q1 and Q2 are half-bridge network, Cr1, Lr1, and Lm1 are resonant tank, T1 is an isolated transformer, and D1 and D2 are rectifier diodes. Coss1 and Coss2 are output capacitances of switches Q1 and Q2 respectively. In the same manner, the circuit 2 includes the circuit components of Q3, Q4, Cr2, Lr2, Lm2, T2, D3 and D4. The output voltage doubler rectifier is adopted to reduce the secondary winding turns compared with the center-tapped rectifier topology. The voltage stress of rectifier diodes is clamped to output terminal voltage Vo. There is only a diode voltage drop at the secondary side instead of two diode voltage drop in the full-wave diode rectifier. The proposed circuit with power factor correction in the front stage can be used in medium power rating applications such as all-in-one PC power supply, LCD-TV power module, PDP-TV power module, server power supply unit and data storage power supply unit to meet the efficiency requirements. Vin Q2 Coss1 Cr1 Lr1 vCr1 iLr1 Coss2 iQ2 vLm1 v D T1 s1 1 Lm1 iD1 iLm1 Np:Ns iD2 iQ3 Q3 Q4 iQ4 Vo Co1 Co2 Io Vo1 Ro iQ1 Q1 Vo2 D2 Coss3 Cr2 Lr2 vCr2 iLr2 Coss4 vLm2 Lm2 iLm2 T2vs2 D3 iD3 Np:Ns iD4 D4 Fig. 1 Proposed parallel LLC series resonant converter. III. OPERATION PRINCIPLE The adopted series resonant converter is regulated using the frequency modulation technique with 50% duty cycle on each power switch. The components of two LLC circuits are Coss=Coss1=Coss2=Coss3=Coss4, identical, Cr=Cr1=Cr2, Lr=Lr1=Lr2, Lm=Lm1=Lm2. The turns ratio of transformers T1 and T2 is n=Np/Ns. The output voltages Vo1=Vo2. Based on the on/off states of switches and rectifier diodes, there are eight operation modes in a switching cycle. Fig. 2 and Fg. 3 give the main key waveforms and the topological equivalent circuits in a switching cycle. Before time t0, Q2 and Q3 are on and the resonant inductor current iLr1=iLm1 and iLr2=iLm2. All rectifier diodes D1~D4 are all off. Mode 1 [t0≤t<t1]: At time t0, switches Q2 and Q3 are turned off and diodes D1 and D4 are conducting in this mode. The magnetizing inductance voltages vLm1 and vLm2 are clamped to nVo1 and -nVo2, respectively. The magnetizing current iLm1 increases and iLm2 decreases in this mode. iLm1 (t ) = iLm1 (t0 ) + nVo1 (t − t0 ) / Lm , iLm 2 (t ) = iLm 2 (t0 ) − nVo 2 (t − t0 ) / Lm (1) where n=Np/Ns and Lm1=Lm2=Lm. Coss1, Coss2, Cr1 and Lr1 are resonant in circuit 1 and Coss3, Coss4, Cr2 and Lr2 are resonant in circuit 2. The inductor current iLr1 charges capacitor Coss2 from zero voltage and discharges capacitor Coss1 from Vin. In the same manner, Capacitor Coss3 is charged from zero voltage and capacitor Coss4 is discharged from Vin. The capacitor voltages are approximately expressed as: i (t ) i (t ) vCoss1 (t ) ≈ Vin − Lr1 0 (t − t 0 ) , vCoss 2 (t ) ≈ Lr1 0 (t − t 0 ) , 2Coss 2Coss i Lr 2 (t 0 ) i (t ) (t − t 0 ) , vCoss 2 (t ) ≈ Vin − Lr 2 0 (t − t 0 ) (2) 2Coss 2Coss The secondary winding currents iD1 and iD4 are given as: iD1 (t ) = n[iLr1 (t ) − iLm1 (t )] , iD 4 (t ) = n[−iLr 2 (t ) + iLm 2 (t )] (3) At time t1, the voltages vCoss2 and vCoss3 equal Vin and vCoss1 and vCoss4 equal 0. Then the anti-parallel diode of Q1 and Q4 is conducting. Mode 2 [t1≤t<t2]: At time t1, the anti-parallel diodes of Q1 and Q4 are conducting. In the secondary side, the rectifier diodes D1 and D4 are forward-biased to charge capacitor voltage Vo1 and Vo2 respectively. Since the switch currents iQ1 and iQ4 are negative in this mode, switches Q1 and Q4 can be turned on in this interval to realize ZVS. This mode ends at time t2 when Q1 and Q4 are turned on. Mode 3 [t2≤t<t3]: At time t2, Q1 and Q4 are turned on at ZVS (since iLr1(t2)<0 and iLr2(t2)>0). The rectifier diodes D1 and D4 are conducting in this mode. Thus the magnetizing inductor voltages vLm1=nVo1 and vLm2=-nVo2. The magnetizing current iLm1 increases linearly with the slope of nVo1/Lm and the magnetizing current iLm2 decreases linearly with the slope of nVo2/Lm. Lr1 and Cr1 are resonant with the applied voltage VinnVo1 in circuit 1 and Lr2 and Cr2 are resonant with the applied voltage -nVo2 in circuit 2. The resonant frequency of circuits 1 and 2 in this mode is derived as: vCoss 3 (t ) ≈ Fig. 2 Key waveforms of the proposed converter. f r = 1 / 2π Lr Cr (3) Ro (b) (c) Ro (a) (d) (e) iQ1 Q1 Vin Q2 Coss1 Cr1 Lr1 vCr1 Coss2 iQ2 vLm1 v D T1 s1 1 iLr1 Lm1 iD1 iLm1 Np:Ns iD2 iQ3 Q3 Q4 iQ4 Vo (f) Io Vo1 Vo2 D2 Coss3 Cr2 vCr2 Coss4 Lr2 vLm2 v D T2 s2 3 iLr2 Lm2 iD3 iLm2 Np:Ns iD4 D4 (g) (h) Fig. 3 Operation modes of the proposed converter (a) mode 1 (b) mode 2 (c) mode 3 (d) mode 4 (e) mode 5 (f) mode 6 (g) mode 7 (h) mode 8. The resonant inductor currents and capacitor voltages during this interval are expressed as: V − nVo1 − vCr1 (t 2 ) t − t2 t − t2 (4) + iLr1 (t 2 ) cos iLr1 (t ) = in sin Lr / Cr Lr Cr Lr Cr iLr 2 (t ) = nVo 2 − vCr 2 (t 2 ) Lr / Cr sin t − t2 Lr Cr + iLr 2 (t 2 ) cos vCr1 (t ) = Vin − nVo1 − [Vin − nVo1 − vCr1 (t 2 )] cos L t − t2 + iLr1 (t 2 ) r sin Cr Lr Cr t − t2 Lr Cr (5) t − t2 Lr Cr (6) vCr 2 (t ) = nVo 2 − [nVo 2 − vCr 2 (t 2 )] cos L t − t2 + iLr 2 (t 2 ) r sin Cr Lr Cr t − t2 Lr Cr (7) The resonant inductor current iLr1 increases and iLr2 decreases. In circuit 1, the power is transferred from input terminal voltage Vin to output voltage Vo1 through Cr1, Lr1, T1 and D1. In circuit 2, the energy stored in resonant inductance Lr2 is transferred to output voltage Vo2 through Cr2, Lr2, T2 and D4. This mode ends at time t3 when iLm1=iLr1 and iLm2=iLr2. Then the diode currents iD1=iD4=0 and diodes D1 and D4 go to turn off. Mode 4 [t3≤t<t4]: This mode starts at t3 when iLm1=iLr1 and iLm2=iLr2. Then all the secondary diodes D1~D4 are off. However, switches Q1 and Q4 are still on. Thus the components Cr1, Lr1 and Lm1 in circuit 1 are resonant. In the same manner, Cr2, Lr2 and Lm2 in circuit 2 are resonant in this interval. The resonant frequency is given as: f p = 1 / 2π ( Lm + Lr )Cr (8) The resonant inductor currents and capacitor voltages during this interval are expressed as: V − v (t ) t − t3 iLr1 (t ) = in Cr1 3 sin ( Lr + Lm ) / Cr ( Lr + Lm )Cr (9) t − t3 + iLr1 (t3 ) cos ( Lr + Lm )Cr i Lr 2 (t ) = − v Cr 2 (t 3 ) ( Lr + Lm ) / C r + i Lr 2 (t 3 ) cos sin t − t3 ( L r + L m )C r t − t3 ( L r + L m )C r vCr1 (t ) = Vin − [Vin − vCr1 (t3 )] cos t − t3 ( Lr + Lm )Cr L + Lm t − t3 + iLr1 (t3 ) r sin Cr ( Lr + Lm )Cr vCr 2 (t ) = vCr 2 (t 3 ) cos (10) (11) t − t3 ( Lr + Lm )C r L + Lm t − t3 + i Lr 2 (t 3 ) r sin Cr ( Lr + Lm )C r (12) In this mode, the resonant inductor current iLr1=iLm1 and iLr2=iLm2. This mode ends at time t4 when switches Q1 and Q4 are turned off. Mode 5 [t4≤t<t5]: At time t4, Q1 and Q4 are turned off and diodes D2 and D3 are conducting. The magnetizing inductance voltages vLm1 and vLm2 are clamped to -nVo2 and nVo1, respectively. The magnetizing current iLm1 decreases with the slope of -nVo2/Lm and iLm2 increases with the slope of nVo1/Lm in this mode. At time t4, the inductor currents iLr1 and iLr2 are positive and negative, respectively. Coss1 and Coss2 are charged and discharged respectively by inductor current iLr1. In the same manner, Coss3 and Coss4 are discharged and charged respectively by inductor current iLr2. If the energy stored in the inductor Lr1 is greater than the energy stored in capacitors Coss1 and Coss2, then capacitor Coss1 can be charged to Vin and Coss2 can be discharged to zero voltage. The drain to source voltages of Q1 and Q2 are derived as: i (t ) vQ1, ds (t ) = vCoss1 (t ) ≈ Lr1 4 (t − t 4 ) , 2Coss iLr1 (t4 ) (t − t4 ) (13) 2Coss Likewise, the drain to source voltages of Q3 and Q4 are derived as: vQ 2, ds (t ) = vCoss 2 (t ) ≈ Vin − vQ3, ds (t ) = vCoss 3 (t ) ≈ Vin − iLr 2 (t 4 ) (t − t4 ) , 2Coss iLr 2 (t 4 ) (t − t4 ) (14) 2Coss The secondary winding currents iD2 and iD3 are given as: iD 2 (t ) = n[−iLr1 (t ) + iLm1 (t )] , iD 3 (t ) = n[iLr 2 (t ) − iLm 2 (t )] (15) At time t5, the capacitor voltages vCoss2 and vCoss3 equal zero voltage. Then the anti-parallel diode of Q2 and Q3 is conducting. Mode 6 [t5≤t<t6]: At time t5, the anti-parallel diode of Q2 and Q3 is conducting (iLr1(t5)>0 and iLr2(t5)<0). The secondary diodes D2 and D3 are conducting in this mode. Thus the magnetizing inductor voltages vLm1=-nVo2 and vLm2=nVo1. The magnetizing currents iLm1 and iLm2 decrease and increases respectively. Since the switch currents iQ2 and iQ3 are both negative in this mode, switches Q2 and Q3 can be turned on in this interval to realize ZVS. This mode ends at time t6 when Q2 and Q3 are turned on. Mode 7 [t6≤t<t7]: At time t6, Q2 and Q3 are both turned on at ZVS (since iLr1(t6)>0 and iLr2(t6)<0). The rectifier diodes D2 and D3 are conducting in this interval and the magnetizing inductor voltages vLm1=-nVo2 and vLm2=nVo1. The magnetizing current iLm1 decreases linearly with the slope of -nVo2/Lm. Likewise, the inductor current iLm2 increases linearly with the slope of nVo1/Lm. Lr1 and Cr1 are resonant with the applied voltage -nVo2 in circuit 1 and Lr2 and Cr2 are resonant with the applied voltage Vin-nVo1 in circuit 2. The resonant inductor currents and capacitor voltages during this interval are expressed as: nV − v (t ) t − t6 t − t6 + iLr1 (t6 ) cos iLr1 (t ) = o 2 Cr1 6 sin (16) Lr / Cr Lr Cr Lr Cr vQ 4, ds (t ) = vCoss 4 (t ) ≈ iLr 2 (t ) = Vin − nVo1 − vCr 2 (t6 ) Lr / Cr sin t − t6 Lr Cr + iLr 2 (t6 ) cos vCr1 (t ) = nVo 2 − [nVo 2 − vCr1 (t6 )] cos t − t6 (17) Lr Cr t − t6 Lr Cr (18) t − t6 L + iLr1 (t6 ) r sin Cr Lr Cr vCr 2 (t ) = Vin − nVo1 − [Vin − nVo1 − vCr1 (t6 )] cos t − t6 L + iLr 2 (t6 ) r sin Cr Lr Cr t − t6 Lr Cr (19) The resonant inductor current iLr1 decreases and iLr2 increases. In circuit 1, the energy stored in resonant inductance Lr1 is transferred to output voltage Vo2 through Cr1, Lr1, T1 and D2. In circuit 2, the power is transferred from input terminal voltage Vin to output voltage Vo1 through Cr2, Lr2, T2 and D3. This mode ends at time t7 when iLm1=iLr1 and iLm2=iLr2. Then diode currents iD2=iD3=0 and all diodes D1~D4 are off. Mode 8 [t7≤t<t0]: This mode starts at t7 when iLm1=iLr1 and iLm2=iLr2. Thus all rectifier diodes D1~D4 are off. Since Q2 and Q3 are still conducting, the components Cr1, Lr1 and Lm1 in circuit 1 are resonant. Likewise, Cr2, Lr2 and Lm2 in circuit 2 are resonant in this interval. The resonant inductor currents and capacitor voltages during this interval are expressed as: vCr1 (t7 ) t − t7 sin iLr1 (t ) = − ( Lr + Lm ) / Cr ( Lr + Lm )Cr (20) t − t7 + iLr1 (t7 ) cos ( Lr + Lm )Cr iLr 2 (t ) = Vin − vCr 2 (t7 ) ( Lr + Lm ) / Cr + iLr 2 (t7 ) cos sin t − t7 ( Lr + Lm )Cr t − t7 (21) t − t7 ( Lr + Lm )C r L + Lm t − t7 sin + i Lr1 (t 7 ) r Cr ( Lr + Lm )C r vCr 2 (t ) = Vin − [Vin − vCr 2 (t7 )] cos (22) t − t7 ( Lr + Lm )Cr L + Lm t − t7 + iLr 2 (t7 ) r sin Cr ( Lr + Lm )Cr (23) In this mode, the resonant inductor current iLr1=iLm1 and iLr2=iLm2. This mode ends at time t0 when switches Q2 and Q3 are turned off. Then one switching cycle is completed. IV. The root-mean-square (rms) value of the fundamental input voltage and input current can be expressed as: VQ 2, f = 2Vin /π , iLr1, f = 2 I Lr1, f sin( 2πf s t − φ) ( Lr + Lm )Cr vCr1 (t ) = vCr1 (t 7 ) cos (b) Fig. 4 Each LLC converter (a) equivalent circuit (b) resonant tank with fundamental switching frequency. SYSTEM ANALYSIS AND DESIGN EXAMPLE A. System Analysis The output voltage of the adopted converter is controlled with the pulse frequency modulation with 50% duty cycle for each power switch. The fundamental harmonic analysis is used to derive the dc voltage conversion ratio. The power transfer from input terminal to output load through the resonant tank is associated to the fundamental switching frequency. Thus the harmonics of the switching frequency are neglected in the following system analysis. Fig. 4(a) shows the equivalent circuit for each converter module. Since the duty cycle of switches Q1 and Q2 is 0.5, the input voltage to the resonant tank vQ2,ds is a square waveform between 0 and Vin. Based on the Fourier series analysis, the input voltage vQ2,ds can be given as: V 2Vin vQ 2, ds = in + ∑ sin( 2πmf s t ) (24) 2 m =1,3,5... mπ where ILr1,f and φ are the rms value and phase shift of fundamental input current iLr1,f. The output side of the proposed converter is driven by a quasi-sinusoidal current. If the inductor current iLr1>iLm1, the rectifier diode D1 is conducting and vLm1=nVo1. If iLr1<iLm1, then vLm1=-nVo2. We assumed that the time intervals in modes 1, 2, 5 and 6 can be neglected, the transformer primary voltage is a quasi-square waveform and can be expressed as: 2nVo vLm1 = ∑ sin( 2πmf s t − θm ) (26) m =1,3 ,5... mπ where θm is the phase angle of m-th harmonic frequency. The rms value of the fundamental primary voltage is derived as vLm1, f = 2 nVo / π . Thus, the load resistance reflected to the transformer primary side is give as: v Lm1, f 4n 2 = 2 Ro Rac = (27) iLr1, f π Therefore the ac resonant tank is excited by an effectively sinusoidal input voltage VQ2,f and drives an effective resistive road Rac. Fig. 4(b) shows the ac equivalent circuit. The input impedance of the resonant tank is given as: VQ 2, f ( s ) 1 sLm Rac Z in ( s ) = = + sLr + (28) I Lr1, f ( s ) sCr sLm + Rac The ac voltage gain related to the switching frequency is derived as: sLm Rac sLm + Rac 1 (29) | Gac ( f ) |=| |= 2 Z in ( s ) fr 2 f f [1 + k (1 − 2 )] + Q 2 ( s − r ) 2 fr fs fs where k=Lr/Lm, Q = (a) (25) Zo = Rac Lr /Cr Rac and f r = 1 / 2π Lr Cr . Under no-load condition (Rac=∞), Q=0 and fs=∞, the minimum ac voltage gain at no-load condition is derived as: 1 | Gac ( f ) | NL,f s = ∞ = (30) (1 + k ) Thus the proposed converter can be controlled at no load condition if the design minimum voltage gain at maximum input voltage meets the following condition. Gdc, min = 2n(Vo / 2 + V f ) Vin , max > 1 (1 + k ) (31) where Vf is the voltage drop on rectifier diodes D1~D4. Fig. 5 Laboratory prototype circuit of the proposed converter. Fig. 7 Measured waveforms of gate and drain voltages at 100% load (a) switches Q1 and Q2 (b) switches Q3 and Q4. V. EXPERIMENTAL RESULTS Experimental results based on a 960W laboratory prototype for server power supply unit were presented to verify the effectiveness of the proposed converter. The circuit parameters of the laboratory prototype with 960W rated power are derived in this section and shown in Fig. 5. The front stage of the proposed converter is a PFC boost converter to supply the stable 390V input terminal voltage. Fig. 6 shows the measured gate voltages of four power switches in the proposed converter. Fig. 7 shows the gate voltages and drain voltages of Q1~Q4 at full load condition (Po=960W). It is clear that the drain voltage has been decreased to zero before the gate voltage is high. Thus the ZVS turn-on of switches is realized and the switching losses on power switches can be reduced. Fig. 8 shows the gate voltage, drain voltage and switch current of switch Q1 at 100% of full load conditions. Fig. 9 shows the measured waveforms vQ1,gs, vCr1, iLr1, vCr2 and iLr2 at 100% of full load conditions. Fig. 6 Measured gate voltages of switches Q1~Q4 at light load. 10V 200V vQ1,ds Fig. 8 Measured waveforms of gate voltage, drain voltage and switch current of switch Q1 at 100% load (Po=960W). 10V vQ1,gs 10V vQ2,gs 10A 400V 200V vQ2,ds 400V 2 s/div 10A (a) vQ3,ds vQ3,gs Fig. 9 Measured waveforms of gate voltage vQ1,gs, resonant capacitor voltages and resonant inductor currents at 100% load (Po=960W). vQ4,ds vQ4,gs 2 s/div (b) Fig. 10 illustrates the measured waveforms of gate voltage vQ1,gs and diode currents iD1~iD4 at 100% of full loads. The measured gate voltage vQ1,gs and output capacitor voltages Vo1 and Vo2 at 100% of full load are shown in Fig. 11. Fig. 12 illustrates the measured results of vQ1,gs, iD1+iD3, iD2+iD4 and io at full load. We can observe that two resultant currents iD1+iD3, iD2+iD4 before output capacitors are balanced. secondary winding in the conventional center-tapped rectifier and the voltage stress of output diode is clamped to output terminal voltage instead of two times of output voltage in the conventional center-tapped rectifier. The fundamental harmonic analysis method is adopted to derive the voltage conversion ratio. The proposed converter can also regulate output voltage at no-load condition with the properly voltage gain design. The design procedure and design example are provided to obtain the component parameters of the proposed converter. Finally experiments based on a 960W prototype are provided to verify the effectiveness of the converter. Fig. 10 Measured waveforms of gate voltage vQ1,gs and secondary diode currents iD1~iD4 at 100% load (Po=960W). Fig. 11 Measured waveforms of gate voltage and output capacitor voltages at at 100% load (Po=960W). Fig. 12 Measured waveforms of gate voltage, resultant diode currents before output capacitors and load current at 100% load. VI. CONCLUSION This paper presents a parallel LLC converter to share the load current and reduce the ripple current on the input side. Based on the designed high voltage gain, the switching frequency is less than the series resonant frequency at full load. Thus the power switches are turned on at ZVS and rectifier diodes are turned off at ZCS. The switching loss on power switches is reduced and reverse recovery current on rectifier diodes is eliminated. The output voltage doubler topology is used in the secondary side to reduce the REFERENCES [1] R. Steigerwald, “A comparison of half bridge resonant converter topologies,” in Proceedings of IEEE IAS, pp. 135-144, 1987. [2] A. K. S. Bhat, “Analysis and design of a modified series resonant converter,” IEEE Trans. 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