Download A New Wave of CMOS Power Amplifier Innovations: Fusing Digital

A New Wave of CMOS Power Amplifier Innovations: Fusing Digital
and Analog Techniques with Large Signal RF Operations
(Invited paper)
Shouhei Kousai1, Kohei Onizuka1, Song Hu2, Hua Wang2, and Ali Hajimiri3
1
Toshiba Corporation, Kawasaki, Japan, 2Georgia Institute of Technology, Atlanta, GA, USA,
3
California Institute of Technology, Pasadena, CA, USA
Abstract —The RF power amplifier (PA) is typically the
most power hungry and area consuming block in a wireless
transceiver system. A viable RF PA solution should offer
competitive power and area efficiency while maintaining
high-performance large-signal RF operations. Fully
integrated RF PA in CMOS has been an area of active
research and development over the past years. Recently,
there has been a surge of interest to leverage the mixed-mode,
analog and digital, computational and signal processing
capability in CMOS to radically enhance RF CMOS PA
solutions and offer unique functionalities in parallel. This
paper reviews several recently reported circuit design
techniques of CMOS PAs. All of these techniques take
advantage of computation and integration advantages of
CMOS process and can potentially lead to competitive PA
solutions compared to traditional III-V HBT PA solutions.
Index Terms — CMOS power amplifiers, linearity
improvement, impedance tuning, back-off efficiency, digital
PA.
I. INTRODUCTION
The growing demand for higher data-rate and longer
battery life has posed increasingly stringent performance
requirements on the mobile handset transceivers. The
power amplifier (PA) is often considered as one of the
most critical building blocks in a wireless system. Serving
as the interface between the radio frequency (RF) system
and the antenna, PA’s performance generally has
significant effect on the entire transmitter metrics, e.g., the
output power level, power efficiency, bandwidth, and
signal fidelity, which therefore significantly impact the
overall quality of the wireless link. Moreover, due to its
large-signal and high-power operation, PA designs often
encounter unique challenges and trade-offs, which deserve
special attentions (Table I).
Traditionally, III-V heterojunction bipolar transistors
(HBTs) based solutions have dominated the high-power
wireless PA market, e.g., mobile handsets, due to the
superior III-V device performance. Such solutions offer
both better device performance as well as cost
effectiveness [1]. Multi-Chip-Module (MCM) is a
common approach in an HBT PA. Typically, it is
composed of a dedicated III-V HBT die with the power
transistors, a CMOS IC as the PA controller, and discrete
components for passive elements; this solution often
978-1-4799-3286-3/14/$31.00 ©2014 IEEE
TABLE I
CHALLENGES IN RF-PA AND THEIR SOLUTIONS
Challenges
Techniques
Linearity
(Amplitude/Phase)
Peak Power Efficiency
Multi-Chip-Module (MCM) [2], Whole
CMOS Integration [7]
DPD [10-11], Feed-Forward [23],
Feedback [24-25]
Switching-Mode [10], LINC [21]
Back-Off Power
Efficiency (Large PAPR
Signal)
Doherty [12-15], EER [16-17], ET [11,18],
Class-G [19], Out-Phasing [20-21],
High/Low Power Dual Mode [23-25]
Module Size/Cost
Robustness Against
Antenna Load
Mismatches and Freq.
Dependence
Reliability
Load Detection and
Tuning
[27-30]
Wideband Matching
[5]
Quadrature PA [6]
SOI Device Stacking [32]
achieves an excellent cost per performance [2]. However,
the occupied footprint is often an issue for the HBT/MCM
solution. Since the RF front-end typically requires more
area than the transceiver. The MCM approach exacerbates
this issue. In addition, due to the recent demand of multiband operation [3] and immunity to antenna proximity
effects [4], wideband matching network [5] and/or
quadrature balanced topology [6] are adopted by HBT PA
designs to achieve robust operation against frequency
variations and antenna load mismatches. However, these
approaches often come with the cost of even larger
footprint and compromised power efficiency.
On the other hand, Complementary Metal–Oxide–
Semiconductor (CMOS) PA is emerging as an arguably
competitive solution; CMOS based solutions often feature
one-chip full PA integration, resulting in a smaller
footprint and thus simplified front-end assembly [7].
Most importantly, CMOS platforms offer unparalleled
advantages of on-chip signal signal processing and
computation [8], which can be exploited to tremendously
enhance the PA performance while maintiaing low cost
and small footprint. Leveraging all these unique features
of CMOS processes has recently transformed the PA
design philosophy and resulted in a paradigm-shift in the
design space. As a result, advanced CMOS PA design has
now expanded its scope from a standalone RF circuit
building block to a complex mixed-signal/mixed-mode RF
system with orchestrated collaboration among analog,
digital, and large-signal RF operations.
The purpose of this paper is to review this recent wave
of CMOS PA innovations, closely in line with the mixedsignal RF design paradigm shift. In particular, in the
following sections, we will focus our discussions on the
new techniques addressing several major PA designs
aspects including linearization, frequency dependence,
load variation, and back-off/peak efficiency enhancement.
Exemplary implementations will be demonstrated with
measurement results. Finally, a concluding remark will
summarize this review.
II. PA LINEARIZATION WITH SELF-CONTAINED MIXEDSIGNAL FEEDBACK LOOP
The high throughputs in modern wireless links, such as
3G WCDMA and 4G LTE standards, have led to the
prevalence of spectrally-efficient modulations schemes.
These schemes require complex digital modulations with
high peak-to-average ratio (PAPR), with drastically
different amplitude/phase settings for different symbols
(e.g. QAM). Moreover, the resulting close symbol spacing
on the constellation map also calls for a high signal-tonoise -distortion ratio (SNDR). As a result, the PA needs
to preserve the high signal fidelity while performing
efficient power amplification. Unfortunately, CMOS
devices often have poorer linearity than III-V HBTs
largely due to the nonlinear gate capacitance [9].
Therefore, linearization technique is a must for viable
CMOS-PA solutions.
Many linearization techniques have been proposed.
digital pre-distortion (DPD) [10-11] is a widely used
method, as it is compatible with various PA architectures
[12-21]. DPD requires a global feedback loop from the PA
output to the digital baseband to compute and calibrate the
distorted symbols. Therefore, such solution tends to be
more suitable for fully integrated transceiver systems
rather than single-chip PA solutions. Other analog
+
-
PA
PA
(a)
(b)
PA
(c)
Fig. 1. Conceptual block diagrams of (a) feed-forward, (b)
feedback with baseband, and (c) PA closed loop. (Please
inter-change the sub-figure (a) and (b).
feedback methods, i.e., Cartesian and polar feedbacks,
also require similar global feedback loop for real-time
distortion cancellation [22] (Fig. 1.a). Besides the
complexity, the large group-delay inevitably limits the
loop bandwidth, posing a challenge in high data-rate
applications. A few feed-forward techniques have also
been proposed [23] (Fig. 1.b). Since they rely on
nonlinearity cancellation, their efficacy can be
compromised under P.V.T. and load condition variations.
To address this challenge, a self-contained PA closedloop feedback architecture has been recently reported [26].
Instead of employing a global feedback, an integrated
local feedback directly controls the final stage of a wattlevel CMOS PA and overcomes the bandwidth issue (Fig.
1.c). Although a stable feedback loop at RF can be
challenging, feedback with separate phase and amplitude
paths can be realized to avoid the stability issue.
Compared to the global feedback loops, this architecture
offers an inherent large bandwidth, since the loop contains
only PA in the signal path resulting in a small loop delay.
More details of implementation and measurement results
are described in the next section together with the antenna
impedance detection/tuning scheme.
III. ENHANCING PA ROBUSTNESS AGAINST ANTENNA
MISMATCHES WITH MIXED-SIGNAL POLAR LOAD
DETECTION/TUNING SCHEME
Automatic impedance detection and tuning can be an
ultimate solution to address load variation and frequency
dependence in PA operations. Conventional impedance
detection techniques only measure limited scalar load
information, e.g., |ΓAntenna|, with costly and bulky
components such as bidirectional coupler [27-29].
Therefore, these solutions cannot tune the antenna
impedance in a vector fashion to precisely and promptly
track the time-varying antenna mismatches.
The PA closed-loop architecture can be extended to
realize vector antenna load detection [30]. Figure 2(a)
summarizes this scheme, which linearizes PA by the selfcontained loop as well as detects the complex PA load
(ZPA) in a polar fashion. In the linearization mode, the
amplitude and phase of the PA output and reference
output are compared to generate the error signals of
amplitude (VA), and phase (V ). These signals are applied
to the PA so that the gain and phase shift are constant.
In the impedance detection-mode, impedance seen form
the PA (ZPA) can be detected by VA and V , which
corresponds polar impedance of magnitude and phase,
respectively. The feedback attenuation ratio (a<1), phase
offset ( ), gain of the reference amplifier (G m2), and the
reference impedance (Zref) can be chosen such that the
(a)
DA
Tuner
Attenuator
V
Amp. Det.
a
Phase Det.
Ref.
Amp.
Varactor
Phase det.
& comp.
Att. (a)
+
+
Offset
Burst Detector
+
V
Amp. Det.
Phase Det.
FPGA
VA
-
For ZRef
Trigger
+
Gm2
ZANT
PA
comparators
Ref.
Amp.
Tuner
ZPA
ZPA
PA
VA
Voltage det.
(b)
Gm1
Amplitude
det. & comp.
Zref
Comparators
Fig. 2. (a) Block diagram and (b) Implementation of the PA closed loop with antenna detection/tuning capabilities.
comparison results, VA and V , are both zero when the
load matches the optimal PA impedance (Zopt). The
resulting Zopt is then obtained as
(1),
where Gm1 is the gain of the main PA. The tuner can be
orthogonally controlled so that the amplitude and phase
detectors’ outputs are both set to zero, resulting in the
optimal impedance. This scheme can be expanded to
different frequency band by applying different attenuation
a and phase offsets for different operating frequency.
Additional benefit is the improved reliability, since the
PA is always loaded by its optimum impedance thus
avoiding device stressing due to load mismatch. Moreover,
it can enhance the PA back-off efficiency by providing the
optimum PA load during the back-off mode. For example,
at the back-off with a factor of b, the Gm of the PA can be
reduced to Gm1/b (b>1), by de-activating several numbers
of PA units and scaling down the activated gate width to
1/b. From eq. (1), the loop thus controls the ZPA to be
SP5T SOI SW
(2),
which is the optimal load impedance for the PA scaled by
1/b. Such proportionally increased load ensures that the
PA output maintains its maximum RF voltage swing and
thus the optimum efficiency due to the load-line
relationship.
Figure 2(b) shows the simplified schematic of the PA
closed-loop architecture with antenna load detection [30].
The phase detector and the comparator are composed of
limiter and mixer, where the phase offset can be applied
by changing DC offset. The on-chip burst detector detects
the beginning of the burst. This triggers the impedance
detection-mode, when the outputs of the amplitude
detector and phase detector are compared with their
references based on the optimal complex load. Based on
the comparison results, an off-chip FPGA updates the
0.5pF 1pF 0.12l 0.06l 1.5nH
@100W @100W
Fig. 3. The schematic of the tuner.
50
50
(a)
30
20
Tuning on
Tuning off
10
0
-180
(b)
40
40
PAE [%]
ZPA = bGm2Zrefe-j /(aGm1) = bZopt
Transmission lines
0.125 l @ 50W, 1.95GHz each
PAE [%]
Zopt = Gm2 Zref e-j / (aGm1),
tuner settings to set the optimal impedance. After the
impedance updates, the linearization mode is on until the
end of the burst. By repeating this tuning procedure, ZPA
thus converges to Zopt. In the linearization mode, V is
applied to the varactors at the PA input to control its phase
shift. The amplitude control is by applying VA to the gate
bias of the PA.
A low-loss impedance tuner is realized based on SOI
switches, benefiting from the recent advance in SOI
technology [31]. Fig. 3 shows the schematic of the tuner
board and the tuner performance. The tuner loss is
measured as 1-S112-S212 and ranges from 0.3 to 1.6dB,
while covering the impedance range within 6:1 VSWR.
The SOI switch is fabricated in the Toshiba 180nm SOI
CMOS process.
Fig. 4 shows the efficiency measurement result at
-90
0
90
Angle [Degrees]
30
20
Loop & tuning on
Loop & tuning off
10
180
0
-180
-90
0
90
180
Angle [Degrees]
Fig. 4. Measured PAE under mismatched load of VSWR = 2.5
with/without load tuning. (a) Peak PAE and (b) PAE at linearmode operation.
1.95GHz. The linear-mode PAE represents the efficiency
where the output spectrum satisfies the ACLR of 40dBc
with a WCDMA signal of 3.5dB PAPR. The loss of the
tuner is included for the results with tuning, and the PAclosed loop is activated with the impedance tuning. When
the VSWR is about 2.5, the peak PAE is kept more than
40% with tuning, whereas it varies from 28% to 45%
without tuning. The linear-mode PAE without the tuning
is 15% as the worst case, while more than 30% of PAE is
achieved when the tuning and PA-closed loop feedback
are enabled. When the PA unit is decreased from 10 to 5,
the drain efficiency is improved from 30% to 40%, at an
output power of 24dBm. In this case, the tuned impedance
is around 100W, aligned with eq. (2). Figs. 5(a) and 5(b)
show the microphotograph of the die and the impedance
tuner board, respectively. The PA chip is fabricated in a
130nm CMOS technology and the chip measures 1.6mm
by 2.2mm. Other measured performance without the tuner
is summarized in table II.
Fig. 5. (a) PA die micrograph and (b) impedance tuner board
TABLE II
PERFORMANCE SUMMERY
Frequency
1.95 GHz
Peak Output Power
30.8 dBm
Peak PAE
47%
WCDMA*1 Linear Output Power *2
27.9 dBm
WCDMA PAE @Linear
38 %
LTE *3 Linear Output Power *4
25.5 dBm
LTE PAE @Linear
30 %
*1 PAPR is 3.5dB. *2 ACLR is 40dB. *3 Bandwidth is 5MHz
and 1% PAPR is 5.0dB. *4 ACLR is 35dB.
(a)
MN
MN
PA IC
MN
To SAW filters
(different bands)
MN
(b)
SOI-Tuner-SW-IC
PA IC
Tuner
To SAW filters
(different bands)
SOI PA-Tuner-SW-IC
Fig. 6. Possible PA module implementations. (a) PA, band
selection switch and matching network for each band, and (b)
PA, tuner, and band selection switch.
In the future, the tuner could be implemented with the
band selection switch. Furthermore, the CMOS PA [32]
could be also be integrated with the tuner together on an
SOI chip, resulting in a small feature size with new
functionalities, as shown in Fig. 6.
IV. IMPROVING PEAK AND BACK-OFF POWER EFFICIENCY
This section reviews PA design techniques to improve
the peak and the back-off PA efficiency, both of which
governs the effective PA efficiency when high PAPR
signals are amplified in modern wireless schemes.
A. Digital Power Mixer Architecture with Mixed-Signal
Control Signals
The PA peak efficiency can be improved by exploiting
digitally modulated polar PAs (DPAs), whose PA core is
commonly implemented as multiple switching-mode unit
PA cells with independent digital controls. Major
advantages, including small feature size, integration to
transceiver ICs, high efficiency, high flexibilities and reconfigurability, make digital PAs even more attractive in
CMOS implementation [8]. However, DPAs typically
experience challenges in the output power dynamic range
and the out-of-band emission due to aliasing and
quantization noise.
The power mixer array architecture is reported to
address these challenges. Fig. 7 compares the power mixer
array with a DPA. In the conventional DPA, polar
modulation is employed, and the amplitude signal is
realized digitally by turning on proper number of binaryweighted unit PAs. This results in limited output power
range, quantization noise, and aliasing, leading to high
noise floor and out-of-band spurs. For a FDD system, the
noise and spurs at the receiving band is a critical issue.
Power mixer array can fundamentally reduce the DPA
noise and spurs by employing a novel mixed-mode
amplitude interpolation (Fig. 7(b)) [33]. First, the
baseband digital pulses are filtered (pulse-shaped) so that
the spurs are largely suppressed. Moreover, an analog
residue path is introduced to augment the amplitude
synthesis [33]. This analog residue enhances the fidelity of
the amplitude interpolation and thus suppresses both
quantization noise and the sampling images. In addition,
this analog residue path also extends the PA output power
range, since it can amplify a small baseband analog signal
to realize output power level less than one LSB of the
digital PA cell arrays. The measured spectrum shows the
reduced close-in noise and the suppressed aliasing signal
(Fig. 8). The aliasing signal shown in the figure is based
on the calculation. The power mixer array can produce
(a)
S
BB control
(b)
Phase (LO)
Analog
residue
S
Filtered
BB Pulse
Phase (LO)
30
10
w/o residue (Calc.)
w/ residue (Meas.)
(a)
-10
-30
-50
-70
-60 -40 -20 0
20 40 60
Frequency offset [MHz]
Output Power [dBm/kHz]
Output Power [dBm/kHz]
Fig. 7. Block diagrams of (a) DPA and (b) Power mixer array.
w/o residue (Meas.)
w/ residue (Meas.)
30
(b)
10
-10
-30
-50
-70
-1
-0.5
0
0.5
1
the time-varying envelope signal but only provides fixed
voltage levels instead (Fig 9(b)). When the input
amplitude is small, the DC-DC converter supplies a low
VDD voltage (Region I), while a high VDD level is used for
large input signal (Region II). To further reduce the cost
and feature size, a supply-path switching scheme is
reported [35] (Fig. 9(c)).
In this new scheme, instead of directly reducing the
supply voltage, the supply connections of the two PAs can
be reconfigured. For small input amplitude (Region I), the
two PAs are stacked across the supply VDD, so that the
effective supply voltage of each PA is halved (VDD/2). At
large input amplitude (Region II), the two PAs are
connected in parallel to the full supply VDD. Therefore,
this supply-path switching scheme achieves two effective
supply levels. No DC-DC convertor is needed and its
overhead and performance degradation are then eliminated.
Theoretically, the efficiency at the 6dB back-off is the
same as that at peak output power in this scheme.
Fig. 10 shows the block diagram of the supply-path
switching class-G in [35]. The PA1 and PA2 have the
same size and their outputs are combined at the output
transformers. This supply-path switching scheme can be
applied to improve the static back-off PA efficiency and
Frequency Offset [MHz]
Fig. 8. Measured spectrum of the power mixer array with(a) out-ofband spurs and (b) close-in noise floor.
(a)
Supply
Modulator
VDD
DC-DC
II
16QAM signal whose output power ranges from -75 dBm
to 26.4 dBm with EVM of less than 5%. The peak PAE of
26% at 1.8 GHz is measured with an output power of
+26.4dBm. The chip is implemented in a 180nm CMOS
technology (Fig. 14(a)).
I
I II I
VDD
(c)
I II I
B. Class-G PA with Supply Path Switching Architecture
The PA back-off efficiency is highly critical when
amplifying a high PAPR signal, since the actual PA output
power stays in the back-off region for most of the time.
Either supply or load modulation can be used to improve
PA back-off efficiency. Here we will first present the
supply modulation technique, and the load modulation is
discussed next with Doherty PA architecture as an
example.
Conventional supply modulation techniques include
Envelope Elimination and Restoration (EER) and Envelop
Tracking (ET), as shown in Fig. 9(a) [11, 16-18]. A DCDC converter is required in the supply modulator
exhibiting both loss and bandwidth limitation, and the
modulator’s external passive components further
complicate the design [34]. To relax the limitation on
bandwidth, the class-G PA concept is introduced [19],
where the DC-DC convertor does not have to fully track
(b)
I
II
Fig. 9. Conceptual block diagrams of (a) ET, (b) Class-G
with a DC-DC convertor, and (c) Class-G with supply-path
switching. No DC-DC convertor is needed in this case.
RF
input
Envelope
Det./Ctrl.
RF
output
PA1
Path
SWs
G2
G1
G2
G1
VDD
(Single
supply)
G1,G2
PA1 Bias
PA2
Fig. 10. Block diagram of the supply-path switching PA [32].
the PA efficiency with large PAPR signals, if the supply
switches are controlled dynamically based on the input
signal strength. This is performed by the on-chip envelope
detector/controller circuit (Fig. 11). The delay of this
envelope path is designed to be sufficiently small
compared to the symbol period of the modulation, e.g., a
20MHz LTE signal.
Fig. 12 shows the measurement result a CMOS
implementation of this technique. For a small PAPR
signals such as WCDMA, only static switching is applied,
and a significant back-off efficiency improvement (Fig.
12(a)). The PAE at the 6dB back-off is almost doubled
and is approximately the same as the PAE at the peak
output power, as expected. Fig. 12(b) shows the
measurement results with a large PAPR signal , i.e., a
20MHz bandwidth LTE signal. The envelope
detector/controller is activated to configure the supply
path dynamically for efficiency improvement. Fig. 13(b)
shows the die micrograph, and the chip is fully integrated
Bias selector
fc=200MH
To PA1
G1
To path
switches
G2
Coupler
Vref
Circuit
delay
1.30ns
0.45ns
Fig. 11. The detailed schematic of the envelope detector/controller.
PAE [%]
20
1.8GHz WCDMA
20
Half-VDD
Full-VDD
15
x2.0
6dB
10
(a)
5
0
5
10
15
20
Output power [dBm]
1.8GHz LTE-Advanced
20MHz 64QAM
Half-VDD
ET
12
Full-VDD
16
PAE [%]
25
8
x1.35
(b)
4
25
0
5
10
15
20
Output power [dBm]
25
Fig. 12. The measurement results of the supply-path switching classG PA. (a) Back-off efficiency improvement for a WCDMA signal
with static supply-patch configuration. (b) Efficiency improvement for
a large PAPR signal, i.e., an LTE-Advanced 20MHz signal, with
dynamic supply-path configuration by the envelope detector/controller
circuit.
(a)
Output
Network
Analog
BB
100mm
(b)
SWs
PA1
PA2
Power
Mixer Array
LO
Distributor
SW driver
Env.
Det. & Ctrl.
100mm
Fig. 13. Die micrographs of (a) Power mixer array, and (b) Supplypath switching PA.
in a 65nm CMOS technology. As shown, this supply-path
switching technique does not require DPD and DC-DC
convertor and is fully compatible with the PA closed loop
feedback technique, which can result in a self-contained,
low-cost, small feature sized PA module solution.
C. Digital Polar Doherty PA Architecture
The Doherty architecture has been widely used in base
stations as a means to achieve back-off efficiency
enhancement [13]. Recently, it has gained major interest
in CMOS PAs, since Doherty PA exhibits potentially
large modulation bandwidth and moderate implementation
overhead compared to other competitive techniques, e.g.,
ET and out-phasing. A Doherty PA typically consists of
two signal paths, i.e., the main and the auxiliary PAs [12],
which operate collectively to provide active load
modulation through an output λ/4 transmission line. This
ensures a constant output RF voltage swing for the main
PA even during the Pout back-off and thus achieves
improved back-off efficiency. Many existing CMOS
Doherty PAs are implemented using two RF amplifiers
biased at different modes (for example, class-AB and
class-C). Such designs typically suffer performance
degradation due to the imperfect cooperation between the
main and auxiliary PA [13-15]. Specifically, the auxiliary
PA turning-on point and the relative gain between the two
PAs achieved in practice can rarely match the desired
relationship in the ideal Doherty operation. Though a few
analog techniques have been proposed, e.g., asymmetrical
main/auxiliary PAs [14] and dynamic biasing [15], this
imperfect two-path cooperation still poses significant
challenges.
To address this issue, a digital Doherty polar PA
architecture is presented in [36] (Fig. 14). Here, the main
and auxiliary PAs are realized as two RF digital-to-analog
convertors (RF-DACs) with digitally programmable and
precisely controlled gain settings. Thus, this architecture
can accurately define the turning-on point of the auxiliary
PA as well as the relative gain between the two PA paths.
Moreover, these gain settings also offer reprogrammability and optimum performance tuning. As a
result, the digital Doherty PA can achieve a superior
performance over its non-digital counterparts.
This digital Doherty PA adopts the polar architecture
(Fig. 14). The phase modulated (PM) RF input is first split
into two signals with 90° phase difference by the input
passive network. These two RF signals are then separately
amplified in the two PA paths, and the outputs are
combined by the output transformer-based passive
network. The output network simultaneously performs
Doherty active load modulation, impedance down-scaling,
A Compact Broadband Digital Doherty Polar
Power Amplifier Chip in Bulk CMOS
Quadrature
Generation
(90⁰ Shift)
×1
×2
0° RF
TM 1
×16
VDD
In+
Doherty Output
Network
Main PA Path
Sub-PA
RF
Input
(PM)
2:2
k1=0.75
InBit1_M
Bit4_M
90° RF
TM 2
Load
VDD
Bit0_M
1:2
k2=0.86
Bit0_A
One On-Chip
Inductor Footprint
Bit1_A
Bit4_A
IoutVctrl
Auxiliary PA Path
Baseband Input
(Amplitude Control)
Two On-Chip
Transformers
5-Bit Main
Control
5-Bit Aux.
Control
28.8µm×Weighting
VRF- /50nm
Fig. 14. A fully integrated digital Doherty polar PA in 65nm bulk CMOS [36].
Fig. 16. Measured PA efficiency with the 50Ω standard antenna load (a)
and a mismatched load VSWR=2 and ∠ΓL=-60°.
Sub-PA
42µm×Weighting
/260nm
VRF+
and differential to single-ended conversion [15]. The
digital code controls the two RF-DACs to turn on the
proper power cells and synthesize the desired amplitude
modulation (AM). High-efficiency switching PAs can be
employed as the power cells for efficiency enhancement.
Compared with other digital PAs, the back-off efficiency
of this design is enhanced by leveraging the Doherty
configuration. Moreover, it is demonstrated in [36] that
programming the gain of the two paths reconfigures the
active load modulation, which enables robust Doherty PA
performance even under antenna mismatch.
This fully integrated digital Doherty polar PA is realized
in a standard 65nm bulk CMOS process (Fig. 15). The PA
achieves its peak power of +27.3dBm at 3.82GHz. The
peak PA drain efficiency and PAE are 32.5% and 28.6%
at 3.6GHz. At 3.82/3.6GHz, the maximum efficiency
improvement compared with a class-B PA is 7.0/6.2% at 5.4/-4.6dB power back-off (PBO), respectively. Fig. 16
shows the PA drain efficiency versus the PBO level at
3.6GHz with 50Ω antenna load. Different measurement
points represent different AM control codes (X, Y)
meaning X and Y unit power cells turned on in the main
and auxiliary RF-DACs. At a given PBO level, the
optimum code can be chosen to achieve the best efficiency.
The PA is also measured with loads at the 2:1 VSWR
Iout+
Fig. 15. Die photo of the digital Doherty polar PA.
circle. Fig. 16 shows an example result with ∠ΓL=-60° at
3.6GHz. The back-off efficiency enhancement by the
Doherty operation is maintained when the PA is subject to
the load variations by digitally reprogramming the gain
settings of the two PA paths.
In the modulation testing, the optimum amplitude code
(X, Y) is set dynamically to generate the desired envelope
modulation signal without any AM-AM distortion. Thus,
no additional AM-AM linearization technique is needed.
Without any AM-PM pre-distortion, the measurements
achieve 3.5/4.7% rms EVM with +23.5/+22.1dBm
average power and 26.8/24.1% PA drain efficiency for the
QPSK (1MSym/s, PAPR=3.7dB) /16QAM (500kSym/s,
PAPR=5.4dB) signals. AM-PM pre-distortion can be
added to this digitally-intensive architecture in the future.
V. CONCLUSION
This paper reviews the recent technology paradigm shift
in CMOS PA development, which focuses on leveraging
the mixed-mode computational and signal processing
capability in CMOS process to radically enhance the RF
CMOS PA solutions and offer unique functionalities.
Several exemplar designs in line with this design
methodology change are shown to demonstrate the
enhancement in several major PA performance aspects,
including linearization, frequency dependence, load
variation, and back-off/peak efficiency enhancement.
For modern and future RF front-ends, a desired PA
solution should offer multi-mode/multi-band operations,
compatibility with various wireless standards, and
adaptability to radiation environment changes, all within
stringent size and cost specifications. By exploiting
CMOS mixed-mode signal processing and integration
capability, CMOS based PAs might offer an overall
superior solution than III-V HBT PAs. In addition, to
avoid adding additional complexity to the RF front-ends,
CMOS PA solutions with self-contained performance
enhancement circuitry or architecture are highly preferred.
These solutions may potentially lead to universal mixedmode CMOS PAs with cross-platform compatibility to
match the fast-evolving wireless systems.
ACKNOWLEDGEMENT
The authors would like to thank for S. Otaka, M.
Nagaoka, Y. Kuriyama, T. Yamaguchi of Toshiba
Corporation for their useful suggestions.
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