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Overview of LECTURE 5
A circuit usually slows down due to energy loss through parasitic resistances and
capacitances.
1. PARASITIC CAPACITANCES
Look at the structure given below. The polysilicon and the insulator and the channel form
a parallel plate capacitance.
ox 
The gate oxide capacitance is determined by: C
 *SiO
2
t
where  is the permittivity
of Silicon Dioxide and t is the thickness of the insulator in Angstrom.
0.345
Cox 
t ( A)
Cox is the gate capacitance per unit area.
*  0 r
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2. Assume we have a transistor,
From drawing, LD is the lateral diffusion of the source or the drain underneath the gate,
ΔW is the oxide encroachment underneath the gate area. Therefore transistor geometry is
given by:
L
L
 2 LD
effective
drawn
W
W
 2W
effective
drawn
A
L
*W
effective
effective
effective
And the capacitances are given as:
C1
C2
C3
C4
C5
C6
C7
Gate to channel capacitance
Gate to Depletion capacitance
Gate to Bulk capacitance
Gate to Source capacitance
Gate to Drain capacitance
Source to Depletion capacitance
Drain to Depletion capacitance
Usually, the gate capacitance
C g  f (C1 , C 2 , C3 , C 4 , C5 ) ,
Cg 
Cox
* Effective Area
Cox is obtained from the process parameter in the process manual.
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Where WL is the effective gate area.
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3. DIFFUSION CAPACITANCE: DRAIN AND SOURCE CAPACITANCES
A source or drain of transistor geometry is shown below:
The drain and Source are like a cube embedded in the bulk. There are two parts to
recognize from this figure, the bottom capacitance and the surrounding capacitance.
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4. BOTTOM AND SIDE CAPACITANCE
Bottom capacitance = Area * Cj where Cj is the Junction Capacitance.
Side capacitance = Perimeter * Cjsw where Cjsw is the Sidewall Capacitance.
Total capacitance CD  C J * L *W  C JSW * (2 L  2W )
Value are given
Drain
Per unit area
Length &
Width
CD  CJ
Value are given
unit length
Drain Length and Width
AD
PD
 C JSW
V
V
[1  BD ] MJ
[1  BD ] MJSW
PB
PB
Note that MJ and MJSW are SPICE based parameters. AD and PD are the Drain, area and
perimeters
A better approximation can be obtained if you calculate CD and multiply it by K constant
(0.3-0.6) – for our process & 3.3V supply, K is roughly 0.4.
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5. FIRST ORDER MODEL OF TRANSISTOR (MOST BASIC SPICE MODEL)
First order model gives the Voltage threshold voltage as, VT  VTO   VSB
Where VT0 is the zero bias threshold voltage, γ is the body effect constant and VSB is the
source to bulk voltage differential.
SPICE parameters and some typical values are given at the end of this overview.
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6. CAPACITIVE LOADS IN A CMOS INVERTER
Assume that we have an inverter driving another inverter. The second inverter can be
considered a capacitive load as shown below.
The first order model capacitances include the drain capacitances of the driver and the
gate capacitances of the driven stage. Cw is the wiring capacitance.
Note: We usually neglect Cgsp and Cgsn while doing hand analysis of such circuits.
C L  Cdp  Cdn  C gp  C gn  Cw
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7. TRANSIENT ANALYSIS OF CAPACITIVE CIRCUITS
Of importance is the transient behavior of the inverter and the speed at which we are able
to drive such an inverter. We assume a step is applied to the input of the inverter. As
shown below the pmos is off and the nmos initially starts in saturation. As the load
capacitor discharges then Vout decreases until Vds =Vgs-Vt when the nmos enters the
linear region. Therefore there is two stages in calculating the fall time of this inverter.
How much time will it take for the output to swing from logic high to logic low?
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Definitions
In response to a step input, the rise and fall times at the output are defined as:
Time taken for 10% to 90% of
Vdd is called Rise Time or tr
Time taken for 90% to 10% of
Vdd is called Fall Time or tf
Now assume that a step input is
applied to an inverter
The propagation delay td is obtained by the 50% line as shown in the figure above. And
the propagation delay td can be calculated using the following equation:
td 
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t phl  t plh
2
Lecture#5 Overview
The fall time, tf
We will analyze the fall time in two steps, ie when the nmos is in saturation and then
when it is in linear region.
Initially when the step input is applied, the nmos is on and in saturation as
VGS-VTn<VDS, we have
I DN 
n
[Vgs  Vtn ]2
2
also,
C.dVds
I CAP 
dt
Merging the two equations,
n
2
[V gs  Vtn ]2 
t2
CdVds
dt
0.9VDD
2C.dVds
 [Vgs  Vtn ]2
VDDVtn n
 dt  
t1
t f1 
2C L (Vin  0.1Vdd )
 n (Vdd  Vtn ) 2
Similarly, for tf2, we have the transistor in the linear region,
t2
VDDVtn
t1
0.1VDD
 dt  
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C.dVds
 n [Vgs  Vtn ]Vds  V 2 ds
Lecture#5 Overview
10. RISE AND FALL TIME EQUATIONS
In order to get tfall (tf) we add tf2 and tf1.
tf 
2C L
V
( n  0.1)
[
 0.5 ln( 19  20n )] , n  tn
 nVdd (1  n ) (1  n )
Vdd
Grouping all the constants into K, the fall time is given as:
tf  K
CL
, where K is a constant between 3 and 4 depending on the process
 nVdd
If the same analysis are done for the trise (tr) we have
tr  K
CL
 pVdd
trise and tfall, are dependent on W/L, CL and Vdd. We can only change CL and W/L
through design, VDD depends on the process.
In order to equalize trise and tfall, make W p   rWn and  r 
n
p
Design Guidelines:
Keep the rise and fall times equal and smaller than the propagation delay of the
inverter. This will have an impact on speed and the power consumption of the
circuit.
Propagation Delay
The following factors influence the delay of the inverter:
•
•
•
•
•
Load Capacitance
Supply Voltage
Transistor Sizes
Junction Temperature
Input Transition Time
For any given process, we can express the delay (td) for an inverter as:
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CL
2n
t PHL = -------------------------------------- ---------------- + ln (3 – 4n )
K NVDD (1 – n ) ( 1 – n )
The same expression can be derived for tPLH
Assume normalized voltages
vin= Vin/ VDD
vo= Vo/ VDD
n = VTN/ VDD
p = VTP/ VDD
Since KN, VDD, KP, n,p are constants for a given process then the delay can be expressed
as:
C
t d  An L
n
The coefficient ‘An’ is obtained for a given process from analytical calculations or better
through SPICE Simulation. That is, for a known CL and n, we usually determine td(spice)
and then determine An. Once An is obtained, it can be used repeatedly for the same
process
An 
t d  spice n
CL
Summarizing then,
CL
–2p
tPLH = -------------------------------------- ----------------- + ln ( 3 + 4p )
KP VDD (1 + p ) (1 + p )
C A'
tP LH = --------L---------P---KP VDD
CL
( – 2) ( 1 + p )
tr = -------------------------------------- ---------------------------- + ln (19 + 20p )
K PVDD ( 1 + p ) (1 + p )
4C L A'P
tr = -------------------KP VDD
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All the previous equations involve the use of a step unit signal as input. However real-life
signals are often ramps. In that case we will use the following equation to incorporate the
effect of the slope of tr and tf:
First Order Model
t
t phl  t 2 phlstep  ( r )2
2
t plh  t 2 plhstep  (
td 
tf
2
)2
1
(t phl  t plh )
2
Alternative Delay Model (for the rise time)
t
V
tdr  tdrstep  f (1  2 p) , p  t
Vdd
6
ALTERNATIVE DELAY (tp) FORMULA
For the short channel transistor the following delay equation is more appropriate
C
1
tp  L (
)
2 P  N
Also in the short channel model the source resistance becomes important and it has to be
taken into account, since it affects both the current and the voltage threshold.
PLEASE NOTE: All models presented are approximate; we only use them as
guideline when implementing circuits. Accurate delays are obtained only through
SIMULATION.
tPHL and tf decrease with the increase of W/L of the NMOS
tPLH and tr decrease with the increase of W/L of the PMOS
The delay of the inverter increases with the increase of the input
transition times tr and tf
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SPICE models:
Level 1: Long Channel Equations - Very Simple
Level 2: Physical Model - Includes Velocity
Saturation and Threshold Variations
Level 3: Semi-Emperical - Based on curve fitting
to measured devices
Level 4 (BSIM): Emperical - Simple and Popular
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End of lecture #5
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