Download ECE 4340/5340

ECE 4340/5340
VLSI Circuit Design
fall 2007
Name:_____________________________________
due: Nov. 8.
SPICE simulation parameters: if not provided in the problem, You can use the default
values in SPICE itself or specify a good reasonable value suitable for the problem.
1. Design a resistive-load inverter with R = 1 kohm, such that VoL = 1.0V. The
enhancement-type nMOS driver transisitor has the following parameters:
VDD = 5.0V VTO=1.0V
 = 0.2 V1/2 = 0 nCox = 22.0 A/V2
a. Determine the required aspect ratio W/L
b. Determine VIL and VIH
c. Determine the noise margins NML and NMH
d. Conduct a SPICE simulation and find answers for a, b, c, from SPICE simulation.
2. For a complex logic function
(a) Implement the above function using a full static CMOS
(b) Can you use less than 10 transistors to implement the above function
ECE 4340 students do (a) only; ECE 5340 students do (a), (b).
3. Using Microwind to
(a) construct the layout of a CMOS three-input NAND gate
(b) conduct simulation based on your layout. You can add signals to the layout in
Microwind.
4. A CMOS inverter with the following device parameters:
nMOS VTO,n= 0.8V nCox = 50 A/V2
pMOS VTO,p= -1.0V pCox = 20 A/V2
The power supply voltage is VDD = 5V.
Both transistors have a channel length of Ln = Lp =1 m. The total output load
capacitance of the circuit is Cout = 2 pF, which is independent of transistor dimensions.
(a) Determine the channel width of the nMOS and the pMOS transistors such that the
switching threshold voltage is 2.2V and the output rise time is rise=5ns.
(b) Calculate the average propagation delay time p for the circuit designed in (a).
(c) Conduct a SPICE simulation of (a) and (b).
5. This problem is for ECE5430 students
a. In order to drive a large capacitance (CL = 20 pF) from a minimum size gate (with
input capacitance Ci = 10fF), you decide to introduce a two-staged buffer as shown in the
following figure. Assume that the propagation delay of a minimum size inverter is 70 ps.
Also assume that the input capacitance of a gate is proportional to its size. Determine the
sizing of the two additional buffer stages that will minimize the propagation delay.
b. If you could add any number of stages to achieve the minimum delay, how many
stages would you insert? What is the propagation delay in this case?