Download Channel Length Modulation

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Channel Length Modulation
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The equation describing the MOSFET
in saturation suggests that the device
acts as a current source.
– ID is constant and independent of
VDS.
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The effective channel length is
actually modulated by VDS.
– An increase in VDS causes the
depletions region at the drain junction
to grow.
– The length of the effective channel is
reduced.
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A more accurate equation describing
the saturation region must account for
this channel length modulation.
I D = I D (1 + λ V DS )
'
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Lambda is the channel length
modulation and is generally
proportional to the inverse of the
channel length.
Channel length modulation is more
pronounced in short channel devices.
Short channel devices are prone to
velocity saturation.
– Velocity saturation occurs when the
horizontal component of the E-field
(along the channel) reaches a critical
value.
– At this point the carriers collide.
Velocity Saturation
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The critical E-field at which
scattering effects occur depends on
the doping levels and the vertical
electric field applied.
Velocity saturation effects are less
pronounced in pMOS devices.
By increasing VDS the electrical field
in the channel ultimately reaches the
critical value and the carriers at the
drain become velocity saturated.
Further increasing VDS does not result
in increased ID. The current saturates
at IDSAT
The behavior of the MOS transistor is
better understood by analysis of the IV curves.
Sub-Threshold Conduction
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Ideally at VGS < VT, ID = 0.
The MOS device is partially
conducting for gate voltages below
the threshold voltage.
This is termed sub-threshold or weak
inversion conduction.
In most digital applications the
presence of sub-threshold current is
undesirable. Why?
….most digital applications …. Does
this mean some digital applications
can tolerate sub-threshold currents?
A Sub-threshold digital circuit
manages to satisfy the ultra-low
power requirement. How?
•
What type of digital applications can
benefit from this ultra low power
design approach?
Dynamic Behaviour
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Dynamic response of a MOSFET is a
function of time required to charge or
discharge the parasitic capacitances.
Designers must understand these intrinsic
parasitic capacitances.
They originate from :
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The basic MOS structure
The channel changes and
The depletion regions of the reverse biased
pn junctions of the drain and source
regions.
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The MOS structure capacitances include:
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The gate oxide capacitance Cox which has
three components whose sum can be
represented by Cg
The gate capacitance has as components:
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The topological structure of the transistor
and
The channel charge.
Creation of the source and drain regions is
not a perfect art and we thus have
instances where the source and drain
extend below the oxide each by an amount
xd.
The effective channel length of the
transistor thus becomes shorter than the
drawn length (Ld).
The drawn length is altered by 2xd.
This lateral diffusion gives rise to parasitic
capacitance between gate and
source/drain.
MOS Dynamic Behaviour
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This is termed the overlap capacitance
and is linear with a fixed value of:
CGSOverlap=CGDOverlap=CoxXdW
The above capacitances are voltage
independent. They are a result of
MOS structural arrangement.
Other parasitics present are result of
the interaction between the gate
voltage and the channel charge.
Recall that the channel region is
connected to the source, the drain and
the substrate.
The gate to channel capacitance is
distributed and voltage dependent.
MOS Dynamic Behaviour
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A simplified view can be obtained by
analyzing these capacitances at the
device’s region of operation: cut-off,
linear and saturation.
In cut-off the surface is not inverted.
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– The gate to channel and gate to drain
capacitances are both 0.
– There is no conducting channel to
link the surface to the source and to
the drain.
– CGS=CGD=0; CGB=CoxWL
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In linear mode the inverted channel
extends from the source to the drain.
The substrate is shielded from the
gate electric field, thus CGB=0.
The distributed gate to channel
capacitance can be viewed as being
shared equally between the source
and drain regions and CGS is:
– CGS=CGD=1/2CoxWL
When the MOSFET is operating in
Saturation region the inversion layer
on the surface does not extend to the
drain, but is pinched off.
– CGD = 0
– The source is linked to the conducting
channel.
– Its shielding effect force the gate to
substrate capacitance to 0.
– CGS = 2/3CoxWL
MOS Dynamic Capacitances
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The voltage dependent sourcesubstrate and drain-substrate junction
capacitances are due to the depletion
charge surrounding the respective
source or drain diffusion regions
embedded in the substrate.