Download Simulating Charge Injection in MOS Analog Circuits

Simulating ChargeInjection in MOSAnalog Circuits
J. Eric Bracken
May, 1989
Department
of Electrical and Computer
Engineering
CarnegieMellonUniversity
Advisor: L. RichardCarley
Copyright © 1989J. Eric Bracken
Submitted
in partial fulfillment of the requirements
for the degreeof
Masterof Sciencein Electrical Engineering
Table of Contents
1 Introduction
2 Model Physics
2.1 Assumptions
2.2 Governing Equations
2.3 Charge PumpingModel
2.4 BoundaryConditions
2.5 Extrinsic Elementsand Terminal Currents
2.5.1 Overlap capacitances
2.5.2 Junction capacitances
2.5.3 Terminalcurrents
3 Numerical Methods
3.1 TheESIM(Explicit Integration) Program
3.2 TheFETuccine(Fully Implicit) Program
4 Experimental Procedures
5 Results
5.1 Preliminaries
5.2 ExperimentalResults
5.2.1 Chargeinjection
5.2.2 Chargepumping
5.3 The Charge PumpingModel
5.4 The Needfor a Non-Quasistatic Model
6 Conclusions
1
5
5
6
8
9
10
10
12
13
14
14
16
17
20
20
21
21
23
23
26
28
1 Introduction
A major trend in modernanalog MOScircuits
is the use of charge to represent analog data.
This is a characteristic of switched-capacitor circuits,
filters,
which are used in frequency-selective
A/D and D/A converters, precision gain amplifiers,
measurementinstruments. In such circuits,
and integrated
capacitance
analog signals are converted from the voltage
domain into the charge domain by applying a voltage to a capacitor through an MOSswitch
(see Figure 1). With the switch closed (gate voltage "high" for the NMOS
device shown),
voltage V~, produces a charge CV~, on the top plate of the capacitor.
If the switch is
subsequently opened(by dropping the gate voltage below threshold), this charge will ideally
remain on the capacitor, whereit can then be processedin a variety of ways.
Vin /
"~.
)
~
~
Chold
Figure 1: Sample-and-holdcircuit
The principal
limitations
to the accuracy of this schemecomefrom the MOSswitch. When
the FETis turned on it suffers from widebandthermal noise, muchlike a resistor. This causes
randomfluctuations
in the device’s drain current, which are continuously integrated by the
capacitor.. Whenthe FETis later turned off, the integral of the noise current is "sampled"onto
the capacitor. Thus an error componentis added to the signal charge. These effects can be
adequatelymodeledby standardlinear systemtheory; see [6] for details.
Whenthe MOSswitch turns off,
two other error sources manifest themselves. As the gate
voltage swings quickly from one supply rail to the other, charge is driven off the bottom plate of
the gate overlap capacitance onto the data storage node. This is called clock feedthrough.
Simultaneously, another effect called charge injection is in operation. This is causedby the
mobile charge in the FET’s inversion layer, which is forced to leave the channel whenthe gate
voltage changes. Any inversion charge that escapes to the data node causes an additional
error in the stored charge. This report is concernedwith the computationof errors due to clock
feedthroughand charge injection.
Theseeffects are muchmoredifficult
to modelthan noise. The main difficulty
keep an accurate accounting of where the charge goes during turn-off.
is trying to
The MOSFET
is still
conducting to someextent until the gate voltage goes well below threshold. Thus, charge is
able to redistribute itself
from source to drain in a complicated fashion. There is also the
possibility of driving somechargeinto the substrate (see below). To consider these possibilities
in moredetail, refer to the cross section of an NMOS
transistor in Figure 2.
G
l
inversion
I
,~.~,.’,’-,’.,’...".~p
layer
o ~v",",’,’v,".~ 9
I
+
p bulk
I
Figure 2: Cross section of an NMOS
transistor
For gate voltages abovethreshold, an inversion layer (consisting of mobile electrons) will
established beneaththe thin oxide in order to mirror the positive charge on the gate. If the gate
voltage begins to drop, then fewer electrons will be neededto mirror the reducedgate charge;
the resulting electrostatic
imbalance impels excess electrons to leave the inversion layer.
During normal operation the source and drain voltages are greater than or equal to the
substrate potential, and so excesselectrons are preferentially attracted towardthese terminals.
(Any electrons leaving through the source and drain will result in charge injection errors.)
However,the source and drain have only a limited capability for removingexcess charge. The
limitation stemsfrom the resistive nature of the channel. The flow of electrons from the center
of the channel toward the drain and source constitutes
a current,
which causes an ohmic
potential drop from the endsof the channel to the center. If this potential drop becomes
large
enough,the potential at the middle of the channelmayactually go belowthe substrate potential.
If this occurs, electrons will be injected from the inversion layer directly into the substrate,
instead of to the sourceor drain. This effect is called chargepumping,and wasfirst reported by
Brugler and Jespers [2]. Fromthe point of view of the analog circuit designer, charge pumping
maybe a benevolenteffect since it reducesthe charge injected to the data node. (Or it maybe
undesirable, if an "open-loop" schemeto cancel the expectedcharge injection is being used.)
The complexity of the charge injection process makesit impossible to study analytically.
Thus, a circuit designer is forced to use somesort of CADtool to obtain accurate predictions of
switch-inducederrors. Unfortunately, existing CADtools are mostly unsuitable for makingthese
predictions. Circuit simulators typically use "compact" charge modelsfor the MOSFET
[13, 27]
which are derived under the quasi-static approximation. In this approximation, terminal voltages
are assumed
to be slowly-varying (how "slowly" has not yet been well quantified), which allows
the conditions inside the channel to be determinedexactly from steady-state analysis, and then
integrated out. The resulting
models predict terminal currents which dependonly on the
instantaneous values of the terminal voltages. Thus, the model currents tend to changemore
abruptly then the currents in actual devices, whenthe terminal voltages are varying rapidly. But
the real problemwith quasi-static modelsis the inherent inaccuracy in assumingthat conditions
in the channel of the MOSFET
always have time to relax to their steady-state values. In
practice this assumptioncan be violated easily, especially whenoperating long devices at high
switching speeds.
At the other end of the spectrum are two-dimensional simulators.
These programs can
simulate a semiconductordevice at the physical level, keeping track of carrier concentrations
and field
strengths throughout the device. Most available
programs (PISCES[20, 21],
MINIMOS
[24], etc.) simulate only a single semiconductordevice (or a single cross-section
silicon)
with very simple boundaryconditions. The programMEDUSA
[4, 3] does allow one to
mix two-dimensional physical modelswith arbitrarily
possibility
complexcircuits.
While this offers the
of simulating charge injection and clock feedthrough with great accuracy, this
approachis extremely computationally intensive, often requiring hours of CPUtime per device.
This limits
the size of the circuits
that can be simulated economically to perhaps a dozen
transistors.
To avoid these problems,someauthors[35, 25, 34] havetried to reducethe chargeinjection
problemto onearchetypalcircuit (suchas that in Figure3), whichis thenstudiedin detail with
specially written simulatorsandlaboratory measurements.
Thesestudies provideresults in the
formof tables andgraphsshowing
chargeinjection as a function of variouscircuit andexcitation
parameters.Suchvisual aids maybe useful to designersin certain applications, but it is
obviousthat not all circuits canbe reducedto sucha simplemodel.
V Gate
~
Vin
Figure3: Thearchetypalchargeinjection circuit
Attemptingto bridge the gap betweenhigh-efficiency and high-accuracysimulation, some
researchers [32, 17] have sought to develop non-quasi-static compactMOSmodels. These
modelsoffer substantial improvement
over quasi-static modelswith very little
increase in
simulationtime. In all the methods
proposed
to date, the inversionchargeprofile in the channel
is approximatedwith a weightedsumof position-dependentfunctions. Theweights for the
functions are themselves
functions of time; they are chosenby suitable variational principles.
Thesemodelshavetwo major problems.First, they makeuse of simplified device physics to
producetractable sets of differential equationsfor the weights. (Neither of these models
addresseschargepumpingeffects.) Second,in order to obtain sufficient accuracyit maybe
necessaryto use a large number
of functions in the approximation.This tends to counteractthe
advantage
of the variational approach.
This report describesanother techniquefor improvingthe efficiency of chargeinjection
modeling.It will present a non-quasi-static one-dimensional
modelof the MOSFET.
This model
takesa finite differencesapproach
by sectioningthe channelof the deviceinto manyelements,
and then simulating the flow of inversion charge from element to element. While this approach
is not new[12, 14, 34], previous efforts havebeenbasedon simplified versions of the governing
equations. A variety of physical effects are included in the present model to improve its
accuracy: mobility degradation due to high fields,
surface potential,
the nonlinear dependence
of bulk charge on
and substrate charge pumping. The performanceof the model is tested by
using it to simulate charge injection
in someswitched-capacitor circuits.
comparedto simulations with the program PISCESand to laboratory
The results are
measurementsfrom an
experimentaltest chip.
2 Model Physics
This section describes the physical equations that govern the one-dimensional MOSFET
model. The equations for an NMOS
transistor will be given; analogousexpressions hold for the
PMOS
device. Consider the schematic of an NMOS
transistor
shownin Figure 4. The direction
along the channelof the device (denotedby the variable x) will be referred to as the horizontal
direction, and the direction perpendicular to the oxide-semiconductorinterface (denoted by the
variable y) will be referred to as the vertical direction.
IG
S
D
/~’/"/"~~,.".~i’tP
o~y 1,-"/"/"./".~T’>, Q
!
,"~,"...’~/"...~"
/’~’~
l e: [’./"..’~/’~ /’.~..’". .... ."~-=~,"
~ I D
]
I
I
IB
B(~
Figure 4: Definitions of coordinates and current orientations
2.1 Assumptions
The one-dimensional MOSFET
model is derived under the charge sheet approximation,
originally introduced by Brews[1]. In this model, the inversion layer is considered to be an
infinitesimally thin sheet of chargeat the oxide-semiconductor
interface. This is justified by the
fact that in the static equilibrium case, the vast majority of the electrons in the inversion layer are
concentrated in a narrow region--perhaps 30-300 angstromsin depths-beneath the gate oxide.
6
While this approximationis strictly
valid only for equilibrium, numerous
two-dimensional
transient simulationshaveindicated that the additional spreadingof the inversion layer can
usually be neglected.
It is also assumed
that the gradual channelapproximationholds within a portion of the
device’s channel;that is, the vertical component
of the electric field is assumed
to be much
larger than the horizontal component.This allows the two components
to be decoupledfrom
oneanother.Thevertical fields maybe usedto compute
surfacepotentials, while the horizontal
fields determinethe transport of mobile inversion charge. Note that the gradual channel
assumption
breaksdownin the regionsnear the sourceanddrain, wherelarge horizontal fields
maybe present (Figure 4). A true two-dimensionalsolution of Poisson’s equation in these
regionsis requiredif it is necessary
to knowtheir extentandthe potential dropacrossthem.It
is certainly also true that in deviceswith very short channels,the gradualchannelregion may
disappearaltogetherat high valuesof "Cos:to supporta large potential dropacrosssucha short
regionrequiresa large horizontalfield throughoutthe channel.This effect is not expectedto be
importantin passtransistors, since VDsis nearly zero during the entire turn-off transient.
Therefore, in the one-dimensionalmodelthe channellength is assumed
to be constant, and
lumpedmodelsof the sourceanddrain regions are used.
2.2 Governing Equations
Theprincipal goal of the simulationis to track the evolution of the inversion layer charge
profile over time. Let Ql(X,t) denotethe inversionlayer chargeper unit area. Thenthe continuity
equation
for QI is
OQI_ ~I + Jpump(X,t)
at ~x
(1)
Here, I(x,t) is the horizontal electron current per unit width (the width being the direction
perpendicular
to the pagein Figure4.) Notethat I(x,t) hasbeendefinedas flowingto the left in
Figure4. Jp,,,p(x,t) is the substratechargepumping
currentdensityat a point x in the channel.
ThehorizontalcurrentI(x,t) is givenby
l(x,t) = ~t4/, [-Qt ~ + ]~r -~-x
(2)
where~t#7is the effectivemobilityof electronsin the inversionlayer, ~) is the surfacepotential,
and Sr is the thermal voltage kT/q. Thefirst
term in (2) represents electron transport by drift,
while the secondrepresents electron diffusion. Note that gey is in general a function of the
vertical and horizontal electric field strengths in the device. The expressions governing the
mobility are [22, 30]
g~ -
go
(3)
1 + O~Eeff,
ver
t
and
(4)
gee= [1 + l’e
(~tlEhori=/Vsar)2]
Here, g0 representsthe surface mobility at low fields.
gl is the effective mobility including the
vertical field degradation, which is controlled by the modelparametere~. Ehomis the horizontal
electric field, andVsa
r is the saturationvelocity for electrons.Eeff, vert is the effective vertical field,
whichis approximated(as in [22])
E ~ve~ -
(a/2)QI + QI~
(5)
esi
Thesurface potential q~ is related to the chargedensity Qxand the externally applied gate-tobulk voltage Va~by Gauss’law:
-Cox(Va~ - Vy~ - ,) = Qr + Q~(~)
(6)
whereVe~is the flat-band voltage, Coxis the gate oxide capacitanceper unit area, and Q~(qs)
the bulk chargedensity per unit area. Physically, Q~consists (in depletion) of ionized acceptor
charge, and (in accumulation)of free hole charge. It is assumed
that the holes in the substrate
are so plentiful
and mobile that the charge Q~can react instantaneously to changesin surface
potential; thus Q~is explicitly
madea function of ~. The dependenceof Q~on q5 takes on a
particularly simple form if the substrate is uniformly dopedwith an impurity concentration Na;
then
Q~(~) = -(2q~siNA)~/z [~ - ~r + ~r exp(-~/~r)] ~/~ sgn((~)
Here, sgnO represents the signum function, ~sl is the permittivity
(7)
of silicon,
and q is the
magnitudeof the electron charge. Equation (7) can be derived from a one-dimensionalsolution
of Poisson’s equation in the vertical direction [31]. A plot of Q~versus ~ is shownin Figure 5.
This expression continuously models the depletion
and accumulation regions of device
operation, which is useful in simulations of charge pumping.
8
Figure 5: Bulk chargedensity versussurface potential
Asan alternative to (7), whichrelies on a uniformlydopedsubstrate,the quantity {2~ could
evaluatedversuse in an off-line preprocessingstep using a one-dimensional
Poissonequation
solver. Theresulting data couldbe stored in a look-uptable for the simulator. This approach
wouldpermit the modelingof non-uniformsubstrate dopingprofiles. (7) has beenusedin the
presentversionof the one-dimensional
modelfor simplicity.
2.3 Charge PumpingModel
A physically basedmodelfor the chargepumping
current is
+ {:rq dn]
Jt,,,nt, = l’t [qn(yo)E(Yz))
wheren(y) is electrondensity, E(y) is the vertical component
of the electric field, andYz~is
location of the depletionregion edgerelative to the surface. Unfortunately,this relationship
cannotbe usedin the one-dimensional
model,becauseof the lack of detailed informationabout
the vertical structure of the electric fields andcarrier concentrations.Theonly information
availableis Qj, the total electronchargeintegratedoverthe vertical direction, and~, the surface
potential. It is therefore necessaryto usean approximate,semi-empiricalmodelfor substrate
chargepumping,whichmakesuse of these quantities.
In the one-dimensional
model,the chargepumpingmechanism
is representedby a diode-like
nonlinearity. Thechargepumping
current is negligible whenthe surface potential is high. but
becomes
quite large as the surface potential drops belowzero. ,f~,,,,~,
is therefore made
proportionalto ¢x#(-~/Vm,t,)whereVt,,,,~ , is a modelparameter,whichis roughlyequalto
Also note that the chargepumping
current can only exist whenthere are still
electronspresent
in the channel;as theseelectronsare removed
J~,,,,~, shouldfall backtowardszero. Therefore
the completemodelis
’ exp(-~/V~,,mt,)
Jt, um~,= tpum~
wherett,,,,r
(8)
is anothermodelparameter,whichis addedto make(8) dimensionallycorrect.
Equation(8) has obvioussimilarities to the ideal diode equation, with the modification
allowingthe effective dopingto varydynamically.
2.4 BoundaryConditions
Theexternally applied sourceand drain voltages Vs~and Vz)n imposeDirichlet boundary
conditionson the valuesof Qt(x,t) and~(x,t) at the endsof the channel.In the presentmodel,it
is assumed
that the endsof the channelare in suchproximity to the sourceanddrain that they
can instantly exchangecharge with these terminals. (This neglects the regions of high
horizontal electric field nearthe sourceanddrain, whichwill slightly delaytheseexchanges.)
Also, drain-inducedbarder lowering effects are assumed
to be negligible, so that the drain
voltagedoesnot significantly affect the potential in the channelnearthe source,andvice-versa.
This permitsthe approximation
of setting the electronquasi-Fermi
potential equalto Vs~~
andVz)
at the appropriatechannelends.
Let Vc~denotethe electron quasi-Fermipotential (either Vs~or Vz)n) at oneend of the
channel.Thenthe surface potential at that endof the channelmaybe determinedfrom Gauss’
law:
--Co=(V~- VFn-- ¢P) = Qc(*,Vc~)
whereQc(~,Vc~)
= Q~+ Q~is the total channelcharge,givenby
~/z [~ + ~:r(e’~/*~- 1) + ~r(ni/N,4)Ze-Vc~/~’~
" (e*/~’r-1)] 1/2 sgn(~)
Qc= -(2qes~a)
(9)
(10)
Equation(10) is an "exact" solution for the total channelcharge,derivedfroman analysis
Poisson’sequationin the vertical direction (again for the caseof a uniformsubstrate)[31].
10
Again,(10) has beenusedfor simplicity in the initial evaluationof the model;ideally, a table
modelof Qcderivedfromsimulationsof realistic dopingprofiles wouldbe used.
After solving equation (9) for ~, Qz can be found by computingQc-Q~from (10) and(7).
Whenthe channel is in weakinversion, special care must be taken whenperforming this
subtractionto avoidloss of significanceerrors.
Theboundary
conditionsimplicitly define twocurrents, I s andIz~, whichflow fromthe channel
endsto the sourceanddrain terminals. Thesecurrents add andremovechargeat the endsof
the channelto assurethat (9) and(10) are satisfied. Thecomputation1s andIz~ will be
discussed
in the next section.
2.5 Extrinsic Elementsand Terminal Currents
This section deals with the parts of the one-dimensionalmodelthat are external to the
gradual channelregion. Thesefeatures of the modelform the interface betweenthe MOSFET
and the external world. Discussedin this section are the overlap capacitances,drain and
sourcejunction capacitances,
andthe evaluationof terminal currents.
2.5.1 Overlapcapacitances
Theoverlap capacitanceswerediscussedin Section1 as the causeof the clock feedthrough
effect.
The use of the term overlap capacitance is a misnomer,since there are three
components
to the total gate-to-draincapacitance,only oneof whichinvolves "overlap". First,
(see Figure 6) there is a true overlap capacitor Coyformedby the drain’s lateral diffusion
beneaththe thin oxide. Second,there are electric field lines whichoriginate on the gate, curve
throughthe field oxide, andterminate on the drain diffusion. Theygive rise to an external
fn’nging capacitance,C#. Third, if the channelof the MOSFET
is not strongly inverted, then the
field lines in the silicon maybe terminatedon the drain diffusion, insteadof on inversioncharge
or ionized bulk charge.This results in an internal fringing capacitance,Cif, whichis dependent
uponthe device’s operatingpoint. Thesethree capacitances
are parallel to oneanother,andso
theyadddirectly to the total gate-to-draincapacitance.
The overlap capacitor is usually modeledas a linear capacitance. Such a modelis
inadequate
for accuratesimulationsof clock feedthrough,because
this capacitance
is inherently
overlap capacitance
external fringing
fringing
bulk
Figure 6: Gate-to-drain capacitancecomponents
nonlinearoverpart of its biasrange[8]. Referringto Figure6, it is fairly obviousthat the overlap
capacitanceis a sort of p-channelMOS
capacitor. For gate voltages greater than the drain
voltage, the n+ surfaceis accumulated,
andthe effective overlapcapacitance
is just Co.~¢[_,,~,
whereZ,,~ is the extentof the overlap.Butif the gate voltagegoesbelowthe drain voltage, then
the surfacestarts to deplete,andCo~falls belowits valuein accumulation.
This effect is most
pronounced
in lightly-dopeddrain (LDD)devices;for conventionalhighly dopeddrains it is less
noticeable[8].
Modeling
of this effect from"first principles"is impossible.First, degenerate
dopinglevels are
often usedin the n+ diffusions. This rendersany simpleanalytical modelsfor MOS
capacitors
(basedon Boltzmannstatistics) invalid. Also, there is a steep horizontal gradient in the
substratedopingof the overlapcapacitor.At the edgeof the gate the dopinglevel is fairly high,
but the concentrationfalls sharply underneath
the gate, usually becoming
negligible after 0.5
l~m or so into the channel. It therefore seemsnecessaryto use an empirical modelfor the
overlap capacitance. Such a model has been presented by Lee and Rennick [13]. The
dependence
of the overlap capacitanceon the gate-to-drain voltage VGD
for this modelis shown
in Figure 7. This model has been implementedin the one-dimensional simulator. This
introducesfive newmodelparameters:Vocand~’t~,, describingthe voltagebreakpointson the
curveof Figure7; ~ocandZoc, whichdescribethe curvedpart of the capacitance
characteristic;
Coy, the value of the overlap capacitancedeepin accumulation;and Coc, the value of the
overlapcapacitance
at zero bias.
Theelectric fields inside the device become
quite curvednear the source. Thusit is not
12
VeD zXoc
OOOoo[’
- 7ooo1
’Coc
3
C = const.
I
-V
oc
0
VGD
V
th
Figure 7: Overlap capacitance model of Lee and Rennick
possible to directly
analyze the internal fringing fields in the one-dimensional simulator.
Although someexperimental studies of this capacitance have been published [9, 10, 19], there
does not yet seemto be enoughdata to define a model for its bias dependence.Cir. has been
neglected in the present version of the one-dimensionalmodel.
The external fringing capacitance C# is currently modeledas a linear capacitance. This
should be quite adequate--there does not seemto be any reason for it to dependon the bias
point.
Accurate evaluation of its value, however, requires a two-dimensional numerical
simulation of the exact gate and drain geometry; or, approximateanalytical models[5, 28] can
be used.
Finally, to allow for the modelingof processing asymmetries(especially those due to ° i on
implantation
shadows) the overlap capacitance parameters Coy and Coc, and the fringe
capacitances, maybe specified independentlyfor the source and drain.
2.5.2 Junction capacitances
The junction capacitances are represented by a simple power-lawcharge storage expression:
Qs = Q.~o[1 )+ VR/~S](~-~:
(11)
Here,~s is the built-in junction potential, VR is the reversebias acrossthe junction, and Qsois the
junction charge at zero bias. ms is the standardjunction law parameter;ms = 0.5 correspondsto
a step junction, while ms = 0.33 correspondsto a linearly gradedjunction.
Again, the source and drain junction capacitances maybe specified independently to model
processing asymmetries.
13
2.5.3 Terminal currents
The source and drain currents
1s and l D may be evaluated
with the Ward-Dutton
integrals [16, 33]. Although these integrals are normally used to derive quasi-static compact
models,their mostgeneral forms are useful in the non-quasi-static case as well. Equation(1)
integrated twice over the dummy
variable x’, first
betweenthe limits [0, x] and then between
[0, L]. (Here L is the length of the gradual channelregion.) An integration by parts is then used
to simplify the expressions,with the result
I s = (1/L I(x,t)dx
~) L ( 1-x/L)Q~(x,t)dx + ( 1- x/L) Jpu mp(X,t)dx
(12)
and
Becauseall horizontal currents weretaken as traveling to the left in Figure 4, I D enters the
drain terminal while ! s leavesthe sourceterminal.
Thegate current i G and the bulk current I B are defined as entering their respective terminals.
A single integration over [0, L] yields
IB = ~tf: Q~(x,t)dx + f: Jp.mp(x,t)dx
(14)
ApplyingKirchhoff’s current law to the entire device gives
I~ = - I~ -I D .+I
s
(15)
Equations(12) through (15) give the intrinsic
total
terminal currents these quantities
terminal currents per unit width. To obtain
are then scaled by the device width W and the
contributions due to the extrinsic elements(overlap and junction capacitances)are addedin.
It should be noted that in actual computation, the numerical approximations used for the
integration dictate majorsimplifications of (12) and (13), so that very little
to evaluate them. Only equation(14) for I~ requires a true integration.
workneedsto be
14
3 Numerical Methods
TwoC programshave beenwritten to exercise the one-dimensionalMOS
model. Thefirst
one(namedESIM)usesan explicit integration scheme
(the ForwardEuler method)for the
evolution of the model.This hasseveral advantages.
First, it is very easyto program,andthe
codeis easy to modify. Also, no large systemsof matrix equations needto be formulated.
Thereforeproblemswith the selection of goodpivots, or the nonconvergence
of the NewtonRaphson
algorithm,are avoided.Themaindisadvantage
of explicit integration is its conditional
stability (discussedbelow), whichforces the programto use very small time steps. This may
result in excessivelylongsimulationtimes.
Thesecondprogram(called FETuccine)
usesan implicit integration scheme
(trapezoidal)
the time evolution. This version of the codeallows muchlarger time stepsto be taken without
compromising
stability.
FETuccinehas beenfound to be nearly as robust as ESIM,and much
faster.
Bothprograms
are discussedin the following sections.
3.1 The ESIM(Explicit Integration) Program
Thegoverningequationsof the simulatormustbe discretized for computer
simulation. In this
work,a uniformgddof points xi = iz~L separatedby a distance~ is used.To simplify notation
in the followingdiscussion,the quantitiesqi = Qz(x~),~ = ~(~i), etc., are introduced.In the
code,equation(1) is discretized usingthe forward-time,centered-space
(FTCS)approximation:
qi(t+At)--qi(t)
Ii.1/2(t)
-
-/i_1/2(t)
+ Jpump,i(t)
(16)
whereAt representsthe time step. Notethat the horizontal currents are evaluatedat points
halfwaybetween
the majorgrid points. This results in the following differenceapproximation
for
(2):
Ii+1/~=t’te~xi+l/2)[-(1/2)(qi+~
+qi)~ ~i+~
+ - ~i
~7 qi+l
(17)
Eachgrid point xi hastwo valuesassociatedwith it: qi and~i. Thetwovaluesare related by
(6). This equationmustbe solved (by Newton’smethod)for eachchannelelementat each
point.
Equations
(16) and(17) are only valid at "internal" grid points (grid points with a neighbor
both.sides). At the endsof the channel("external" points) the boundary
conditionsexpressed
(9) mustbe imposed.This requires two moresolutions by Newton’smethod.
Finally, to generateterminal currents, equations(12) through(15) are applied. Given(16),
andassuming
that the trapezoidalrule is usedto performthe integrations indicated in (12) and
(13), it canbe shownthat massivecancellationsof termsin the discrete approximations
of the
integrals occur. Thusthe numericalintegration is "shorted out", andreducedto the following
expressions:
I s = (1- 1/4N)I1/2 (1/4N)IN_I/2 - A/,/(2At)[qo(t+At)-qo(t)]
(18)
and
(19)
1o =-(1/4N)Ivz (1-1/4N)lN_1/2
+ Z~L/(2At)[qN(t+At)--qN(t)
]
whereN + 1 is the total number
of grid points. Theonly numericalintegration that needsto be
cardedout is for (14). Thisis doneusingthe trapezoidalrule.
Thealgorithm usedin the ESIMprogramto updatethe one-dimensionalmodelat eachtime
point is nowgiven:
1. The mainprogramupdatesthe values of external sources and calls the onedimensionalmodelevaluationroutine.
2. Horizontal currents andchargepumping
currents are evaluated.
3. Explicit integration is usedto updatethe valuesof the inversion chargeat the
internalgrid points.
4. Theboundarycondition equationsare solvedby Newton’smethodto find Qzand¢
at the endsof the channel.At this point the currentsis andI Dmaybe computed.
5. Thesurfacepotentials, %are foundby Newton’s
method
for eachinternal point.
6. Theintegrals in equation(14) are evaluatedto determinethe current [B" Charge
conservation
is usedto find I
G.
7. Theone-dimensional
modelevaluator exits, returning the valuesof the terminal
currentsto the calling program.
It has already been.pointed out that the majordrawbackof ESIMis the instability of the
explicit integration scheme.It hasbeenfoundempiricallythat to ensurestability the time step
mustbe chosento satisfy
~t _<
to(VGs
-
(20)
Here, (Vcs-VT),,,, ~ is the maximumgate voltage drive (above the threshold voltage)
experiencedby the device. In a typical 5 Volt process, a 10#mdevice with its channel
partitioned into 10 elementsrequires At < 5 picoseconds,while a l#m devicewith 10 elements
requires z~t < 50 femtoseconds.Becauseof this requirement, CPUtimes for ESIMcan become
excessively long. This wasthe impetusfor the developmentof the implicit FETuccinecode,
whichis discussedin the nextsection.
3.2 The FETuccine(Fully Implicit) Program
In the FETuccine
program,the channelis divided into a numberof closed, one-dimensional
Gaussiansurfaces(see Figure 8): Thechargeprofile is approximated
by linear interpolation
Figure8: Spatial discretization scheme
in FETuccine
betweenthe meshpoints. Thus,the total chargeQ~nenclosedin the surface centeredat mesh
point xi (shownas the shaded
region in Figure8) canbe written
Qi = A[, [(l[8)qi_ 1 + (3/4)qi + (l[8)qi+l]
(21)
(A uniform grid spacing is used.) This approximationis moreaccurate than the FTCSscheme
usedin the ESIMcode(which amountsto a piecewiseconstant representation of the charge
profile.) Thereis verylittle
additional overhead
for usingthis scheme
in the FETuccine
program,
since the implicit integration scheme
alreadyrequiresthe useof matrixmethods.
Theenclosedchargegivenin (21) is then usedin the continuity equation:
o~t
(22)
(Thequantity ~" is the total interpolated chargepumping
current integrated over the Gaussian
surfacecenteredat xi. It is computed
with an expressionsimilar to (21).) Equation(22) is
discretizedin time with the trapezoidalrule. This results in a systemof nonlinearequationsin
17
the {q;} and {~;}.
This system of equations is then linearized and solved with the Newton-
Raphson method.
(The sparse matrix packagedescribed in [11] is used to solve the linear
equations.)
It should be pointed out that the straightforward current discretization of (17) mayresult
poorly conditioned matrices whenthe potential difference betweenneighboring grid points
exceeds2~r (see, e.g., [23, 29]). This can give rise to physically unreasonablesimulation
results, such as positive values of the electron charge Qz; in extremesituations it can cause
numerical oscillations.
Therefore the FETuccine program uses the well-known Scharfetter-
Gummel
discretization scheme[23] to avoid these problems:
- exp(Enorm)q
i
J[i+ l/2 -----
--]’l’/+If2
(23)
j~ qi~l : ~
whereE = (¢i+1 - ¢i)/z~L is the horizontal electric field and Enorm = ((~i+1 ddi)/#PT is a normalized
electric field quantity. For values of E,,o,,, muchless than unity, (23) reducesto the standard
finite difference approximation(17).
4 Experimental Procedures
In orderto correlate
simulation
resultswithphysical
reality, a test chipwasfabricated
in a
CMOS
3-t~m p-well technology through MOSIS.The chip includes a numberof charge injection
test structures, shownbelowin Figure
gate
init
~
t
DUT
init
Z
init
init
buffers
Figure9: Chargeinjection test structure
Thetest structure is quite similar to the one usedby Wilsonet aL [35]. Thecore of this circuit
is a versionof the archetypalpasstransistor circuit of Figure3, with infinite sourceimpedance.
Theunit capacitorvalue wasapproximately0.5 pF; capacitorratios of n = 1, 2, 4, and8 were
used.Thechip includedboth P andN test transistors of varioussizes, but dueto a layout error
only the largest devicesof eachtype wereavailable for testing. Thelargest N test device
measured120~mwide and 3 ~mlong, while the largest P device was 360~mwide and 3 I~m
long. Deviceswith minimum
lengths werechosen,since pass transistors are almost always
minimum-sized.Thewidths weremadelarge so that the resulting chargedumpswouldbe easy
to measure.
A direct measurement
of the chargeinjection errors with normallaboratory equipment
would
add large additional stray capacitancesto the source and drain nodes. To avoid this, the
voltages at these nodeswerebuffered with on-chip source-followercircuits (see Figure 10).
Thecommon-mode
input rangeof any follower is limited by saturation of the biasing current
sources. Thereforetwo complementary
buffers--oneusing NMOS
transistors for the input stage
andthe other using PMOS
transistors--were employed
to provide a rail-to-rail
effective input
range. For both buffers, two stageswereused; this keepsthe input capacitancelow, but still
allows themto drive large off-chip capacitive loads. Thechip also allowedthe transfer curves
andgain characteristics of the buffers to be measured;
thus, the amplifier nonlinearities were
calibratedout.
VDD
NBI~
/
,’
Figure10: Buffers usedto measure
chargeinjection
Thesubstrate chargepumpingeffect can be measuredin the following way: Thegate is
turnedoff with a relatively slowramp,andthe total chargeinjected to the sourceanddrain is
measured.
When
the turn-off time is very long, the electrons in the channelshouldhaveample
time to escapeto the source and drain, and so no charge will be pumpedinto the substrate.
The gate can then be turned off with a fast ramp; a decreasein the total charge injection at
source and drain indicates the amountof electron charge pumped
to the substrate.
As a check for this measurementscheme, the substrate currents were measureddirectly.
The NMOS
test devices were placed in the samewell, and the connection to this well was
brought out to a pad. The well connection was tied to the summingjunction of an external
op-ampintegrator (Figure 1 1). Any chargeentering or leaving the well addsor subtracts to the
charge on the integrating
capacitor, causing a corresponding change in the op-ampoutput
voltage. The positive input terminal of the op-ampis connectedto a voltage source; this allows
the well potential to be set to any desired value.
gate
"-~
Cint
O out
from well
O
Vwell
Figure 11 ." Schemefor measuring charge pumping
It should be pointed out that the well current involves two components;one due to the
electrons pumpedfrom the channel, and the other one due to the movementof holes. Transient
hole currents are induced in the well whenan NMOS
device turns off, becausethe depletion
layer beneath the channel shrinks suddenly. Holes must enter the well to cancel the excess
depletion charge. This charge can only comefrom the bottom plate of the integrating capacitor
of Figure 11, and therefore it addsto the measuredcharge. This is not a problem, since a slow
gate rampcan be usedin an initial
calibration step to determinethe hole component.
The structure of Figure 9 was exercised with a three-phase clocking scheme. In the first
phase, the transmission gates T1 and T2 are closed. This initializes
the value ~’i,~t.
the capacitor voltages to
Onthe second phase, the transmission gates are opened.The devices in the
transmission gates inject charge onto the source and drain nodesat this time; however, the
2O
resulting
errors do not significantly
affect
the measurementbecause the test device can
equilibrate the voltages at its source and drain before the third phasebegins. In the third, or
"test" phase, the device under test is switched off. Theresulting charge injection and charge
pumpingeffects can be observedat the outputs of the buffers, or the external op-amp,using an
oscilloscope. Thetesting cycle then repeatsitself.
For "slow" gate ramps, the gate voltages for the test transistors
external CMOS
inverter,
were supplied from an
with a fall time of approximately 50 nanoseconds.For "fast" ramps, a
TTL inverter (with an extra pull-up resistor) was used. The fall time was about 10 nanoseconds
in this case. For both ramps, the high value of the gate voltage was5 volts and the low value
wasapproximately 0 volts.
5 Results
In this section, the results of the one-dimensional model are comparedwith experimental
measurementson the test chip. Somecommentsare madeabout the experimental procedure.
Then the charge pumping model of the one-dimensional simulator
is evaluated through
comparisonswith two-dimensional PISCESsimulations. Finally, the need for a non-quasistatic
modelis investigated with one-dimensionalsimulations and quasistatic simulations.
5.1 Preliminaries
The model parameters for the simulators were derived from the parametric test results
supplied by MOSIS. (Data from the suggested SPICE parameters were avoided wherever
possible, however. These numbersare generated through a parameter extraction/curve-fitting
process which destroys mostof their physical significance.) The external fringing capacitance
was computed with the model of Greeneich [5],
angstroms. The substrate doping profile
assuming a poly gate thickness of 3800
was approximated as uniform; an equivalent doping
was computedfrom the body effect parameter. The results of this simple parameter extraction
processare given in Table 1.
The experimental devices are believed to use conventional drain implants, not LDD’s,
becauseof their relatively long channels(about 2 p~m). Usingthe data of Ishiuchi [8], the biasdependentoverlap capacitance parameters were selected; this resulted in a zero,bias overlap
Parameter
v~
t~//
fox
N,.
b
Value
-0.8722
1.364
483
1.356 x 1016
565
20
50
Units
Volts
#m
angstroms
cm-3
cm2/Volt-sec
Po
femtoFarad
C#
femtoFarad
Co,
,
Table 1 ; Modelparametervalues for simulators
capacitanceof 40 fF, tapering off to 35 fF at 5 volts reversebias.
The values for the capacitors in the test beds were derived from the MOSISdata for layerlayer capacitances. Parasitics due to wiring and diffusions were also factored into the total
capacitance.
5.2 Experimental Results
5.2.1 Chargeinjection
Figure 12 showsthe experimentalresults for the voltage errors induced by the turn-off of an
NMOS
device, using a capacitance ratio of 1:1. Error voltages are shownas a function of the
initializing
voltage Vi,it. (The error voltage decreases
with increasingV~,it since there is less and
less inversion charge present before turn-off).
Also shownare the one-dimensional model’s
predictions of the voltage error. Agreement
is within 8 millivolts across the full rangeof initial
voltages. (Experimentalerror is +/- 3 millivolts.)
In Figure 13, the voltage errors are comparedfor the capacitanceratio 1.4:1. (Dueto rather
large parasitics in the MOSISrun, the actual capacitanceratios differ substantially from the
designed ones; this ratio corresponds to n = 2.) The voltage errors shownare for the highcapacitance side. Agreementin this case is not as good; the maximum
difference betweenthe
two sets of data is 17 millivolts.
There are several possible reasons for the disparity
between the experimental data and
simulation results. First, the MOSIS
test data mustbe called into question. Thedevices usedin
the testing werequite wide, and so their junction capacitanceswerea large fraction of the total
drain and source capacitances. Knowingthese capacitancesis critical
for predicting the voltage
errors due to chargeinjection. But the only data available for junction capacitancemodelingare
22
-120
V~I’I*
(mV)
experiment
1-D
-180-
0
3
2
Vinit(Volts)
1
4
5
Figure 12: Voltageerrors for 1:1 capacitance
ratio
-50 -
-70-80 -90(mV)
/
-100 -
/
/
/
..
-110experiment
-120 -130 1-D
-140 -150 I
0
I
1
I
t
3
2
Vinit (Volts)
I
4
Figure 13: Voltageerrors for 2:1 capacitanceratio
the SPICE model parameters, which have undergonean optimizing parameter extraction
process. Thereforethey do not accuratelyreflect the junction voltagedependencies.
Another problem was the use of minimum-lengthtest devices. Lithographical errors of a few
tenths of a micron can substantially, changethe total channel lengths of these devices. Also,
errors in the lateral diffusion lengths cancausetoo muchor too little
of the gate to be interpreted
as overlap capacitance.
In future investigations of chargeinjection, it wouldbe desirable to give the experimenterthe
ability
to measurethe relative values of MOStransistor capacitances and junction parasitics
himself in order to calibrate
appropriate test structures
the measurementprocedure. This could be done by including
and probe points on the chip. Electron microscopy could be
employedto accurately determinethe geometrical parametersof the transistors.
5.2.2 Charge pumping
The injected
charge was measuredversus values of ~,,it
from 0 to 5 Volts, using the
measurementschemedescribed above. The experiments showedthat the total
charge pumped
to the substrate is muchless than the total inversion charge. Within the experimental accuracy
(which is on the order of 5 femtoCoulombs,
owing to the uncertainties in the relative values of
the drain and source capacitances), no changein the total charge injected at the source and
drain was observed when the gate fall
time was changed from 50 nanoseconds to 10
nanoseconds.
This result is in agreementwith the work of Wegmann
et aL [34], which indicated that the
percentage of the channel charge pumpedto the substrate should decrease rapidly
with
decreasesin the gate length of the passtransistor.
5.3 The Charge Pumping Model
Simulations with both PISCESand the empirical charge pumpingmodel indicate
the same
tendency of the pumpedcharge to decrease with shrinking gate length. They also indicate that
the pumped
charge is strongly dependenton the value of the initial
source/drain voltage T/i,it.
The charge pumpingcurrent from PISCESis shownin Figure 14 for a 2-~mdevice with Vi,it
0 Volts and a 2-nanosecondgate voltage fall
Changingthe initial
3.5x10-13 Amps.
=
time. The peak current is 3.5x10-1° Amps. -
voltage to 1 Volt results in a similar curve, but with a peak value of
24
3.5e-10 --
3e-10 --
PISCES
2.5e-10 Ipump
2e-10 -
1.5e-lO -
le-lO-
5e-11 -
0
0
5¢-10
le-09
1.5e-09
timc (see)
2¢-09
I
2.5e-09
"’i
3e-09
Figure14: Chargepumping
currentsin PISCES
and1-D simulator:
2-micror~device
Thedecreasein the pumped
chargewith larger V~,,~t is believedto be causedby the increased
potential barrier betweenthe substrateand the channel.The sourceand drain junctions
become
moreattractive to electrons than the substrate, becausethey are at a morepositive
potential.
Thesubstrateelectroncurrentfromthe one-dimensional
modelis also shown
in Figure14
(dottedline). Theone-dimensional
modelparameters
re,,, e andVe,,m
e weretreatedpurelyas
fitting parameters
andadjustedto give a reasonable
fit to the PISCES
data. Thecurveshown
usedtp,me= 7.83 nanoseconds
andVp,,,~ = 50 millivolts (roughly2¢r). Thetotal charge
pumped
to the substratein PISCES
is 1.56x1019 Coulombs;
the total chargepumped
in the
"2° Coulombs.
empiricalmodelis 8.68x10
IncreasingVi,it to 1 Volt, andkeepingthe model
parameters
the same,resultedin a peaksubstratecurrentof 1.1 x10"11 Amps
in the empirical
model.Thisis much
lowerthanbefore,butnot as smallas PISCES
predicted.
Thedifferencesbetween
the twoprograms’results will be discussedbelow.To showthe
effectsof channel
lengthin the twosimulators,the substratecurrentsfor a 10-1~m
deviceare
25
plotted in Figure 15. Thetotal chargepumped
to the substrate greatly increases in both: for the
one-dimensional
model, it
grew to 1.92 femtoCoulombs, and in PISCES, to 37.7
femtoCoulombs. (The charge pumping model parameters were the same as for the 2-1~m
device.)
6e-05 -
5e-05 -
4e-05 -
PISCES
Iparap
3e-05-(A)
1-D
2.e-05--
le-05 --
0
}
0
5e-10
le4)9
1.5¢-09
time (see)
2¢-09
2.5e-09
3e-09
Figure 15: Chargepumpingcurrents in PISCESand 1-D simulator:
1 O-microndevice
The differences betweenthe two simulators’ results can be attributed to one the fundamental
assumptions of the one-dimensional model: the charge sheet approximation. It was assumed
at the outset that electrons remainedtrapped at the oxide interface in a sheet of negligible
thickness.
The one-dimensional model treats
charge pumping as a minor effect
transports someelectrons away from the inversion layer without seriously affecting
distribution.
which
this
To see howgood this approximation is, PISCESwas used to computethe location
of the electrons’ center of mass(centroid) relative to the oxide interface during a chargepumpingtransient.
The result is shownbelow in Figure 16. The centroids were computedat
the center of a 10-1~mdevice, switching off in 2 nanoseconds,with Vi,lt = 0 Volts. Also shown
is the location of the depletion edge. At t = 2 nanosecondsthe gate voltage reaches 0 Volts,
and the electron centroid has movedout past the depletion region edge. This indicates that the
26
charge sheet approximationstarts to fail badly whenstrong charge pumpingtakes place.
0.’7
’...Depletion edge
0.4-
Position
~rn)
Centroid
0.3n
0.2n
/
0
0.5
1.5
Time(nsec)
1
2
2.5
3
Figure 16: Electron centroid and depletion edge versus time
5.4 The Need for a Non-Quasistatic Model
Analog designers are most interested in simulating charge injection
devices. Pass transistors
are invariably
in minimum-length
madeas short as possible so that the switch’s
conductancecan be maximizedwhile its area (and hence, its charge dump)is minimized. From
a knowledgeof the behavior of distributed circuit elements,such as transmissionlines, it seems
reasonableto expect that non-quasistatic effects wouldbe minimizedin a very short device. It
is therefore natural to wonder whether a non-quasistatic
model is really
necessary for
simulations of such devices; might a quasistatic modeldo just as well?
This question is investigated by comparingthe predictions of the one-dimensionalmodelto
those of the Berkeley Short-channel IGFETModel (BSIM)[26, 27], as implemented in the
program HSPICE[7].
In BSIM, capacitances
are derived from the charge-based Ward
model[16, 33]. Paulos [18] has shownthat the Wardmodel is "first-order
whereasthe Meyermodel [15] (which is still
quasi-static.
used in manycircuit
non-quasistatic",
simulators) is completely
Thus it is expected that the Wardmodelwill perform better than previous SPICE
modelswhensimulating fast transients. In all the simulations, the "charge partitioning"
flag
XPART
was selected so that in saturation, 40%of the channel charge is lumpedat the drain,
and 60%at the source. Although other partitioning ratios are sometimesused, this is the ratio
predicted by rigorous application of the Wardmodel.
BSIMand the one-dimensionalmodelwere used to simulate charge injection in the circuit
of
Figure 9 with n = 8 from V~,it = 0 Volts to 5 Volts. The transistor’s channel length was2 ~tm.
The result is shownbelow in Figure 17. The maximum
difference betweenthe two sets of data
is 2.5 millivolts.
Excellent agreementbetweenthe two simulators was retained across the whole
range of capacitance ratios considered (n = 1, 2, 4, 8), with a maximum
difference of 2.9
millivolts.
-30 .40-50 .-60-70 V~IT
(mY)
-80 -90-I00~
-110 1-D
-120 -130 ~
BSIM
-140 I
0
I
]
I
I
2
3
Vinit (Volts)
I
4
I
5
Figure 17: BSIMversus the 1-D modelfor a short device: capacitance ratio 8:1
In another test, the error voltage waveforms
wereplotted for the circuit of Figure 1. To stress
all the transient aspects of the models, three input voltage waveformswere used. First, the
input voltage was held constant as it was sampled; then, the input voltage was changedto a
fast rising ramp (+1 Volt/nanosecond), and a fast falling
circuit
ramp (-1 Volt/nanosecond). Other
parameters were chosen to matchthe experiment of Park et aL [17], who simulated the
98
samecircuit with their ownnon-quasistaticmodel.In all three casesthe input voltagestarted at
10 Volts; the gate voltage rampeddownfrom 20 Volts to 0 Volts in 2 nanoseconds.
A channel
length of 3 #mwasused. Theoverlap and fringe capacitanceswerezeroedin both simulators.
Thewaveformsare shownin Figure 18: BSIMresults are shownwith a solid line, and onedimensional modelsresults with a dotted line. The agreementis still
good: a maximum
discrepancy
of 2.7 millivolts is observed.
20-
OWns
-80-
o120-1 V/ns
-180
-200 |
0
5e-10
le-09
1.5e-09
Time(see)
2e-09
2.5e-09
3e-09
Figure18: Error voltagefor the sampled
ramptest (after Parket al.)
Finally, a comparison
of the predictederror voltagesis shownin Figure 19 for a relatively
long-channeldevice(L = 10 #m). All other conditions are the sameas those in Figure 17. The
differencesbetween
the twosimulatorsare nowquite significant.
6 Conclusions
This report has presenteda one-dimensional
non-quasistaticmodelfor the MOS
transistor.
The performanceof this modelhas been explored through experimental measurement
and
comparisonwith other simulators. The experimental data does not showoverwhelming
agreementwith the modelacross a range of different capacitance ratios. In subsequent
studies, more work should be done to characterize the actual device geometries and
o
-50
-100 -150 -200-250 (mY)
-300-350 -4.00-450 -500 -550 -
0
l
2
3
Vinit (Volts)
4-
5
Figure 19: BSIMversusthe 1-D modelfor a long device: capacitanceratio 8:1
capacitance values on the test chip; this would help to determine whether the discrepancies can
be attributedto physical effects that are not being modeled,or to inaccurate input data.
The possibility of modelingthe substrate chargepumpingeffect with a simple diode-like
substrate current modelwasinvestigated. It wasfoundthat serious problemsbegin to occur
whenthe chargepumpingbecomes
significant, becausethe chargesheet approximationbreaks
down.
The needfor a non-quasistaticmodelin the simulationof chargeinjection wasstudied. The
results seemto indicate that short devicesoccupya "sweetspot" wherequasistatic modelscan
still be usedwith goodresults. For longer devices, the quasistatic approximation
is no longer
good enough: the disturbance from equilibrium becomessignificant,
effects are important.
and charge pumping
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A charge-sheetmodelof the MOSFET.
Solid-StateElectronics,vol. 21, pages345-355,1979.
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J. S. BruglerandP. G. A. Jespers.
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MEDUSA--A
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J. E. Meyer.
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H. J. Park, P. K. Ko and C. Hu.
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J. J. Paulosand D. A. Antoniadis.
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